Experiment 7 Digital Logic Devices and the 555-Timer

Transcription

1 Experiment 7 Digital Lgic Devices and the 555-Timer Purpse: In this experiment we address the cncepts f digital electrnics and lk at the 555-timer, a device that uses digital devices and ther electrnic switching elements t generate pulses. Equipment Required: Vltmeter (Rensselaer RED2 IOBard) Oscillscpe (Rensselaer RED2 IOBard) Functin Generatr (Rensselaer RED2 IOBard) +4V (+Vcc) Pwer Supply (Rensselaer IOBard, n RED2 be sure t use V+ and GND) 555-Timer,7402, 7404, 7410, 7414, 74107, ICs Helpful links fr this experiment can be fund n the links page fr this curse. Part A Basic Lgic Gates Backgrund Digital lgic gates: All digital lgic gates are based n binary lgic. Binary lgic has tw values, called TRUE and FALSE, LOGIC 1 and LOGIC 0, ON and OFF, r HIGH and LOW. The crrespnding binary number can have tw pssible values, 1 and 0. Digital lgic gates perfrm many cmmn lgic peratins n binary signals, such as AND, OR, NOT, NAND, and NOR. The table in Figure A-1 cntains the cmmn symbl fr each type f gate, an expressin fr the functin f the gate in Blean algebra, and a truth table fr the device. The truth table shws hw the gate will behave fr all pssible cmbinatins f digital inputs. Figure A-1. K.A. Cnnr, S. Bnner, P. Schch - 1 -

2 Figure A-1 (cntinued). Digital lgic chips: In TTL (transistr-transistr lgic) digital electrnic circuits, the representatin f binary numbers in terms f vltages is abut 5V fr LOGIC 1 and abut 0V fr LOGIC 0. Abut 5V usually means a vltage between 2 and 5V while abut 0V means any vltage in the range 0 t 0.8V. The vltage levels when using TTL devices must always be in the ranges indicated r the circuits will nt functin crrectly. LOGIC 1 and LOGIC 0 are the nly utput levels ne shuld see with lgical devices. This is ne characteristic that makes them differ frm analg devices. They als switch very fast frm ne state t the ther. Switching speeds are usually much faster than fr analg devices, especially cheap devices like the 741 p-amp. A digital chip generally has 14- r 16-pins. It usually cntains mre than ne f the same lgic gate. (Fr example, a 14-pin chip will have six single-input gates r fur 2-input gates.) By cnventin, the upper right pin n a digital chip is always cnnected t HIGH (+Vcc) and the bttm left pin t LOW (0V). Vcc is usually either +4V r +5V, depending n what supplies are available. Mst lgic chips will perate ver a range f supply vltages. On a 14- pin chip this crrespnds t pin 7 (0V) and pin 14 (+Vcc) and n a 16-pin chip, pin 8 (0V) and pin 16 (+Vcc). These tw cnnectins prvide reference values fr the peratins the chips perfrm. Generally circuit diagrams d nt shw these tw reference cnnectins. If yu frget t cnnect these tw pins, yur circuit will nt functin. Timing diagrams: Timing diagrams are a special kind f transient utput which are useful fr viewing many binary signals. Since the vltage levels f binary signals can nly be either high r lw, knwing the exact vltage level is nt as significant as knwing when the different signals transitin frm high t lw (r lw t high). A timing diagram is much easier t read when yu need t cmpare many binary signals. Unlike a regular PSpice plt (where all signals are displayed with the same vltage and time axis) a timing diagram displays the signals n separate lines with the same time scale. A sample is shwn in Figure A-2. K.A. Cnnr, S. Bnner, P. Schch - 2 -

3 Figure A-2. Nte that there are six signals shwn n this plt. We can see where they are high and lw and we can als see the relative time that each signal changes state. Experiment Truth Tables f Basic Lgic Gates We will nw cnsider three basic lgical elements: a tw input NOR gate, a three input NAND gate and an INVERTER. Wire the circuits in Figure A-3 n yur prtbard. D nt frget t tie pin 14 t +Vcc (4V) and pin 7 t 0V (GND) n each chip. (Als nte that the chip and the 7410 chip in yur kit are nt the same chip. We want the 7410 here.) Digital Ch U1A 1 Digital Ch Digital Ch 2 Digital Ch U2A 12 Digital Ch U3A Figure A-3. Digital Ch 6 Set Digital Ch 1, 2 and 3 t Output and set Digital Ch 4, 5, and 6 t Input by clicking n the Input r Output label. Figure A-4. Cnsider all pssible cmbinatins f inputs t generate a truth table fr each device. The NOT gate has nly ne input. Therefre, we need nly need t bserve the utput when the input is HIGH (Vcc) and LOW (0V). First set channel 1 t high (green) and recrd the status f channel 6. Then set channel 1 t lw (red) and recrd the status f channel 6. Des the gate invert the input? K.A. Cnnr, S. Bnner, P. Schch - 3 -

4 Take a picture (screen capture) f ne f the input/utput cmbinatins. Draw a truth table fr this gate n the utput plt. Include this plt in yur reprt. Nw yu will repeat this prcess fr the ther tw gates. The NOR gate has tw inputs, s we must bserve the utput at pin 1 (Digital I/O channel 4) fr all pssible cmbinatins f binary inputs at pins 2 and 3: (LOW, LOW), (LOW, HIGH), (HIGH, LOW) and (HIGH, HIGH). Take a picture (screen capture) f ne f the input/utput trace cmbinatins. Recrd the truth table n the plt. Include this plt in yur reprt. The NAND gate has three inputs. Hw many cmbinatins f HIGH and LOW are required t fully test this gate? Recrd the input and utput fr this gate in a truth table n a sample screen capture, as well. Include this plt in yur reprt. Simulatin f Basic Lgic Gates We will nw wire the same three basic lgical elements using PSpice. Create the fllwing circuit (Figure A-5) in PSpice. Figure A-5. Wiring the circuit in PSpice is smewhat different than n the prtbard. PSpice assumes that the +5V and 0V references have already been wired, s yu d nt need t make these cnnectins. We cannt simply mve the wires t recrd all pssibilities. Therefre, we use digital clcks with different pulse lengths t create the signals we need t test the gates. We have remved the resistrs cnnecting the gate utputs t grund. This tells PSpice t utput timing diagrams by default. Nw we need t set the clcks up t wrk with different pulse lengths. Use DigClck in the SOURCE library Use the default settings fr DSTM1 (n delay, n time = 0.5us, ff time = 0.5us). Fr DSTM2, duble the n and ff times t 1us. Fr DSTM3, duble them again t 2us. Run a simulatin Simulate fr 8us with a step size f 0.01us. Display all the inputs frm the clcks and the utput f each f the three gates. Prduce a hardcpy f the timing diagram with the inputs and the utputs fr all three gates. Mark the utput trace fr each gate n the diagram. Fr each gate, generate the truth table fr the device based n the utputs and inputs yu bserve n the timing diagram. Write them n the utput plt. Include this plt in yur reprt. D yur results agree with the truth tables yu fund using frm the circuits yu built? K.A. Cnnr, S. Bnner, P. Schch - 4 -

5 Summary Basic lgic gates allw yu t use electrnic signals t perfrm peratins n digital signals. They can als be cmbined t perfrm mre cmplex peratins, such as additin and subtractin. This makes them a basic building blck f digital cmputers. Part B Flip Flps Backgrund Flip Flps: It is pssible using basic lgic gates t build a circuit that remembers its present cnditin. These circuits are called flip flps. The PSpice symbl fr a JK flip flp is pictured in Figure B-1. There are several different kinds f flip flps with slightly different characteristics. In this curse we use the JK flip flp. JK flip flps, like ther flip flps have fur inputs, tw utputs and the usual tw pwer cnnectins (V CC and grund). The utputs are labeled Q and Q (als called Qbar and NQ). They are cmplements f ne anther. Thus, when Q is LOW, Qbar is HIGH, etc. CLK is the digital clck. A flip flp nly changes its utput when the clck pulse at CLK ges frm HIGH (+Vcc) t LOW (0V). This is called the falling edge f the clck. The input CLR, when LOW, will reset the utputs t a knwn state. It has the fllwing truth table: Figure B-1. Nte that the flip flp is an edge-triggered device. This means that instead f changing state as sn as its inputs change, it waits until it receives a falling edge at the clck input (CLK). T decide hw t set the utput, the flip flp lks at the values at the inputs at J and K AND at the current value f the utput. Based n these three values, it decides hw t reset the utput. Yu may be familiar with clcks. They are used t crdinate the instructins perfrmed by the CPU and ther devices in a cmputer. When a cmputer has a clck speed f 1GHz it can handle instructins per secnd; ne fr every clck cycle. The flip flp wrks n the same principal. With every clck cycle, it lks at its inputs and changes state accrdingly. The flip flp is a memry device. If bth inputs are zer, its utput will remain the same indefinitely. A bank f 4 flip flps can stre a digital byte f memry in a cmputer. If yu want t change the value f a single bit f that byte t zer, yu can set the inputs t the crrespnding flip flp t J = 0 and K = 1. On the next clck cycle, the utput will change t zer. If yu want t change a single bit f the byte t ne, yu can set the inputs f the crrespnding flip flp t J = 1 and K = 0. On the next clck cycle, the utput will change t 1. Yu can als tggle the value f the flip flp utput by setting bth inputs t 1. Timing diagram fr a flip flp: T illustrate the behavir f a JK flip flp, we wired the circuit in Figure B-2 in PSpice and created the timing diagram shwn in Figure B-3. K.A. Cnnr, S. Bnner, P. Schch - 5 -

6 DSTM1 CLK DSTM2 CLK DSTM3 CLK J Q CLK Q K CLR 13 U1A DSTM4 CLK Figure B-2. Figure B-3. DSTM2 is the clck. Each time the clck falls, lk at the values f the inputs at J (DSTM1), K (DSTM3), and the utput signal (U1A:Q). If the truth table is crrect, what shuld the utput value at U1A:Q be fr each cmbinatin? Is the timing diagram crrect? Please check the datasheet fr the SN74107 flip flp lcated n the curse web page fr details abut this device. Nise and Digital Circuits: Any time yu build a circuit, there will be nise. In an edge-triggered device, where timing is a factr, nise can cause many prblems. A nise spike might be interpreted as the falling edge f the clck. If this happens, the flip flp will change state at the wrng time and pssibly with the wrng inputs. T avid this prblem, it is essential t use a bypass capacitr in every timed digital circuit yu build. A bypass capacitr is simply a capacitr placed between the surce vltage and grund. What it des is filter ut high frequency nise, s that any spikes that might be misinterpreted are filtered ut. Figure B-4 shws a bypass capacitr. V+ GND Figure B-4. T understand hw the bypass capacitr wrks, we nly need t recall that a capacitr lks like an pen circuit at lw frequencies and a shrt at high frequencies. Digital signals cnsist f tw DC values, 0V and +Vcc. A DC vltage has zer frequency. Therefre the bypass capacitr will lk like an pen circuit and all f the DC signal will pass int the circuit. A nise spike is a very sudden high frequency event. At high frequencies, the capacitr lks like a shrt. Therefre, the high frequency event will pass thrugh the capacitr t grund and nt cntinue n int the circuit. When a signal changes frm lw t high (r high t lw), the temprary nise f the transitin may cause the device t make the wrng utput decisin. Since the values f the inputs, as they are changing, are indeterminate, the utput that a flip flp will generate if the inputs are changing is unknwn. In PSpice, this unknwn state is depicted by a duble red line. If yu lk at the timing diagram abve yu will see that bth Q and Qbar start ut in an unknwn state until the first falling edge f the clck. Als ntice that the transitins fr J and K take place well befre the falling edge f the clck. We deliberately set up the timing f DSTM1 and DSTM3 s that they d nt change the state f the input at the same time the clck transitins frm high t lw. If we had, PSpice wuld cntinue t display the duble red line, signifying that it cannt prperly set the utput because it isn t sure what the inputs are suppsed t be. K.A. Cnnr, S. Bnner, P. Schch - 6 -

7 Experiment The JK Flip Flp In this part f the experiment, we will lk at the behavir f a flip flp n yur prtbard. Set up the JK flip flp n the prtbard. Prvide 0V at pin 7 f the chip and +Vcc t pin 14. Place a 0.1uF by-pass capacitr between 0 and +Vcc. Use three Digital I/O channels t create the J, K, and Clck signals. These shuld be set as utputs Use 2 Digital I/O channels t read the Q and Qbar signals. These are set as inputs. Set the CLR t zer t be sure that the flip flp begins in a knwn state. THEN attach it t +Vcc t enable the functin f the chip. (Or use yet anther Digital I/O channel as an utput and cycle it lw and then high.) Run all pssible cmbinatins f lgic levels fr J and K (see belw). Each time yu change J r K, yu need t cycle the Digital I/O that is the Clck signal. This means t make the changes in J and/r K and then switch the clck frm lw t high and then back t lw. By mnitring the Q utput, yu shuld be able t cmplete the table belw. It may take a little thught. Fill in the fllwing truth table fr this device. Yu will nt be able t fill in the table in rder. Yu will need t skip arund depending n the current state (befre pulse) f the flip flp. Q (befre pulse) J K Q (after pulse) Qbar (after pulse) Take a screen capture f the Digital I/O status fr the case when J and K equal t 1. Label each Digital I/O channel used with J, K, Clck, Q and Qbar. Cpy the truth table abve fr the flip flp nt a print ut f the Digital I/O status screen capture. Include this plt in yur reprt. Summary The JK flip flp is an edge-triggered device that uses an external clck t crdinate state changes with ther clcked devices in a circuit. It is capable f hlding its utput stable, changing its utput directly t high r lw, r tggling the utput t the ppsite f its current value. It can be used as a memry device r as a building blck t create mre cmplex devices, such as cunters. Part C Cunters Backgrund Binary Cunters: JK flip flps can be cnnected in a cunter cnfiguratin as shwn in Figure C-1. The utput f each flip flp is used as the input clck t the next flip flp. On all flip flps, J and K are tied high. This means that they will tggle n each pulse f their clcks. The first flip flp tggles every clck cycle. The secnd flip flp K.A. Cnnr, S. Bnner, P. Schch - 7 -

8 tggles every time the utput frm the first flip flp changes. This causes it t tggle at a rate equal t half f the clck rate. By the same reasning, the third flip flp tggles at a rate ¼ f the clck rate. Figure C-1. If we attach a bit f a binary number, (b0,b1,b2), t the utput f each flip flp (b0 t the first, b1 t the secnd, and b2 t the last). We get a pattern ut which crrespnds t the binary cunting shwn in Figure C-2 belw: Figure C-2. The lwest rder bit f the binary numbers tggles frm 0 t 1: ( ). The secnd rder bit als tggles between 1 and 0, but at half the rate: ( ). The third rder bit tggles als, but at half the rate f the previus bit: ( ). The pattern in the table is the same as the pattern created by the cascaded set f flip flps. Thus, the cunter is cunting. It is nt necessary fr us t cnfigure several flip flps t create a cunting circuit, because this is already dne in many kinds f chips. The SN74393, fr example, has tw sets f fur JK flip flps cnnected as binary cunters. Light Emitting Dides: LEDs (light emitting dides) are very useful when dealing with digital circuits. Because they have tw states, ON and OFF, yu can hk them t a binary signal, and use them directly t bserve whether r nt the signal is HIGH r LOW. Althugh there are cnventins fr the plarity f dides, many manufacturers d nt seem t fllw them. The best way t determine the plarity f a dide is t place it directly between +Vcc and grund (with a series resistr). If it lights, use it in that directin. If it desn t light, try switching the plarity. If it lights that way, then use that plarity. If it lights in neither plarity, thrw it away. It is burnt ut. LEDs are like light bulbs. They burn ut after a while. In rder t prlng the life (and brightness) f an LED, it is a gd idea t wire it in series with a small resistr (330 hms is abut right). If the LED is nt bright enugh, yu can replace the resistr with a smaller ne. Experiment Simulatin f a cascaded binary cunter In this part f the experiment, we will use PSpice t create a simulatin f tw cunters cascaded tgether. This will allw us t cunt t numbers greater than 15. Simulate the circuit in Figure C-3 in PSpice. K.A. Cnnr, S. Bnner, P. Schch - 8 -

9 OFFTIME = 0.5uS DSTM1 ONTIME = 0.5uS CLK DELAY = STARTVAL = 0 OPPVAL = 1 1 A U1A QA 3 QB 4 QC 5 QD 6 CLR V V V 13 A U1B QA 11 QB 10 QC 9 QD 8 CLR V V V V V V V OFFTIME = 45uS ONTIME = 0.5uS DELAY = 0.7u STARTVAL = 0 OPPVAL = 1 DSTM2 CLK Figure C-3. DSTM1 is the actual clck fr the cunter, DigClck in SOURCE library with OFFTIME = ONTIME = 0.5us. DSTM2 (als DigClck) is set up s that it first clears the cunters, lets them cunt, and then clears them again. (OFFTIME = 45us, ONTIME = 0.5us, DELAY = 0.7us) If the PSpice mdels fr cunters r flip flps are nt cleared initially, they will have indeterminate data. By cnnecting the tw cunters tgether as shwn, the sequence f numbers 2QD, 2QC, 2QB, 2QA, 1QD, 1QC, 1QB, 1QA (IN THAT ORDER) frm the binary number. Since the cunter is set up t cunt clck pulses, it will cunt up frm 0 (at reset) t the number f pulses sequentially. Run the simulatin. Generate the utput fr this circuit fr time 0 t 100us using 1us increments. Yu shuld display the reset pulse, the input clck at pin 1 f U1A, and all eight f the cunter utputs (QA, QB, QC, QD fr bth cunters, selected in rder frm mst significant t least significant bit). Using the timing diagram, verify that the cunters are actually cunting. Yu can use the cursr t easily get yur binary number. The binary value is displayed n the left by the y-axis. What is the highest number it cunts t befre it resets? Express this number bth as a binary number and a decimal number. At what time des it reset? Write it n the timing diagram fr the circuit. Hw many pulses will the clck have t cycle thrugh between the time it is reset and when it hits its maximum value f ? Include the timing diagram utput in yur reprt. Build a cunter circuit In this part f the experiment, we will build a cunter circuit n the prtbard. Build the circuit in Figure C-4 n yur prtbard. LEDs D1 R1 220 Input frm AWG1 (RED2) U3A A U4A QA 3 QB 4 QC 5 QD 6 CLR D2 D3 D4 R2 220 R3 220 R4 220 Figure C-4. The Schmitt trigger inverter cleans up the signal frm AWG1. Dn t frget that the 74LS14 and the 74LS393 bth need pwer and grund. 0 Use the functin generatr fr the clck. Set it fr a square wave with a frequency f 20Hz. We are using a fairly lw frequency s that we will be able t see the switching with the LEDs. Use the ffset feature t shift the square wave up such that it cycles between 0V and 4V. With the RED2 IOBard, setting the ffset K.A. Cnnr, S. Bnner, P. Schch - 9 -

10 t 2V and the peak-peak vltage t 4V will utput the required signal. Be sure that yu use the scillscpe t check the peratin f the functin generatr. Tie pin 7 t grund and pin 14 t +Vcc n bth the 74LS14 and the 74LS393 lgic chips. Place a 0.1uF by-pass capacitr between +Vcc and grund. Check yur LEDs by cnnecting ne with a 220 Ohm resistr between +Vcc and grund t see which plarity causes it t light. Place it in the circuit with the crrect plarity. Usually the lead n the flattened side f the case ges t grund. If yu cannt find 220 hm resistrs, use nes clse t 220 hms. Set the CLR t +Vcc t be sure that the cunter begins cunting at zer. THEN attach it t 0V t enable the chip t functin. Nte that this is the ppsite f the flip flp. The circle at the input t the clear tells yu whether the CLR signal must be high r lw. (Circle Hld high t disable clear & enable cunting. N Circle Hld lw t disable clear & enable cunting.) If yu tie this pin incrrectly, the chip will cntinuusly reset itself and will nt wrk. Once yu have the circuit wrking, bserve the utput. Are they changing at the expected rates? Change the functin generatr frequency if it helps yu determine the frequencies. Place channel 1 f the scpe n the clck signal and set the time cntrls s that it displays 50 clck cycles. D nt change the time scale as yu take yur pictures. All fur shuld shw 50 clck cycles fr cmparisn purpses. Yu will need t take fur pictures using Mbile Studi. Include them in yur reprt. Channel 1 = clck and Channel 2 = QA Channel 1 = clck and Channel 2 = QB Channel 1 = clck and Channel 2 = QC Channel 1 = clck and Channel 2 = QD What d yu bserve abut the rates f the different signals with respect t the clck? Can yu tell which utput crrespnds t which bit in the binary number? Keep this circuit fr part D. Part D The 555-Timer Backgrund The 555-Timer: The 555-timer is a chip that allws us t create a variety f useful digital and analg signals. Much like the p-amp, it can be used t perfrm different functins depending upn what circuit yu place it int. The 555-timer can be used t generate digital pulses. When it is wired as a ne-sht (als called mn-stable mde), it generates a single, clean, digital pulse at the utput, when it experiences a (pssibly nisy) pulse at the input. This is useful when de-buncing a mechanical switch. In this experiment, we are cncerned with the 555-timer when it is wired in astable mde. This is als called an astable multivibratr. In this mde, the 555-timer circuit creates a stream f regular pulses. The wiring diagram fr the 555-timer in astable mde is shwn in Figure D-1. K.A. Cnnr, S. Bnner, P. Schch

11 1 Freq = T + T 1 2 Figure D-1. Inside the 555-Timer: In rder t understand hw the 555-timer can create this regular stream f pulses, we need t lk inside and see hw it functins. As yu can see in Figure D-2, the inside f the device cntains many f the cmpnents we have studied in experiments 6 and 7. Figure D-2. First nte that there is a vltage divider alng the left side f the diagram. This divides a DC surce vltage at Vcc int three equal vltages. Therefre, P1 is equal t (2/3)Vcc and P2 is equal t (1/3)Vcc. Next t the vltage divider, there are tw cmparatrs. The Threshld Cmparatr cmpares the vltage at pin 6 (the Threshld) t the vltage at P1. Since the Threshld is at the nn-inverting input, the cmparatr will saturate high when the Threshld exceeds P1. The Trigger Cmparatr cmpares the vltage at pin 2 (the Trigger) t the vltage at P2. Since the Trigger is at the inverting input, the cmparatr will saturate high when the Trigger dips belw P2. The utputs f these tw cmparatrs are used t cntrl a flip flp. (Yu may als see an RS flip flp here, but we have used a JK flip flp because that is the ne yu are familiar with.) When the Threshld cmparatr utputs a high signal, the K input is high and the utput f the flip flp ges lw. When the Trigger cmparatr utputs a high signal, the J input is high and the utput f the flip flp ges high. The utput f the flip flp is attached t the 555- timer chip s pin 3 (Output). The 555-timer chip has ne mre feature, a transistr switch. This switch will be ff when the Output pin is high and the signal at pin 7 (Discharge) will nt be influenced by the switch. When the Output pin 3 is lw, hwever, the transistr switch is clsed. This frces the Discharge pin t grund. The 555-Timer in Astable mde: When we wire the 555-timer in astable mde, we create a circuit that generates a string f pulses with the same perid and duty cycle. The nature f these pulses is determined by the values f the R1-R2-C1 K.A. Cnnr, S. Bnner, P. Schch

12 cmbinatin n the utside f the timer in the diagram fr Basic Astable Mde n the previus page. We have seen that when current flws thrugh a series cmbinatin f a resistr R and a capacitr C, that the circuit respnds with a characteristic time cnstant τ = RC. The n-time fr each pulse is determined by hw fast the capacitr C1 charges when the transistr switch is pen and the utput f the timer chip at pin 3 is high. In this case, the capacitr is attached t the surce vltage thrugh the resistrs R1 and R2. The charging time cnstant is τ charge = C1(R1+R2). When the capacitr has charged up t (2/3)Vcc, the Threshld Cmparatr saturates high, the flip flp switches, the utput ges lw and the transistr switch clses. The ff-time fr each pulse is determined by hw fast the capacitr discharges t grund thrugh the transistr. The discharge path is thrugh R2 t pin 7 t grund, s the discharging rate is τ discharge = C1(R2). When the capacitr has discharged dwn t (1/3)Vcc, the Trigger Cmparatr saturates high, the flip flp switches, the utput ges high, the transistr pens, and the capacitr is n lnger attached t grund at pin 7. The capacitr begins t charge again and the cycle repeats. By selecting just the right values fr the resistrs and capacitrs in this circuit, we can make the vltage at pin 3 (the OUTPUT) g frm zer t V CC at whatever rate we desire. We can als cntrl the percentage f time that the utput will be n relative t the length f an entire cycle. The equatins that gvern this behavir are: T ON = 0.693( R1 + R2) C1 T OFF = 0.693( R2) C1 f = T ON 1 + T OFF 1.44 = ( R1 + 2R2) C1 Pulse width mdulatin: One f the mst imprtant things we can use 555-timers fr is t cntrl and drive a large variety f systems with pulse width mdulatin. Please read ver the links n mtr cntrl and flw valve cntrl n the curse links page. The pwer f pulse width mdulatin cmes frm its simplicity. Rather than cntrlling the flw f sme liquid by carefully pening a valve part way, yu can alternately pen and clse the valve fully in such a manner that the average pen time prduces the same effect as a partially pen valve. In effect, the rate f flw is cntrlled by the duty cycle f the cntrlling vltage. It is much easier t fully pen r clse a valve than t precisely pen it part way. One can als apply pwer t a mtr in this manner t cntrl the speed f rtatin. The key gal f this mdulatin prcess is t achieve a desired average value fr sme prcess. The range f pssibilities is shwn in Figure D-3 where A has a high duty cycle (fast) and C a lw duty cycle (slw). Experiment Figure D-3. Simulatin f a 555-timer circuit In this part f the experiment, we will use PSpice t demnstrate the peratin f the 555-timer chip in astable mde. K.A. Cnnr, S. Bnner, P. Schch

13 Wire the circuit in Figure D-4 in PSpice. Figure D-4. Run the simulatin. Perfrm a transient analysis in increments f 2us up t 5ms. Plt the threshld/trigger, discharge and utput vltages. The trigger vltage is pin 2 and the threshld vltage is pin 6. (They are tied tgether.) The discharge vltage is pin 7, and the utput is taken at pin 3. Include a cpy f the plt in yur reprt. Verify that the timer utput changes accrding t the rules listed fr the 555-timer in astable mde. Use the plt t find the time perid that the utput is ON and the time perid that the utput is OFF. Nte: D nt use the first cycle f pulses prduced by the timer circuit. It takes ne cycle t settle in t its steady-state cnditin. One f these times shuld be equal t 0.693(R1+R2)C1 while the ther shuld be equal t 0.693(R2)C1. Which is which? What is the ttal perid f this utput? Which f the three signals n yur plt crrespnds t the charging and discharging f the capacitr, C1? T what vltage des it charge each time? T what vltage des it discharge? What it the rate f charge? Is the rate f discharge the same? Determine the average vltage f the signal. Change the end time fr the transient analysis t 60ms. Display nly the utput vltage (pin 3) n yur plt. Rerun the simulatin. Add a trace f the average f the utput using the average functin, AVG(). This shuld add a trace f the time average f the utput vltage. The average at any instant f time is the average f the vltage frm time = 0 t the time f interest. Thus, yu shuld see that the average asympttically appraches a particular value. Cpy this plt and write the apprximate vltage the average is appraching n the plt. Include this plt in yur reprt. Find a larger and smaller average vltage fr yur circuit Find an expressin fr the duty cycle f an astable 555-timer circuit using the equatins given. Cnsider what relative values f R1 and R2 wuld prduce the highest duty cycle and what relative values f R1 and R2 wuld prduce the smallest duty cycle. Nw, using any cmbinatin fr 3kΩ, 10kΩ r 30kΩ resistrs (nly ne f each value) fr R1 and R2, find the cmbinatin f tw resistrs which results in the largest average vltage and the cmbinatin f tw resistrs which results in the smallest average vltage. Cpy the plt fr each f these tw cases, write the values fr R1 and R2 yu used n each plt. Include these tw plts in yur reprt. K.A. Cnnr, S. Bnner, P. Schch

14 Verify in each case that the pulses prduced by the multivibratr circuit bey the design rules. If the simulatin des nt wrk, the design rules are prbably vilated. Build the 555-timer circuit n yur prtbard In this part f the experiment, we will build the astable multivibratr and use it as the clck fr yur timer circuit. Wire the astable multivibratr shwn in Figure D-5 n yur prtbard. +Vcc Figure D-5. Recrd yur results. Yu will nt be able t see the LED flash because the perid f yur circuit is t fast. Take a Mbile Studi picture f yur utput. Cpy this plt and include it in yur reprt. What is the perid f yur utput signal? What are the ff-time and n-time? Use the equatins t calculate what these values shuld be. Hw d they cmpare? Slw dwn the pulses s that yu can bserve them with the LED. Keeping the resistrs R1 and R2 the same, determine a new value fr C1 such that the perid f the timer will be arund 1 secnd. Replace C1 in yur circuit and bserve the LED. Des it flash nce a secnd? What is yur n-time and ff-time nw? Hw are these related t the n- and ff-times f the riginal circuit? Why des this relatinship hld? Use the 555-timer circuit as the clck fr yur cunter. Remve the functin generatr frm pin 1 f the cunter. Cnnect the utput at pin 3 f the 555-timer circuit t pin 1 f yur cunter circuit. Des the cunter cunt the 555-timer pulses? Can yu see the lwer rder bits change nw? Reprt and Cnclusins The fllwing shuld be included in yur written reprt. Everything shuld be clearly labeled and easy t find. Partial credit will be deducted fr pr labeling r unclear presentatin. Part A (12 pints) Include the fllwing plts: 1. Mbile Studi plt f a single trace frm a NOR gate with truth table. (2 pt) 2. Mbile Studi plt f a single trace frm a NAND gate with truth table. (2 pt) K.A. Cnnr, S. Bnner, P. Schch

15 3. Mbile Studi plt f a single trace frm a NOT gate with truth table. (2 pt) 4. PSpice timing diagram fr the three gates in the circuit with utput traces marked. (2 pt) Answer the fllwing questins: 1. What are the actual vltage values yu bserved as HIGH and LOW states in the hardware realizatin f the circuit? (2 pt) 2. Hw d the truth tables generated using the actual chips crrespnd t the truth tables yu generated using yur PSpice utput? (1 pt) 3. If yu had a gate with fur inputs, hw many cases wuld yu have t cnsider t create its truth table? (1 pt) Part B (10 pints) Include the fllwing plt: 1. Mbile Studi plt f a single trace frm the flip flp with truth table. (2 pt) Answer the fllwing questins: 1. Flip flps are called memry devices. Why d yu think this is true? (2 pt) 2. Shw that the flip flp is giving the crrect utput at the clck cycles (A,B, C and D) indicated n the timing diagram in Figure S-1. DSTM2 is the clck signal, DSTM1 is J, and DSTM3 is K. Shw hw the truth table yu fund fr the actual flip flp is cnsistent with the timing diagram at thse fur pints. (6 pt) Part C (14 pints) Include the fllwing plts: 1. PSpice timing diagram f cunters. (2 pt) 2. Mbile Studi plt f clck and QA. (2 pt) 3. Mbile Studi plt f clck and QB. (2 pt) 4. Mbile Studi plt f clck and QC. (2 pt) 5. Mbile Studi plt f clck and QD. (2 pt) Figure S-1. Answer the fllwing questins: 1. Fr the cunter circuit cnfiguratin just studied, what is the highest number it cunts t in the time shwn n yur utput? Express as bth a binary and decimal number. (2 pt) 2. Hw many pulses will the clck have t cycle thrugh after it resets befre the cunter hits its maximum value? (1 pt) 3. Which utput f the timer (QA, QB, QC, QD) crrespnd t the bits in the binary number (b3 b2 b1 b0): N = b b b b (1 pt) Part D (36 pints) Include fllwing plts: 1. PSpice plt fr the astable circuit with R1 = 10k and R2 = 10k. (2 pt) 2. PSpice plts fr the average vltage f the astable circuit with R1 = R2 = 10k. (1 pt) K.A. Cnnr, S. Bnner, P. Schch

16 3. PSpice plt fr the average vltage f the astable circuit with highest duty cycle. (1 pt) 4. PSpice plt fr the average vltage f the astable circuit with lwest duty cycle. (1 pt) 5. Mbile Studi plt f utput frm 555-timer circuit when R1 = 1.8k, R2 = 6.8k and C1 = 0.1μF. (4 pt) Answer fllwing questins: 1. What are the n-time, the ff-time, and the perid f the signal in plt 1.? What are the calculated values fr these? Are they cnsistent? (4 pt) 2. What are the maximum and minimum values fr the vltage acrss the capacitr C1 (at pins 2 and 6)? (Ignre the vltage at times befre it reaches steady state.) Why d these values make sense? (3 pt) 3. Calculate the value f τ (the decay cnstant) that cntrls the rate at which the capacitr C1 charges. Calculate the value f τ (the decay cnstant) that cntrls the rate at which the capacitr C1 discharges. (4 pt) 4. What is the minimum duty cycle that can be btained frm the astable multivibratr we mdeled using PSpice? Can yu shw this mathematically using Duty Cycle = T1/(T1+T2)? (3 pt) 5. What was the average vltage fr yur riginal circuit? What were the minimum and maximum average vltages when yu cnsidered different cmbinatins f R1 and R2? (3 pt) 6. What are the n-time, the ff-time, and the perid f the signal in plt 5.? What are the calculated values fr these? Are they cnsistent? (4 pt) 7. Hw did yu find the value fr C1 that gave the circuit yu built a ne secnd perid? What value did yu find? (2 pt) 8. What are the calculated n-time, ff-time and perid values fr yur circuit with the new capacitr? Hw d these relate t the initial values? Why? (4 pt) Organizatin and respnsibilities (8 pints) 1. Discuss mistakes and prblems. (6 pt) 2. List member respnsibilities (see belw). (2 pt) K.A. Cnnr, S. Bnner, P. Schch

17 List grup member respnsibilities. Nte that this is a list f respnsibilities, nt a list f what each partner did. It is very imprtant that yu divide the respnsibility fr each aspect f the experiment s that it is clear wh will make sure that it is cmpleted. Respnsibilities include, but are nt limited t, reading the full write up befre the first class; cllecting all infrmatin and writing the reprt; building circuits and cllecting data (i.e. ding the experiment); setting up and running the simulatins; cmparing the thery, experiment and simulatin t develp the practical mdel f whatever system is being addressed, etc. Summary/Overview (0 t -10 pts) There are tw parts t this sectin, bth f which require revisiting everything dne n this experiment and addressing brad issues. Grading fr this sectin wrks a bit differently in that the verall reprt grade will be reduced if the respnses are nt satisfactry. 1. Applicatin: Identify at least ne applicatin f the cntent addressed in this experiment. That is, find an engineered system, device, prcess that is based, at least in part, n what yu have learned. Yu must identify the fundamental system and then describe at least ne practical applicatin. 2. Engineering Design Prcess: Describe the fundamental math and science (ideal) picture f the system, device, and prcess yu address in part 1 and the key infrmatin yu btained frm experiment and simulatin. Cmpare and cntrast the results frm each f the task areas (math and science, experiment, simulatin) and then generate ne r tw cnclusins fr the practical applicatin. That is, hw des the practical system mdel differ frm the riginal ideal? Be specific and quantitative. Fr example, all systems wrk as specified in a limited perating range. Be sure t define this range. Ttal: 80 pints fr experiment packet 0 t -10 pints fr Summary/Overview 20 pints fr attendance 100 pints Attendance (20 pssible pints) 2 classes (20 pints), 1 class (10 pints), 0 class (0 pints) Minus 5 pints fr each late. N attendance at all = N grade fr this experiment. K.A. Cnnr, S. Bnner, P. Schch

18 Experiment 7 Electrnic Instrumentatin Sectin: Reprt Grade: Name Name Checklist w/ Signatures fr Main Cncepts T btain a signature, yu must shw the experiment r simulatin while it is wrking and be prepared t answer questins abut yur results. Tw questins that must always be answered are (1) What are yu shwing that yu have cmpleted and (2) Why d yu knw it is crrect? Fr the secnd questin, yu shuld be able t explain any features f yur data. PART A: Basic Lgic Gates 1. Mbile Studi plt single trace NOR gate with truth table 2. Mbile Studi plt single trace NAND gate with truth table 3. Mbile Studi plt single trace NOT gate with truth table 4. PSpice timing diagram fr the three gates in the circuit with utput traces marked Questins 1-3 PART B: Flip Flps 1. Mbile Studi single trace flip flp with truth table Questins 1-2 PART C: Cunters 1. PSpice timing diagram f cunters 2. Mbile Studi plt f clck and QA 3. Mbile Studi plt f clck and QB 4. Mbile Studi plt f clck and QC 5. Mbile Studi plt f clck and QD Questins 1-3 PART D: 555-Timer 1. PSpice plt astable circuit with R1 = 10k, R2 = 10k 2. PSpice plts average vltage astable circuit with R1 = R2 = 10k 3. PSpice plts average vltage astable circuit with highest duty cycle 4. PSpice plts average vltage astable circuit with lwest duty cycle 5. Mbile Studi plt utput frm 555-timer circuit R1 = 1.8k, R2 = 6.8k and C1 = 0.1μF Questin 1-8 Member Respnsibilities Summary/Overview K.A. Cnnr, S. Bnner, P. Schch