Creating HyperLynx DDRx Memory Controller Timing Model

Transcription

1 Creating HyperLynx DDRx Memry Cntrller Timing Mdel AppNte A P P N T E S SM Creating HyperLynx DDRx Memry Cntrller Timing Mdel By: Min Maung Last Mdified: April 30, ntrductin The DRAM and Cntrller timing mdels are required by the HyperLynx 8.0 DDRx Wizard t specify the timing requirements at bth ends fr the interfacing signals. The DDRx Wizard uses the parameters frm the timing mdels fr deriving the final timing margins. These timing parameters include skew, delay, setup and hld time requirements n signals with respect t their assciated strbe r clck signal. The DRAM timing mdels are quite standardized since the timing specificatins at the DRAMs are specified by the JEDEC standards. n the case f the cntrllers, it is very likely that the timing requirements are different frm vendr t vendr. The default cntrller timing mdels fr each DDRx interface (ddr_ctl.v, ddr2_ctl.v, and ddr3_ctl.v) are included with HyperLynx in the flder such as C:\MentrGraphics\<release>\SDD_HME\hyperlynx\Libs. These default timing mdels can be used t perfrm simulatins using the DDRx Wizard quickly. f yur cntrller s timing parameters differ significantly frm the default mdel, yu will need t create yur wn mdel t btain the accurate timing simulatin results. T help yu with this prcess, HyperLynx includes the HyperLynx Timing Mdel Wizard and the HyperLynx Timing Mdel Editr. The HyperLynx Timing Mdel Wizard guides yu thrugh the prcess f creating the timing mdel. The HyperLynx Timing Mdel Editr allws yu t edit, check fr syntax, and view the timing relatinships in the frm f timing diagrams. n this applicatin nte, firstly the DDRx timing relatinships in each signal grup are reviewed. Secndly, it defines and explains the timing parameters that are required by the DDRx Wizard at the cntrller. Thirdly, it prvides guidance n hw t find the relevant timing parameters frm three different cntrller datasheets and translate them int the required DDRx Wizard cntrller parameters. Finally, it shws the methdlgy fr creating the cntrller timing mdel by entering thse parameters in the HyperLynx Timing Mdel Wizard (GU based) r in the HyperLynx Timing Mdel Editr (syntax-based). 2.0 Review n DDRx n Timing Relatinships This sectin reviews the DDRx specific timing relatinships between signals at the cntrller during read and write peratins. n the DDRx memry interface, there are fur main grups f signals: Address and Cmmand Signals (A[15:0], BA[2:0], RAS#, CAS# & WE#) Cntrl Signals (CS[3:0], E[3:0], & DT[3:0]) Data, Data Mask, and Strbe signals (DQ[63:0], DM[8:0], CB[7:0], DQS/#DQS[8:0]) Clck Signals (/#[5:0])

2 First, the perating frequency f the clck signal must be determined. The DDRx interface is usually specified by ntatin DDRx <speed-grade>, fr example DDR-400, DDR2-533 r DDR The speed-grade unit is in MT/s (mega-transfer per secnd). n this applicatin nte, DDR3-800 will be used as an example thrughut. n this case, the speed-grade is 800MT/s, and the perating frequency is half f the speed-grade; 400MHz. The bit perid fr address/cmmand/cntrl and data signals is needed infrmatin. The address, cmmand and cntrl signals are utput nly signals but are used fr bth read and write peratins. The address, cmmand and cntrl signals reference an assciated clck () signal. 1T r 2T timing is allwed n address and cmmand signals but nly 1T timing is allwed n cntrl signals. Typically, the cntrller utputs these signals apprximately aligned with a falling clck edge. T achieve this, the address/cmmand/cntrl signal is launched half the clck perid earlier than the clck. This timing is referred t as 1T timing. Fr 2T timing, the address /cmmand signal is launched ne and a half perid earlier than the clck s that there is mre setup time at the receiver. S, the shrtest available setup time fr the address signal fr 1T timing is ne clck perid and fr 2T timing, it is 2 clck perids. Figure 1 is the timing diagram shwing the timing relatinships explained abve. The gray windws are the uncertainties that need t be accunted fr in the real peratin. Figure 1: DDRx Address, Cmmand, and Cntrl Signal Timing at the Cntrller 0ps 1ns 2ns 3ns 4ns 5ns 6ns t 400MHz 1T Prelaunch Delay(max) 1T Prelaunch Delay (min) A/CMD/CTL (1T) [15..0] 1T Bit Perid A/CMD (2T) [15..0] 2T Prelaunch Delay (max) 2T Prelaunch Delay (min) 2T Bit Perid The data, data mask and strbe signals are bi-directinal signals: utputs during the write peratin and inputs n the read peratin. Each data byte lane references a DQS signal. During the write peratin, DQ and DM signals are launched a quarter f the clck perid earlier than the DQS signal fr each byte lane s that bth rising and falling edges f the strbe are centered in the valid data bit windw. Since the data and data mask signals can be clcked in at every strbe edge, the bit perid fr these signals is half f the clck perid. Figure 2 shws the abve described timing relatinship. The gray windws are the uncertainties that need t be accunted fr in real peratin. Figure 2: DDRx DQ/DM Signals Timing at the Cntrller during Write 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns 4ns t 400MHz DQS (Write) DQ Prelaunch Delay (max) DQ/DM (Write) [63..0] DQ Prelaunch Delay (min)

3 During the write peratin, the cntrller als needs t meet the delay timing relatinship between the clck signals () and strbe signals (DQS). This relatinship is defined in Figure 3. Figure 3: DDRx and DQS Timing at the Cntrller 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns t DQS 400MHz Delay t (min) Delay t (max) During the read peratin, the DRAMs send bth DQ signals and DQS signals t the cntrller, edge aligned. At the cntrller, these signals must meet certain setup and hld requirements. The setup and hld requirements at the cntrller can be specified in tw ways: at the pins r at the internal registers. f the timing requirements are at the pins, DQ/DM signals and DQS signals are edge aligned. f the timing requirements are specified at the internal registers, infrmatin n hw the cntrller captures the data internally is needed. Typically, the ideal phase shift is ne quarter f the clck cycle. Figure 4 shws the abve described timing relatinships. Figure 4: DDRx DQ/DM Signals Timing at the Cntrller during Read 0ps 500ps 1ns 1.5ns 2ns 2.5ns DQS DQS(Shifted) Setup at Pin Hld at Pin DQ/DM [63..0] Setup at Register Hld at Register Table 1 shws the summary f the timing relatinships in a DDRx interface. Table 1: Summary f DDRx Timing Relatinships at the Cntrller peratin Signals Ref. Signal Ref. Signal Freq Clcked Edge Typical Signal Prelaunch at Receiver Delay Relative t r DQS Timing Read/Write A/Cmd +/ 0.5*DataRate Rise 0.5*t 1T r 2T Read/Write Ctl +/ 0.5*DataRate Rise 0.5*t 1T Write DQ/DM DQS+/ 0.5*DataRate Rise & Fall 0.25*t NA Write DQS+/ +/ 0.5*DataRate Rise & Fall 0 NA Read DQ/DM DQS+/ 0.5*DataRate Rise & Fall 0 NA 3.0 Cntrller Timing Parameters Required by the DDRx Wizard Fr any cntrller, the DDRx Wizard requires the parameters that are described in this sectin. The same parameters are als required if yu want t create a cntrller mdel using the HyperLynx Timing Mdel Wizard. 3.1 tac(min) and tac(max) Applicable t address (A) and cmmand signals (BA, RAS, CAS, and WE) n bth read and write cycles

4 The minimum and maximum delay between the address and cmmand utput signals, transitining t valid befre the rising edge f the utput clck () Allws 1T (Figure 5) r 2T (Figure 6) timing n these signals f the delay between a valid transitin f the Address and Cmmand signals and the rising edge f the clck is mre than ne clck cycle, it is referred t as 2T timing. Figure 5: tac (min) and tac(max) (1T Timing) Figure 6: tac (min) and tac(max) (2T Timing) 3.2 tctl(min) and tctl(max) Applicable t cntrl signals (CS, E, and DT) n bth read and write cycles. The minimum and maximum delay between the cntrl utput signals transitining t valid befre the rising edge f the utput clck. Allws nly 1T timing (Figure 7) n these signals. Figure 7: tctl(min) and tctl(max) 3.3 tdqs(min) and tdqs(max) Applicable t and DQS signals during the WRTE cycle The minimum and maximum skew (Figure 8) between the rising edge f the utput data strbe (DQS) and the rising edge f the utput clck (). Figure 8: tdqs(min) and tdqs(max) 3.4 tdqsdq(min) and tdqsdq(max) Applicable t data(dq) and data mask (DM ) signals and its assciated DQS signal during the WRTE cycle The minimum and maximum delay between the data and data mask utput signals transitining t valid and the assciated utput data strbe edge (either rising r falling) Figure 9: tdqsdq(min) and tdqsdq(max)

5 3.5 tds and tdh Applicable t data(dq) signals and its assciated DQS signal during the READ cycle Data setup (tds) and hld (tdh) windw relative t assciated DQS During a read cycle, the DRAMs utput the transitins f the DQS signal apprximately aligned with the transitins f the DQ signals. The cntrller captures the DQ signals by typically phase shifting the DQS signal internally by abut 1/4 clck perid. Specify whether the "setup" and "hld" parameters are measured at the cntrller pins (phase shift=0) (Figure 10) r after an internal 90 phase shift (Figure 11). Setup values are psitive if DQ must be valid befre DQS (negative if after); Hld values are psitive if DQ must remain valid until after DQS (negative if befre). Figure 10: tds and tdh with 0 Phase Shift Figure 11: tds and tdh with 90 Phase Shift 4.0 nterpreting and Deriving Required Timing Parameters frm Datasheet n this sectin, three examples are shwn in deriving the HyperLynx DDRx required parameters frm the datasheet parameters. These derivatins are required since each chip vendr specifies the timing parameters fr the cntrller in different ways. Sme f the variatins are: Specified either at the internal registers r at the pin-pad Specified as a skew r as a valid windw Relative t a clck/strbe rising r falling edge 4.1 Example 1: The HyperLynx Default ddr3_ctl Cntrller Mdel n the default cntrller mdel, ddr3_ctl.v, the parameters shwn in Table 2 were assumed t be defined in the cntrller datasheet and Figure 12 shws the timing diagram f these parameters. Table 2: Default ddr3_ctl Cntrller Datasheet Parameters Definitins Parameters Definitins taccskew utput delay skew frm falling t Addr/Cmd/Ctl (+/ ) tdqs utput delay skew frm rising t DQS rising (+/ ) tdqsdqq utput delay skew frm DQS t DQ (+/ ) tds Minimum DQ t DQS setup time, with 1/4 cycle DQS shift tdh Minimum DQS t DQ hld time, with 1/4 cycle DQS shift

6 Figure 12: Default ddr3_ctl Cntrller Datasheet Parameters Timing Diagram 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns t 400MHz A/CMD/CTL [15..0] taccskew(min) taccskew(max) tdqs(min) tdqs(max) DQS(Write) DQS (Write) tdqprelaunch DQ/DM (Write) [63..0] DQS (Read) DQS (Read Shifted) DQ/DM (Read) [63..0] tdqsdqq(min) tdqsdqq(max) tdqsshift tds tdh tds tdh 625ps 1.875ps The fllwing sectins shw the derivatins f the DDRx Wizard required parameters frm the abve default cntrller s datasheet parameters Deriving tac(min) and tac(max) fr DDR3 Default Timing Mdel Yu need taccskew t derive tac(min) and tac(max). The timing relatinships between thse parameters are shwn in Figure 13. Figure 13: tac/tctl Timing Diagram fr DDR3 Default Timing Mdel 0ps 200ps 400ps 600ps 800ps 1ns 1.2ns 1.4ns 1.6ns 1.8ns 2ns 2.2ns 2.4ns 2.6ns t 400MHz tac(min)/tctl(min) tac(max)/tctl(max) tacdlymin tacdlymax A/CMD/CTL [15..0] taccskew(min) taccskew(max) T derive tac(min) and tac(max) frm taccskew, ACDlyMin and tacdlymax parameters are defined as fllws and als shwn in Figure 13: tacdlymin = Delay frm rising ut t Addr/Cmd/Ctl invalid (min) tacdlymax = Delay frm rising ut t Addr/Cmd/Ctl invalid (max)

7 Table 3: Deriving tac(min) and tac(max) fr DDR3 Default Timing Mdel SpeedGrade t taccskew(min) taccskew(max) DDR ps 300 ps +300 ps tacdlymin tacdlymax t/2+taccskew(min) = = 950 ps t/2+taccskew(max) = = 1550 ps tac(min) tac(max) t + tacdlymin = = 1550 ps t + tacdlymax = = 950 ps Deriving tctl(min) and tctl (max) fr DDR3 Default Timing Mdel The parameters tctl(min) and tctl(max) are derived exactly the same way as tac(min) and tac(max) as shwn in Figure 13. Table 4: Deriving tctl(min) and tctl (max) fr DDR3 Default Timing Mdel SpeedGrade t taccskew(min) taccskew(max) DDR ps 300 ps +300 ps tacdlymin tacdlymax t/2+taccskew(min) = = 950 ps t/2+taccskew(max) = = 1550 ps tctl(min) tctl(max) t + tacdlymin = = 1550 ps t + tacdlymax = = 950 ps Deriving tdqs(min) and tdqs(max) fr DDR3 Default Timing Mdel The parameter tdqs is defined in the default cntrller datasheet in the exact same way as needed by the DDRx Wizard as shwn in Figure 14. Figure 14: tdqs(min) and tdqs(max) Timing Diagram fr DDR3 Default Timing Mdel 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns t 400MHz DQS(Write) tdqs(min) tdqs(max) Table 5: Deriving tdqs(min) and tdqs(max) fr DDR3 Default Timing Mdel SpeedGrade t tdqs(min) tdqs(max) DDR ps 150 ps +150 ps tdqs(min) tdqs(max) 150 ps +150 ps Deriving tdqsdq(min) and tdqsdq(max) fr DDR3 Default Timing Mdel Yu will need tdqsdqq parameter frm the DDR3 Default Timing Mdel datasheet t derive tdqsdq(min) and tdqsdq(max). The timing relatinships between thse parameters are shwn in Figure 15.

8 Figure 15: tdqsdq(min) and tdqsdq(max) Timing Diagram fr DDR3 Default Timing Mdel 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns t 400MHz DQS (Write) tdqprelaunch tdqsdq(max) DQ/DM (Write) [63..0] tdqsdqq(min) tdqsdqq(max) tdqsdq(min) DQS (Read Shifted) Table 6: Deriving tdqsdq(min) and tdqsdq(max) fr DDR3 Default Timing Mdel SpeedGrade t tdqsdqq(min) tdqsdqq(max) DDR ps 150 ps +150 ps tdqsdq(min) tdqsdq(max) tdqprelaunch + tdqsdqq(min) = = 775 ps tdqprelaunch + tdqsdqq(max) = = 475 ps Deriving tds and tdh fr DDR3 Default Timing Mdel The parameters tds and tdh are defined in the default cntrller datasheet exactly the same way as the DDRx Wizard required timing parameters as shwn in Figure 16. Figure 16: tds and tdh Timing Diagrams fr DDR3 Default Timing Mdel 0ps 500ps 1ns 1.5ns 2ns 2.5ns t DQS (Read) 400MHz DQS (Read Shifted) tdqsshift tds tdh tdqdqs(min) tdqdqs(max) tds tdh DQ/DM (Read) [63..0] Therefre, yu will nt need t derive these parameters. Nte that tdqdqs(min) and tdqdqs(max) parameters (shwn in Figure 16) are derived frm tds and tdh r vice versa. The DDRx Wizard nly needs thse parameters t be defined using either tdqdqs(min) and tdqdqs(max) r tds and tdh. Table 7: Deriving tds and tdh fr DDR3 Default Timing Mdel SpeedGrade t tds tdh DDR ps 150 ps 250 ps tds tdh tdqdqs(min) tdqdqs(max) 0.5*t tdqsshift tdh = ( ) ps = 375 ps tdqsshift tds = ( ) ps = 475 ps Summary f DDRx Wizard Required Timing Parameters fr DDR3 Default Timing Mdel Table 8 shws the summary f derived timing parameters which are needed by the DDRx Wizard. These parameters can be entered directly int the HyperLynx Timing Mdel Wizard which will be cvered in the next sectin.

9 Table 8: Summary f DDRx Wizard Required Timing Parameters DDR3 Default Timing Mdel DDRx Wizard Required Parameters Min (ps) Max (ps) tac tctl tdqs tdqsdq tds 150 tdh Example 2: MPC8544E PwerQUCC ntegrated Prcessr Cntrller Mdel n this example, each f the fllwing sectin shws the derivatin f DDRx Wizard required parameters frm the Freescale MPC8544E PwerQUCC ntegrated Prcessr datasheet parameters. The fllwing diagrams are screenshts f the utput timing parameters and the diagrams fr Freescale MPC8544E PwerQUCC ntegrated Prcessr: Figure 17: MPC8544E utput Timing Diagram Figure 18: MPC8544E utput Timing Parameters

10 MPC8544E utput Timing Parameters (Cnt.) Deriving tac(min) and tac(max) fr MPC8544E Figure 17 and Figure 18 shws that the needed timing parameters t derive tac(min)/(max) are tddkhas and tddkhax. n this derivatin, the 533MHz case will be used. Nte that the 533MHz in this case is nt the frequency f the clck but it is rather the speed grade fr the DDRx interface. The actual frequency f the clck is half f 533MHz which is equal t 267MHz. Frm the definitin f tddkhas and tddkhax, they are specified as utput setup and hld parameters. As yu will recall frm sectin 3.1, tac(min) and tac(max) parameters are defined as delay between the address and cmmand utput signals, transitining t "valid" befre the rising edge f the utput clck. Figure 19 shws the relatinship between the DDRx Wizard needed parameters tac(min)/(max) and the datasheet parameters (tddkhas and tddkhax). Table 9 shws the needed derivatins. Figure 19: Relatinship Between tac (min)/tac(max) and tddkhas/tddkhax 0ps 1ns 2ns 3ns 4ns 5ns MHz t tac(min) tac(max) ADDR/CMD [15..0] tddkhax tddkhas tddkhax

11 Table 9: Deriving tac(min) and tac(max) fr MPC8544E SpeedGrade t tddkhas tddkhax DDR /267MHz = 3750 ps 1480 ps 1480 ps tac(min) tac (max) t + tddhax = 3750 ps ps = 2270 ps tac(max) = tddkhas = 1480 ps Deriving tctl(min) and tctl(max) fr MPC8544E Frm the definitin f tddkhcs and tddkhcx in Figure 18 and Figure 17, they are specified as utput setup and hld parameters. As yu will recall frm sectin 3.2, tctl(min) and tctl(max) parameters are defined as delay between the cntrl utput signals, transitining t "valid" befre the rising edge f the utput clck. Figure 20 and Table 10 shw the timing relatinships and the derivatins. Figure 20: Relatinship Between tctl(min)/ tctl(max) and tddkhcs/tddkhcx 0ps 1ns 2ns 3ns 4ns 5ns MHz t CTL tddkhcx tctl(min) tctl(max) tddkhcs tddkhcx Table 10: 1 Deriving tctl(min) and tctl(max) fr MPC8544E SpeedGrade t tddkhcs tddkhcx DDR /267MHz = 3750 ps 1480 ps 1480 ps tctl(min) tctl(max) t + tddhcx = 3750 ps ps = 2270 ps tac(max) = tddkhcs = 1480 ps Figure 21: MPC8544E M t MDQS Skew Parameter (tddkhmh) Deriving tdqs(min) and tdqs(max) fr MPC8544E Frm the definitin f tddkhmh in Figure 18 and Figure 21, tdqs(min) is equivalent t tddkhmh(min) and tdqs(max) is equivalent t tddkhmh(max). Figure 22 and Table 11 shw the timing relatinships and derivatins f the abve parameters.

12 Figure 22: Relatinship Between tdqs(min)/ tdqs(max) and tddkhmh(min)/tddkhmh(max) 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns 4ns 4.5ns 5ns MHz t tdqs(min) tdqs(max) tddkhmh(min) tddkhmh(max) DQS Table 11: Deriving tdqs(min) and tdqs(max) fr MPC8544E SpeedGrade t tddkhmh(min) tddkhmh(max) DDR /267MHz = 3750 ps 600 ps 600 ps tdqs(min) tdqs(max) tddkhmh(min) = 600 ps tddkhmh(max) = 600 ps Deriving tdqsdq(min) and tdqsdq(max) fr MPC8544E As yu can see frm Figure 17 and Figure 18, the related timing parameters t derive tdqsdq(min) and tdqsdq(max) are tddkhds/tddklds and tddkhds/tddkldx. Figure 23: Relatinship Between tdqsdq(min)/ tdqsdq(max) and tddklds/tddkldx 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns MHz t 0.5*t DQS (Write) tdqsdq(max) tdqsdq(min) tddkhds DQ/DM (Write) [63..0] tddkhdx tddklds tddkldx Table 12: Deriving tdqsdq(min) and tdqsdq(max) fr MPC8544E SpeedGrade t tddklds/ tddkhds tddkldx/ tddkhdx DDR /267MHz = 3750 ps 538 ps 538 ps tdqsdq(min) tdqsdq(max) 0.5*t + tddkldx = 0.5 * 3750ps + 538ps = 1337ps tddklds = 538ps Deriving tds and tdh fr MPC8544E Referring t Figure 24 and Figure 25, the DDRx Wizard needed parameters tds and tdh can be derived frm the tcskew(min) and tcskew(max). As yu can see in the Ntes 2 f Figure 24, tdskew = (T/4 abs(tcskew)). This gives yu a clue that DQS is shifted by t/4 with relative t DQ.

13 Figure 24: MPC8544E nput AC Timing Specificatins Figure 25: MPC8544E nput Timing Diagram Figure 26 and Table 14 shw the timing relatinships and derivatins f tds and tdh parameters. Figure 26: tds & tdh Timing Diagram fr MPC8544E 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns 4ns t MHz DQS(Read) DQS (Read Shifted) tdqsshift tdskew(max) tdskew(min) tdskew(max) CSKEW(min) CSKEW(max) DQ/DM (Read) [63..0] tds tdh Table 13: Deriving tds and tdh fr MPC8544E SpeedGrade t tcskew(min) tcskew(max) DDR /267MHz = 3750 ps 300 ps 300 ps tds tdh tcskew(min) = 300 ps tcskew(max) = 300 ps

14 4.2.6 Summary f DDRx Wizard Needed Parameters fr MPC8544E Table 14: Summary f DDRx Wizard Required Timing Parameters fr MPC8544E DDRx Wizard Required Parameters Min (ps) Max (ps) tac tctl tdqs tdqsdq tds 300 tdh Example 3: Chipset Memry Cntrller n this example, the memry cntrller mdel is f a chipset frm a majr vendr. Table 15 defines the parameters that were prvided in this chipset cntrller datasheet and Figure 27 shws the timing diagram f thse parameters. Table 15: Chipset Memry Cntrller Datasheet Parameters Definitins Parameters Definitins tcmdvb minimum time Addr/Cmd (+/ ) will becme valid befre rising tcmdva minimum time Addr/Cmd (+/ ) will remain valid after rising tcntlvb minimum time Cntrl (+/ ) will becme valid befre rising tcntlva minimum time Cntrl (+/ ) will remain valid after rising tdssctlr DQS fall t rise (min, write cycles) tdshctlr rise t DQS fall (min, write cycles) tdvb utput delay skew frm rising t DQS rising (+/ ) tdva utput delay skew frm DQS t DQ (+/ ) tsuctlr Minimum DQ t DQS setup time, with 0 cycle DQS shift thdctlr Minimum DQS t DQ hld time, with 0 cycle DQS shift Figure 27: Chipset Memry Cntrller Datasheet Parameters Timing Diagram 0ps 1ns 2ns 3ns 4ns 5ns 6ns t 400MHz tdssctlr tdshctlr DQS A/CMD (2T) [15..0] tcmdvb tcmdva tcntlvb tcntlva CTL [15..0] DQS (Write) DQ/DM (Write) [63..0] tdvb tdva DQS (Read) thdctlr DQ/DM (Read) [63..0] tsuctlr Deriving tac(min) and tac(max) fr DDR3 Chipset Memry Cntrller The derivatins in Table 16 were dne by referring t Figure 28. Nte that this cntrller uses 2T timing n the Address/Cmmand signals.

15 Table 16: Deriving tac(min) and tac(max) fr Chipset Memry Cntrller SpeedGrade t tcmdvb tcmdva DDR ps 3302 ps 1244 ps tac(min) tac(max) 2*t + tcmdva = = 3756 ps tcmdvb = 3302 ps Figure 28: tac(min) and tac(max) Timing Diagrams fr Chipset Memry Cntrller 0ps 1ns 2ns 3ns 4ns 5ns 6ns t 400MHz tac(max) tac(min) A/CMD (2T) [15..0] tcmdvb tcmdva Deriving tctl(min) and tctl (max) fr Chipset Memry Cntrller The derivatins in Table 17 were dne by referring t Figure 29. Table 17: Deriving tctl(min) and tctl (max) fr Chipset Memry Cntrller SpeedGrade t tcntl_vb tcntl_va DDR ps 802 ps 1244 ps tctl(min) tctl(max) t + tcntl_va = = 1256 ps tcntl_vb = 802 ps Figure 29: tctl(min) and tctl Timing Diagrams fr Chipset Memry Cntrller 0ps 1ns 2ns 3ns 4ns 5ns 6ns t 400MHz tctl(max) tctl(min) tcntlvb tcntlva CTL [15..0] Deriving tdqs(min) and tdqs(max) fr Chipset Memry Cntrller Refer t Figure 30 fr the derivatins in Table 18. Table 18: Deriving tdqs(min) and tdqs(max) fr Chipset Memry Cntrller SpeedGrade t tdssctlr tdshctlr DDR ps 1173 ps 920 ps tdqs(min) tdqs(max) tdshctlr 0.5*t = = 330 ps 0.5*t tdssctlr = = 77 ps

16 Figure 30: tdqs(min) and tdqs(max) Timing Diagrams fr Chipset Memry Cntrller 4ns 4.5ns 5ns 5.5ns 6ns t 400MHz tdqs(min) tdqs(max) tdssctlr tdshctlr DQS Deriving tdqsdq(min) and tdqsdq(max) fr Chipset Memry Cntrller Refer t Figure 31 fr the derivatins in Table 19. Table 19: Deriving tdqsdq(min) and tdqsdq(max) fr Chipset Memry Cntrller SpeedGrade t tdvb tdva DDR ps 494 ps 494 ps tdqsdq(min) tdqsdq(max) 0.5*t + tdva = = 756 ps tdvb = 494 ps Figure 31: tdqsdq(min) and tdqsdq(max) Timing Diagrams fr Chipset Memry Cntrller 0ps 500ps 1ns 1.5ns 2ns 2.5ns 3ns 3.5ns t 400MHz DQS (Write) tdqsdq(max) tdqsdq(min) DQ/DM (Write) [63..0] tdvb tdva Deriving tds and tdh fr Chipset Memry Cntrller Refer t Figure 32 fr the derivatins in Table 20. Table 20: Deriving tds and tdh fr Chipset Memry Cntrller SpeedGrade t thdctlr tsuctlr DDR ps 500 ps 200 ps tds tdh tsuctlr = 200 ps thdctlr = 500 ps Figure 32: tds and tdh Timing Diagrams fr Chipset Memry Cntrller 4ns 4.5ns 5ns 5.5ns 6ns t 400MHz DQS (Read) tdh tds DQ/DM (Read) [63..0] thdctlr tsuctlr

17 4.3.6 Summary f DDRx Wizard Needed Parameters fr Chipset Memry Cntrller Table 21: Summary f DDRx Wizard Required Timing Parameters fr Chipset Memry Cntrller DDRx Wizard Required Parameters Min (ps) Max (ps) tac tctl tdqs tdqsdq tds 200 tdh Creating the DDRx Timing Mdels (.v) The required timing parameters derived frm the previus sectin nw needs t be implemented int the HyperLynx Timing Mdel (HLTM) frmat that is recgnized by the DDRx Wizard. This can be dne using the fllwing methdlgies: Using the HyperLynx Timing Mdel Wizard The parameters entered int the Wizard must be the derived DDRx Wizard required parameters The wizard just creates the mst basic mdel with just ne speed grade parameters N syntax expertise required Easy t create and the mdel is ready fr use Using the HyperLynx Timing Mdel Wizard and adding simple syntax in the HyperLynx Timing Mdel Editr The parameters entered int the Wizard must be the derived DDRx Wizard required parameters Cmbine different speed-grade timing mdels created by the Timing Mdel Wizard t create a multi-speed-grade mdel Sme syntax expertise is required but the Verilg syntax used in these timing mdels is nt that cmplicated Mre effrt is invlved than the previus methd but it is a als mre rbust mdel Entering the required syntax in the HyperLynx Timing Mdel Editr Define the timing parameters in the mdel (.v file) as defined in the cntrller spreadsheet Enter the syntax t derive the DDRx Wizard required timing parameters frm the spreadsheet parameters Mre syntax expertise is required but the Verilg syntax used in these timing mdels is nt that cmplicated Creates the mst rbust mdel and all timing derivatins are self-cntained fr future understanding f the mdel and reference Please refer t BardSim Help Manual in sectin Cncepts and Reference Guide > File Specificatins > HyperLynx Timing Mdel Frmat fr mre infrmatin n the HyperLynx timing mdel frmat and syntax. 5.1 Creating the Single Speed-grade Mdel nce yu have the required DDRx Wizard timing parameters derived, entering the parameters int the Wizard is quite simple. n this example, the chipset cntrller parameters frm Table 21 are used fr the creatin prcess. Nte that even thugh this is the simplest mdel t create, it desn t mean that it s

18 less accurate. t simply means that it is the easiest and quickest t create with just ne speed grade parameters. pen the HyperLynx Timing Mdel Wizard frm BardSim by chsing Mdels > Run DDRx Cntrller Timing Mdel Wizard HyperLynx Timing Mdel Wizard: ntrductin page Set the data rate fr the parameters that were derived HyperLynx Timing Mdel Wizard: Address/Cmmand Timing Enter tac (min/earliest) and tac(max/latest) values. These values are entered as psitive numbers here.

19 5.1.3 HyperLynx Timing Mdel Wizard: Cntrl Timing page Enter tctl (min/earliest) and tctl (max/latest) values. These values shuld be entered as psitive numbers HyperLynx Timing Mdel Wizard: Write Strbe Timing page Enter tdqs (min/earliest) and tdqs (max/latest) values. The earliest value is a negative number and latest value is a psitive number

20 5.1.5 HyperLynx Timing Mdel Wizard: Write Data Timing page Enter tdqsdq (min/earliest) and tdqsdq (max/latest) values. These values shuld be entered as psitive numbers HyperLynx Timing Mdel Wizard: Read Data Timing page 0 if parameters are defined at the pin. 90 if p arameters are defined at the internal registers. n this example, it is set t 0. Enter tds and tdh values. Setup values are psitive if DQ must be valid befre DQS (negative if after); Hld values are psitive if DQ must remain valid until after DQS (negative if befre) nce the mdel is saved, the.v file with the syntax shwn in Figure 33 is created by the Timing Mdel Wizard. Please refer t the BardSim Help Manual in Cncepts and Reference Guide > File Specificatins > HyperLynx Timing Mdel Frmat sectin fr mre infrmatin n the HyperLynx timing mdel frmat and syntax. The created mdel can be pened in the HyperLynx Timing Mdel Editr t view the timing diagram f the parameters and it is shwn in Figure 34. The HyperLynx Timing Mdel Editr can be pened frm BardSim by chsing Mdels > Edit DDRx Timing Mdels (.v).

21 Figure 33: Syntax fr Single Speed-grade Chipset Cntrller Mdel Created by the Timing Mdel Wizard Figure 34: Timing Diagram fr the Simplest Chipset Cntrller Mdel Viewed frm Timing Mdel Editr Nte that tac(min)/(max), tctl(min)/(max), and tdqsdq(min)/(max) values were entered as psitive numbers in the DDRx Timing Mdel Wizard but in Figure 33 and Figure 34, yu will ntice that thse values are displayed as negative numbers. Be aware f this number cnventin: the DDRx Timing Mdel Wizard needs these numbers as psitive numbers and the DDRx Wizard needs these numbers as negative numbers.

22 5.2 Creating Multi-Speed-grade Timing Mdel This sectin describes the methdlgy t create a multi speed-grade mdel by cmbining the single speedgrade mdels created by the Timing Mdel Wizard frm the previus sectin and adding additinal simple syntax t the mdel. Figure 35: Syntax fr Simple Multi Speed-grade Chipset Cntrller Mdel Figure 35 shws the required syntax fr that multi-grade mdel and the methdlgy t create this mdel is as fllws: 1. Create a mdel fr each speed-grade using the Timing Mdel Wizard as described in the previus sectin. n this example, there are three speed grades mdel files with the names: DDR2_667.v, DDR3_800.v, and DDR3_1066.v. 2. pen the first speed-grade mdel (DDR2_667.v ) in the HyperLynx Timing Mdel Editr. 3. Save this file as DDRx_multigrade.v. 4. n the line after specify, enter `ifdef DDR2_ At the end f `ifdef sectin, enter `elsif DDR3_ pen the secnd speed-grade mdel (DDR3_800.v), and cpy all the lines that are between specify and endspecify. 7. Paste it in the DDRx_multigrade.v file after the line `elsif DDR3_ At the end f `elsif sectin enter `else `define DDR3_ pen the third speed-grade mdel (DDR3_1066.v), and cpy all the lines that are between specify and endspecify. 10. Paste it in the DDRx_multigrade.v file after the line `else `define DDR3_1066

23 11. At the end f `else `define sectin, type in `endif 12. Chse Build > Cmpile t check fr any syntax errrs. Please refer t the BardSim Help Manual in Cncepts and Reference Guide > File Specificatins > HyperLynx Timing Mdel Frmat > "Detailed Syntax - HyperLynx Timing Mdels" sectin fr descriptin f the syntax in mre details. 5.3 Creating a Cntrller Timing Mdel Syntactically n this sectin, the same chipset cntrller mdel is created by entering the syntax directly in the HyperLynx Timing mdel Editr. Since sme f the syntax is cmmn t all mdels, a default cntrller mdel can be used as a starting pint fr this mdel creatin methdlgy Define Tp-level Mdule and HyperLynx Standard Prt Names The tp level mdule and standard HyperLynx prt names are defined in this sectin. The mdule name can be arbitrary but the prt names are reserved fr HyperLynx as defined in the embedded table in Figure 36. This sectin is required in the HyperLynx timing mdel. Figure 36: Syntax fr Defining Tp-level Mdule and HyperLynx Standard Prt Names Specify Chipset Cntrller Datasheet Parameters by Speed-grade n this sectin, the parameters f different speed-grades are entered exactly as defined in the datasheet. The speed designatrs must fllw the cnventin as described in the embedded table (frm Help) Figure 37. Figure 37: Syntax fr Specifying Chipset Cntrller Datasheet Parameters by Speed-grade

24 5.3.3 Derive HyperLynx Required Timing Parameters Table 22 shws the equatins needed t derive the HyperLynx required timing parameters frm the chipset cntrller timing parameters. The left clumn shws the generic timing equatins that were used in sectin 4.3 Example 3: Chipset Memry Cntrller. The right clumn shw the syntax required in HyperLynx timing mdel frmat. Nte that tac(min)/(max), tctl(min)/(max), and tdqsdq(min)/(max) values are defined syntactically as negative numbers. Table 22: Derivatins Cmparisn between Generic Timing Equatins and HLTM Syntax Equatins Generic Timing Equatins HyperLynx Timing Mdel Syntax (HLTM) Frm Table 16: tac(min) = 2*t + tcmdva parameter tacmin = (2*`t) + tcmd_va; tac(max) = tcmdvb tacmax = tcmd_vb; Frm Table 17 tctl(min) = t tcntl_va tctl(max) = tcntl_vb Frm Table 18: tdqs(min) = tdshctlr 0.5*t tdqs(max) = 0.5*t tdssctlr Frm Table 19: tdqsdq(min) = 0.5*t + tdva tdqsdq(max) = tdvb Frm Table 20: tds = tsuctlr tdh = thdctlr parameter tctlmin = tcntl_va `t; parameter tctlmax = tcntl_vb; parameter tdqsmin = tdshctlr tdqbit; parameter tdqsmax = tdqbit tdssctlr; parameter tdqsdqmin = tdqbit + tdva; parameter tdqsdqmax = tdva; parameter tds = tsuctlr; parameter thd = thdctlr; Figure 38: HyperLynx Timing Mdel Syntax t Derive the Required HyperLynx Timing Parameters Define Timing Relatinships in the Mdel's Specify Blck n this sectin, the timing relatinships are defined. This sectin is respnsible fr prviding the min and max delay values, and setup and hld values between prts t the DDRx Wizard. All cntrller timing mdels must include this sectin and Figure 39 shws the required syntax fr each parameter. The $delay functin is a nn-verilg cnstruct added t the HyperLynx timing mdel syntax. The fllwing is the syntax t specify delay relatinship between tw mdule prts: $delay(frmprt_event, tprt_event, min_delay, max_delay); Fr example, in Figure 39, the syntax $delay(psedge ck, addr_cmd, tacmin, tacmax); sends the min and max delay values (tacmin and tacmax) between the ck and addr_cmd prts t the DDRx Wizard. Remember that the values tacmin and tacmax were defined in

25 the previus sectin. The parameter names are arbitrary but it is recmmended that the standard parameter names (as required by the DDRx Wizard) are used fr purpse f clarity. Nte that parameter tdqdqs and parameters tds/tdh are cmplementary methds f describing the DQ-t- DQS timings during read cycles; nly ne f the tw methds shuld be specified in the timing mdel file. Please refer t HyperLynx Help fr mre infrmatin. Figure 39: Syntax t Define Timing Relatinships This chipset cntrller timing mdel can be dwnladed frm the link in the fllwing tech nte: 6 Summary This applicatin nte prvided necessary infrmatin needed t create a cntrller HyperLynx timing mdel frm a vendr s datasheet. Three examples f different cntrller types were used t describe the mdel creatin prcess. n rder t create these mdels, it is imprtant that the datasheet parameters are translated int the HyperLynx required parameters crrectly. nce the parameters are translated crrectly, the mdel can be created using the HyperLynx Timing Mdel Wizard (GU-based) r using the HyperLynx Timing Editr (Syntax-based). A less rbust cntrller timing mdel can be created quickly and easily using the Timing mdel wizard r a mre rbust mdel can be created syntactically.