VITERBI DECODER Application Notes
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1 VITERBI DECODER Applicatin Ntes
2 Table f Cntents GENERAL DESCRIPTION... 3 FEATURES... 3 FUNCTIONAL DESCRIPTION... 4 INTERFACE... 5 Symbl... 5 Signal descriptin... 5 Typical Cre Intercnnectin... 6 IMPLEMENTATION DATA... 6 Perfrmance Page 2
3 GENERAL DESCRIPTION Viterbi encding is widely used fr satellite and ther nisy cmmunicatins channels. There are tw imprtant cmpnents f a channel using Viterbi encding: the Viterbi encder (at the transmitter), the Viterbi decder (at the receiver). A Viterbi encder adds extra infrmatin in the transmitted signal t reduce the prbability f errrs in the received signal that may be crrupted by nise. A Viterbi decder perfrms a maximum likelihd detectin f 1 bit data transmitted ver a channel with inter-symbl interference (ISI). The 1-bit data t be transmitted is encded with an n-bit cnvlutinal cde in the cnvlutinal encder. The fllwing figure shws the simplified data path frm the Cnvlutinal Encder t the Viterbi Decder. Figure 1. Simplified data path frm the Cnvlutinal Encder t the Viterbi Decder. Viterbi encding (cnvlutinal encding)applied in: FEATURES wireless telecmmunicatin: digital cellular phnes satellites satellite grund statins cnsumer electrnics CD players HDTVs. Decding f cnvlutinal cdes, Hard Decisin Decding, Trace-back methd fr survivr memry, Parameterized architecture allws fr custmizatin f the fllwing functins: Cnvlutinal cde definitin parameters: - cde rate, - cde generatin vectrs, - cde cnstraint length. Page 3
4 The survivr memry wrd length (RAM) The initial path metric fr state 0, Parallel r serial (reverse r crrect rder) data utput frmat. FUNCTIONAL DESCRIPTION Figure 2. Viterbi Decder Blck Diagram. The Viterbi cre is partitined int mdules as shwn in figure 2 and described belw: Add Cmpare Select (ACS) Unit The ACS unit calculates the path metrics t find the minimum path. The ACS unit has a RADIX-4 architecture. The number f ACS units is parameterizable. Viterbi Cntrl Unit The cntrl blck cntrls the peratin f Viterbi decder. This blck handles the survivr memry management. The state-machine cntrls the alternatin f reading new branch metrics and trace back. During trace back cntrl unit reads the decisin values frm external memry and utputs the decded bits. It recnstructs the actins in the reversed rder by updating the state-register with a decisin value pinted by the frmer state value but the decded bits are utput in crrect rder. Viterbi Memry Viterbi memry is a RAM memry, which stres the trace back values during calculatin. Page 4
5 INTERFACE Symbl Figure 3 shws Viderbi Decder cre symbl. Figure 3. Decder Viterbi cre symbl. Signal descriptin The descriptins f the cre signals are represented in the belw table. SIGNAL TYPE DESCRIPTION clk input Glbal clck clk_en input Clck enable, active high reset input Asynchrnus reset, active high lad_data input Enables data lading, active high bit_in(0:x) input Input values, the width depends n the cde parameters datatdec(0:x) input Data frm external memry valid_ut utput Valid utput data, active high bit_ut utput Decded utput bit lad_ready utput Ready fr data, active high wrmem utput Write enable t external memry, active high addr(0:x) utput Address t external memry datatmem(0:x) utput Data t external memry Page 5
6 Typical Cre Intercnnectin Figure 4. Typical Decder Viterbi cre intercnnectin with external memry. Cmpnents: Viterbi decder cre RAM - external data memry 32 bytes IMPLEMENTATION DATA Perfrmance The fllwing table illustrates the VITERBI DECODER cre perfrmance in Xilinx VIRTEX, Xilinx 4000 series, Xilinx Spartan and Altera Flex6000 devices. Target device XC4013XLBG XCV300BG352-5 S30VQ100-3 EPF6024ATC144-1 Area Number f CLBs: 383 Number f Slices: Page 6 Number f CLBs: System clck fmax MHz MHz MHz 22.57MHz 383 LCs: 1355
7 Results btained fr the parameters in the table belw. Parameter Value Number f states in trellis 16 Number f bits t represent transitin values 8 Length f the trace back 32 Length f the received burst 5 Initial path metric fr state 0-4 Survivr memry wrd length 8 Page 7
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