Automated Design of an ASIP for Image Processing Applications

Transcription

1 Autmated Design f an ASIP fr Image Prcessing Applicatins Henj Scht and Henk Crpraal Delft University f Technlgy Department f Electrical Engineering Sectin Cmputer Architecture and Digital Technique P.O. Bx 5031, 2600 GA Delft, The Netherlands H.J.M.Scht@FEL.tn.nl, H.Crpraal@et.tudelft.nl Abstract. This paper presents the design f highly ptimized TTA architectures fr image prcessing applicatins. An autmatic prcessr design framewrk as described in [2] is used. Specialized hardware is used t imprve the perfrmance-cst rati f the prcessrs. An explrer searches the design space fr slutins that are gd in terms f cst and perfrmance. We shw that architectures can be fund that efficiently execute very different algrithms at lw cst. A hardware feasible architecture is presented that efficiently executes a set f image prcessing algrithms and perfrms almst equally r better than alternative, cmmercial-available slutins d. 1 Intrductin In this paper, we shw the design f an applicatin specific instructin set prcessr (ASIP) fr a set f image prcessing algrithms. Prcessrs and cde are generated, trying t explit the instructin level parallelism f image prcessing algrithms. We shw that prcessrs can be generated that efficiently execute very different algrithms at lw cst. We add applicatin specific hardware and functinality t imprve the perfrmance cst f the prcessrs. The architecture f the ASIP we develp is a Transprt Triggered Architecture (TTA) [2]. An autmated design framewrk, called the MOVE framewrk [], is used fr the develpment f the VLIW like prcessr. It tries t find an architecture with an ptimal cst/perfrmance rati. The designer can use Special Functin Units (SFUs) t imprve the cst-perfrmance rati f an architecture. These SFUs can be incrprated in the MOVE framewrk. Our wrk n the design f a highly ptimized prcessr architecture differs frm thers [3] in that we use TTAs and applicatin specific hardware (SFUs) in rder t find architectures with higher perfrmance-cst ratis. The next sectin describes the image prcessing algrithms we used. Sectin 3 shws the mapping f the algrithms t TTAs. Sectin 4 presents the results and cnclusins. A. Bde et al. (Eds.): Eur-Par 2000, LNCS 1900, pp , Springer-Verlag Berlin Heidelberg 2000

2 1106 Henj Scht and Henk Crpraal 2 Image Prcessing Algrithms Fur image prcessing algrithms were mapped t TTAs. A clr cnversin algrithm, and three gray-scale neighbrhd algrithms: cnvlutin and tw edge detectin algrithms n a 3x3 area. Here we cncentrate n the clr cnversin algrithm. Clr cnversin is an peratin frm the area f clr image prcessing. It is used t cnvert between clr representatins e.g. a clr in RGB has t be cnverted t represent the same clr using CMYK clr cmpnents. There are several methds t perfrm clr cnversin. In ur case we uses lkup tables (LUTs) and triinterplatin. Using this methd, the cnversin f a clr P starts with searching the lkup table fr the eight nearest pints. Seven linear interplatins are perfrmed n these pints. Figure 1 shws pint P and its eight nearest pints that crrespnd with the crners f a cube. The interplatins are shwn as bld lines. The final interplatin is perfrmed n V and W. The distance a f pint V t pint P and the distance 1 - a f pint W t pint P are used as interplatin cefficients a B P = (1-a)W + av 0<a<1 V W P G 000 R Fig. 1. Tri-linear interplatin f pint P in the RGB space. Since the calculatin f each pixel is independent f ther pixels, in principle, all pixels can be prcessed in parallel. The amunt f parallelism that can be attained by TTAs is determined by the maximum number f available resurces and the ability f the cmpiler t explit the parallelism. In ur implementatin, we use a LUT f 4 K entries. This size results in reasnable interplatin accuracy at lw cst. Higher accuracy requires larger lkup tables. The LUT is addressed using the 4 mst significant bits f each clr cmpnent. The 4 least significant bits are used fr the interplatin distance giving interplatin cefficients f 0, 1/16,... 16/16. We aim t achieve a perfrmance that is cmparable r better than that f available slutins (12.5 Mpixels/s [7]), at lwer cst.

3 Autmated Design f an ASIP fr Image Prcessing Applicatins Mapping the Algrithms t TTAs The main cmpnents f the MOVE framewrk are a retargetable C/C++ cmpiler, a prcessr generatr and hardware mdeller and a design explrer. The explre tl searches the design space fr architecture slutins using hardware cst and perfrmance as its main design criteria. The explre tl drives bth the cmpiler and the hardware mdeler in rder t find architecture slutins with a gd perfrmance/cst rati. A paret-curve with the resulting architecture slutins is prduced, frm which the designer chses an architecture cnfiguratin. The mapping f the algrithm starts with analyzing the slutins that are fund in case we use basic peratins nly. The curve w/ SFUs in figure 2 shws that the latency fr high cst architectures remains quite lng. E.g.. an architecture f cst 300 (in integer units) des clr cnversin f a single pixel in 11 cycles. Fig. 2. The TTA design space fr the clr cnversin applicatin. An enrmus imprvement in perfrmance is achieved when SFUs are used. Parts f the algrithm that are implemented in hardware are the lkup peratin and a linear interplatin. Figure 3 shws the dataflw symbls f different implementatins f the interplatin. They are implemented by extending a multiplier FU with these specific functins. The impact f the SFUs n architectures cst/perfrmance is als shwn in figure 2. Slutins with 2 t 60 times better perfrmance at equal cst are fund. x a y 16-a * * + x y a Interpl x.y packed Interpl a Fig. 3. Dataflw symbls f the interplatin functins Architectures that execute a set f algrithms are fund by cmbining multiple algrithms in an applicatin. Resulting architectures shwed a small lss in

4 1108 Henj Scht and Henk Crpraal perfrmance fr each algrithm, but verall they perfrmed very well, as can be seen in figure 4. Fig. 4. The TTA design space fr bth clr cnversin and neighbrhd peratins. 4 Results A feasible prcessr cnfiguratin which efficiently executes the whle set f algrithms is selected frm the curve in figure 4. In this cnfiguratin, marked with +, the in- and utputs f each FU and register file are cnnected t all buses, which is impractical. We therefre remve as much cnnectins as pssible withut perfrmance lsses. The resulting prcessr is shwn in figure5. It can d clr cnversin at 5.3 cycles/pixel. It cntains 8 buses and 11 functinal units (FUs). The register file, as shwn, cntains many read and write prts. Hwever, the tls allw t split up this file int multiple small register files [4][5]. Fig. 5. A prcessr cnfiguratin that efficiently executes the clr cnversin algrithm and the whle repertire f neighbrhd peratins.

5 Autmated Design f an ASIP fr Image Prcessing Applicatins 1109 Table 1 gives an verview f the perfrmance f cmmercial available slutins [6]-[11] and ur slutin. It is seen that the Imagine and the C6x perfrm better fr the cnvlutin applicatin than ur slutin des. Fr the ther algrithms ur slutin perfrms significantly better. Table 1. Perfrmances f the applicatins fr ther available slutins and ur slutin. Perfrmance (Mpixels/s) Algrithm 66 MHz PixelMagic 75 MHz TI 200 MHz Chamelen 100 MHz cnvlutin n.a. 27 Min-max peratin < n.a. 27 Edge detectin < 15 < 11.8 n.a. 23 Clr cnversin Cnclusin In this paper, we shwed that the MOVE framewrk can be used t find slutins fr digital image prcessing algrithms. Slutins can be fund fr applicatins cntaining several algrithms, including very different nes. Furthermre, hardware feasible slutins are fund that perfrm almst equally r better than alternative, cmmercially available slutins. A large part f the prcessr design is dne autmatically. Hwever, a lt f manual interactin is required in the identificatin and applicatin f Special Functin Units. Autmatin f this part f the design trajectry is currently being researched [1]. References 1. Marnix Arnld and Henk Crpraal, Autmatic Detectin f Recurring Operatin Patterns, Cdes 99, May Henk Crpraal, Micrprcessr Architectures; frm VLIW t TTA, Jhn Wiley, 1998, ISBN X 3. Jseph A. Fisher, Pal Farabschi and Guiseppe Desli, Custm-Fit Prcessrs: Letting Applicatins Define Architectures, 4. Jan Hgerbrugge, Cde Generatin fr Transprt Triggered Architectures, Delft University f Technlgy, Jhan Janssen and Henk Crpraal, Partitined Register File fr TTAs, Delft University f Technlgy 6. Redfrd, J., Iler, J. and Berger, E., The PM44: A Single-Chip SIMD GigaOp DSP fr Imaging, Pixel Magic Inc, Andver MA 7. The Barc Chamelen ASIC; A very high speed, very high accuracy, clr crrectin utility, Barc Graphics, Redfrd, J., Iler, J. and Berger, E., The PM44: A Single-Chip SIMD GigaOp DSP fr Imaging, Pixel Magic Inc, Andver MA 9. Evaluatin f the Perfrmance f the C6201 Prcessr & Cmpiler, Lughbrugh Sund Images plc., TMX320C6201 DIGITAL SIGNAL PROCESSOR, Texas Instruments Inc., The Imagine engine; Dcumentatin & User Manual, Arcbel Graphics B.V., March 1994