100G SERDES Power Study

Transcription

1 100G SERDES Pwer Study Phil Sun, Cred IEEE 802.3ck Task Frce

2 Intrductin 100Gbps SERDES pwer challenge and lwer-pwer slutins have been presented. sun_3ck_01a_0518 intrduced balanced lwer-pwer EQ, training prtcl, and silicn test results. healey_3ck_01b_0718 pinted ut extensins t TX FFE can imprve margin while keeping lw C2M pwer. welch_3ck_adhc_01_ cncluded pwer budget fr C2M interface is very little fr sme future mdules. lim_3ck_01b_0718 shwed 8 FFE taps may be needed fr C2M and SERDES pwer may be a cncern. This cntributin is t discuss 100G SERDES pwer f different SERDES architectures. Pwer ptimizatin and shrink may be very different fr each design and each prcess. PAM4 SERDES requires better linearity, bandwidth, and nise cntrl than NRZ. This cntributin tries t summarize latest papers n PAM4 SERDES, and predict pwer f 100G SERDES by scaling clck frequency. 2 IEEE P802.3ck Task Frce

3 Majr Blcks f a Typical SERDES High-pwer blcks are TX driver, RX FFE/DFE, PLL/clck buffers, CTLE. Sme SERDES als has ADC. FFE and DFE may be implemented in analg r digital dmain depend n whether there is high-precisin ADC. 3 IEEE P802.3ck Task Frce

4 SERDES Structure with Balanced EQ Balanced EQ is prpsed t mve part f the equalizatin frm RX t TX t save pwer. Fr C2M, mdule RX is CTLE nly and hst has extended TX FFE. There are tw pssible structures based n Mdule TX: 1. Asymmetric structure: mdule has shrt TX FFE (e.g. 4 taps with 2 pre). Hst has full RX. 2. Symmetric structure: mdule has extended TX FFE. Hst RX des nt have lng FFE/DFE. Mdule TX Mdule RX Hst TX Hst RX Asymmetric Balanced EQ Shrt FFE (e.g. 4 taps) CTLE nly Extended FFE (e.g. 11-taps) Full RX Symmetric Balanced EQ Extended FFE (e.g. 11-taps) CTLE nly Extended FFE (e.g. 11-taps) Shrter Equalizer Traditinal Structure Shrt FFE (e.g. 4 taps) CTLE + FFE/ DFE with 8 pst cursrs Regular TX FFE (e.g. 6 taps) Full RX Equalizatin Cnfiguratin (assuming 2 pre and 8 pst cursrs fr C2M) 4 IEEE P802.3ck Task Frce

5 PAM4 SERDES Pwer Survey -TX Reference [1] Dicksn [2] Frans [3] Im [4] Upadhyaya [5] Wang [6] Depali [7] Menl ISSCC 2017 JSSC 2017 ISSCC 2017 ISSCC 2018 ISSCC 2018 ISSCC 2018 ISSCC 2018 Technlgy 14nm 16nm 16nm 16nm 16nm 28nm 14nm Data Rate [Gb/s] TX vltage driver FFE taps: 3 Reslutin:30 Current driver FFE taps: 3 Reslutin:5b - vltage driver FFE taps: 4 Reslutin:78-90 slices vltage driver FFE taps: 3 Reslutin:33 slices with vltage driver FFE taps: 4 Reslutin:72 slices DAC FFE taps: 8 Reslutin:8 bit slices fr each tap half cells TX Pwer (mw) Including 34 fr 8-tap FIR TX Pwer Scaled t Gb/s (mw) Including 32mw fr 8-tap FIR Mst f the data rates listed are clse t 56Gbps. Fr the same structure, pwer will be almst duble fr 112Gbps cnsidering majrity f circuit pwer scales with clck rate/bandwidth. Dynamic pwer is prprtinal t CV 2 f clk There are 4 vltage mde drivers. Reslutin and the number f taps are amng the majr cntributrs t the pwer difference. 2.5% reslutins and at least 4 TX FFE taps are assumed fr 100G C2M (healey_3ck_01b_0718). Reslutin and the number f FFE taps f [1] and [5] need t be increased and result in higher pwer fr this applicatin. [7] is an early design f 112G TX with high-precisin DAC. Pwer usually will imprve with time. 5 IEEE P802.3ck Task Frce

6 Traditinal Vltage v.s. DAC Drivers [7] Menl, ISSCC 2018 Summatin circuit f FFE is in analg dmain fr traditinal vltage-mde driver, and in digital dmain fr DAC based TX. Traditinal vltage mde driver pwer scales up quickly with reslutin (and the number f taps). DAC based receiver becmes ppular because f its flexibility in the number f FFE taps and weights. 6 IEEE P802.3ck Task Frce

7 PAM4 SERDES Pwer Survey Reference [1] Dicksn [2] Frans [3] Im [4] Upadhyaya [5] Wang [6] Depali [7] Menl ISSCC 2017 JSSC 2017 ISSCC 2017 ISSCC 2018 ISSCC 2018 ISSCC 2018 ISSCC 2018 Technlgy 14nm 16nm 16nm 16nm 16nm 28nm 14nm Data Rate [Gb/s] RX EQ TX Only CTLE CTLE CTLE CTLE CTLE TX Only 24-tap FFE 1-tap DFE ADC based 10-tap directfeedback DFE 14-tap FFE 1-tap DFE ADC Res (bits) - 8 Nn-ADC 7 3 if FFE/DFE Off 6 2 fr easy channels Nn-ADC - RX Pwer (mw) DSP Pwer nt included Ttal Pwer (mw) DSP Pwer nt included Ttal Pwer at Gb/s (mw) DSP Pwer nt included fr 8.6dB channel fr 13.6dB channel fr 29.5dB channel FFE, Deserializer, PLL, CDR are nt included 350* 545 (PMA 325, digital 220) fr high lss channel 360 w/ FFE/DFE (PMA 295, digital 65) 664* w/ FFE/DFE fr 8.6dB channel fr 13.6dB channel fr 29.5dB channel (FFE, Deserializer, PLL, CDR are nt included) 360 fr 8.6dB channel fr 13.6dB channel 709 fr 2b 29.5dB channel (FFE, Deserializer, PLL, CDR are nt included) if scaled fr 56G and 16nm** if scaled fr 56G and 16nm** 419 fr 16nm * [3] ttal pwer is arund 350mW if assuming a 120mW TX. **Assuming 20% pwer saving frm 28nm t 16nm. (pssibly +/-10% estimatin errr fr ne full nde) 7 IEEE P802.3ck Task Frce

8 PAM4 SERDES Pwer Survey Summary Sme latest receiver architectures published n ISSCC and JSSC are listed CTLE nly, direct feedback DFE, and ADC-based. In average TX pwer abut 110mW fr Gbps and 220mW fr Gb/s. [5] and [6] shws ADC-based receiver pwer can be reduced by 350mW at Gb/s by turning ff RX FFE/DFE. SERDES pwer increased abut 51% t enable RX FFE/DFE. As the same design can be used fr bth lng-reach and shrt-reach with ptimized pwer, design cst is reduced. Can receiver FFE/DFE be turned ff fr C2M channels? sun_nea_01a_0517 shws TX FIR effectively cancels bad reflectins fr a 33dB channel. sun_3ck_01a_0518 shws channel utput eye is wide pen fr a 14dB channel with extended TX FIR. N RX FFE/DFE will be needed. twmbly_3ck_01a_0718 shws gd perfrmance n a 30dB channel by extending TX FIR. Only 3-tap FFE and DFE n the RX side t deal with material lss. healey_3ck_01b_0718 cmpared perfrmance f TX and RX FFE, and cncluded extended TX FFE can imprve link margin and increase lss budget while keeping a CTLE nly receiver. 8 IEEE P802.3ck Task Frce

9 106.25Gb/s C2M SERDES Pwer 8 pst cursrs Architecture Equalizatin 9 IEEE P802.3ck Task Frce Balanced EQ (1. Asymmetric, 2. symmetric) TX: FIR (2/4 taps fr asymmetric structure, 2/11 taps fr symmetric structure) RX: CTLE TX Pwer*(mW) (symmetric structure) RX Pwer (mw) 239 (by scaling [6]) Relative ttal Pwer (mw) Pwer Difference fr 2x400G Mdule C2M at G (mw) Prjectin with 30% reductin (mw)*** 0 (435 as Baseline fr asymmetric) 28 (463 fr symmetric) 0 fr asymmetric (Ttal 3480) 224 fr symmetric (Ttal 3704) 0 fr asymmetric (Ttal 305) 19 fr symmetric (Ttal 324) 3. Analg DFE ** 4. ADC Based TX: FIR (2/4) RX: CTLE, with DFE taps (by scaling [3], 2 DFE tail tap pwer is very lw) 197 (ttal 632) 1,576 (Ttal 5056) TX: FIR (2/4) RX: CTLE, 6-bit ADC, 8 pstcursr digital FFE 498 (310 by scaling [5] frnt end fr 13.6dB channel; 108 fr FFE by scaling FIR f [7] fr 6b input; 80 fr PLL, deserializer and CDR) 259 (ttal 694) 2,072 (Ttal 5552) 137 (ttal 442) 181 (ttal 486) Pwer f different SERDES structure is derived frm the survey results. 8 pstcursr taps are assumed. *assuming 180mw fr a 6 bit DAC based n feedbacks f ad hc meeting. TX FIR is 4mw per tap based n [7]. The asymmetric structure adds 28mW pwer n switch (0.9W fr 32 prts) t trade fr lwest mdule pwer. Symmetric The symmetric structure enables clse t lwest pwer RX fr bth mdule and hst. **DFE tap 1 timing is tight. Assuming it can implemented by ther pwer equivalent ways fr C2M perfrmance. Ttal pwer rati fr architecture 1, 2, 3, and 4 is 1 : 1.06 : 1.45 : ***Brave prjectin fr future ndes with design imprvements.

10 Mdule Pwer Budget 8 Pstcursr Taps 5.1mW 0W -1.8W Electrical I/O Pwer Budget ADC 5.6W Analg DFE 5.1W Balanced EQ 3.5W 16nm Slutins ADC 3.9W Analg DFE 3.5W Balanced EQ 2.4W Pssible Slutins after 30% pwer reductin welch_3ck_adhc_01_ analyzed pwer budget fr electrical I/O. Pwer available fr C2M is 5.1W in the best case, and -1.8W in the wrst case. Average is 3.45W. Balanced EQ is clse t the average pwer budget. Direct feedback is at the edge f best case budget, but DFE errr prpagatin may be a prblem fr C2M interface. Balanced EQ needs extra lgic fr adaptive turning. If management netwrk is used fr this purpse, the extra lgic is mainly fr register access and its pwer shuld be small. 10 IEEE P802.3ck Task Frce

11 C2M SERDES Pwer 5 pst cursrs Besides implementatins in the survey table, FFE with a few taps can als be implemented in analg dmain. Assuming 5 FFE pstcursrs are enugh by tightening channel r relaxing pre-fec BER target, pwer rati f C2M with asymmetric TX FFE, symmetric TX FFE, and analg RX FFE is abut 1.00 : 1.04 : FEE pwer culd be lwer at cst f larger area etc. In this case, pwer rati f these three architectures is estimated t be abut 1.00:1.04:1.30. TX FIR has 4 r 11 taps depending n whether there is RX FFE. The TX in this survey is different frm [7]. Its tail taps are assumed t have less bits than majr taps, and TX pwer is als lwer. 11 IEEE P802.3ck Task Frce

12 Mdule Pwer Budget 5 Pstcursr Taps 5.1mW 0W -1.8W Electrical I/O Pwer Budget Analg FFE Balanced EQ 16nm Slutins If 5 pstcursr taps are needed, 16nm analg FFE based lw-pwer architecture meets budget between best and average. 12 IEEE P802.3ck Task Frce

13 Analg FFE Based Architecture Delay f analg FFE is usually implemented by buffers and passive/active LC delay lines [10, 11, 12]. Circuit distrtin is a challenge if t many FFE taps are required. Main tap will be distrted if there are precursrs and becmes a prblem especially fr PAM4. Reference [10] Mmtaz JSSC 2010 [11] Chen JSSC 2012 [12] Mammei JSSC 2014 Technlgy 65nm CMOS 65nm CMOS 28nm LP CMOS Signaling 40Gb/s NRZ 40Gb/s NRZ 25Gb/s NRZ FFE taps 7 T/2 (3.5 UI) 3 T (3UI) 7 3/4 T (5.25UI) FFE Pwer (mw) chip pwer (mw) Applicatin Repeater CDR CDR If scale [12] fr GBd NRZ n 16nm (assuming 20% prcess shrink with prbably 10% estimatin errr), FFE pwer wuld be 153mw. Higher pwer is expected fr Gb/s PAM4 but hard t estimate withut actual implementatins. ghiasi_3ck_02_0918 derives FFE pwer frm [10]. But [10] is ptimized fr single-lane repeater, nt suitable fr multilane chips [ref 12]. 13

14 Analg FFE Based Architecture Cnt d Delay cell, die size, and eye diagram f [10] [10] achieved very lw pwer using this structure fr a 7-tap T/2 FFE n 65nm. This design is well ptimized fr a single-lane repeater with NRZ signaling. Inductrs are extensively used fr lw pwer at cst f large die size. As it is fr NRZ, device nnlinearity is tlerated and signal swing is very small. Cupling caused by inductrs is less prblematic fr a single-lane repeater which has n cmplicated clck circuits. 14 IEEE P802.3ck Task Frce

15 Analg Based FFE Architecture Cnt d Lng FFE (e.g. 8 pst taps) is very difficult t be implemented by this structure even at latest prcess. If we need 8 pstcursr taps, 9 UI cverage is needed. (7-tap T/2 FFE f [10] cvers 3.5 UI. ) [10] is published 8 years ag, industry is still experimenting different architectures fr lw pwer. This can als be bserved in publicatins. Fr Gb/s PAM4 C2M fr multi-lane mdules, new challenges may result in a lt higher pwer cmpared t [10]. PAM4 can tlerate much less device nnlinearity and nise. Inductrs can be used t save pwer, but need t be cntrlled t avid very large die size and cupling issue. Inductr size des nt scale with prcess. Delay needs t increase frm 12.5ps t 18.8ps. Simply adjusting transcnductance amplifier will result in lw delay cell bandwidth and degrade perfrmance. Mre inductrs may be needed fr this purpse regardless f prcess. [10] FFE bandwidth is 20GHz with delay cell bandwidth f 41GHz. T keep the same perfrmance fr Gb/s PAM4, mre than 30% bandwidth increase is likely needed. Signal swing needs t be greatly increased. As a cnsequence, device nnlinearity becmes mre challenging. It can be very misleading t estimate Gb/s PAM4 C2M pwer based n [10]. Actual implementatin is needed t quantify pwer increase and check perfrmance related t linearity, nise, r ther challenges. Area and cupling issues are prblematic fr multilane applicatins. Pwer shrink this type f circuit can be bad. Pwer scale acrss multiple prcess may result in huge estimatin errr. (e.g. fr tw generatins, assuming 10% r 30% pwer shrink results in 65% estimatin difference. ) 15 IEEE P802.3ck Task Frce

16 Cnclusins The number f EQ taps impacts architecture chices. If 8 pstcursr taps are needed, pwer f balanced EQ, analg DFE, and ADC based SERDES are cnsidered. The rati is 1 : 1.45 : If 5 pstcursr taps are needed, analg FFE based architecture appears t be mre pwer efficient than the ther RX equalizatin structures. Pwer rati f balanced EQ and analg FFE based SERDES is 1 : 1.3. Fr 16nm SERDES with 8 pstcursr taps, 2x400G mdule pwer is 1.6W t 2.1W lwer by using balanced EQ. The pwer difference is 1.1W and 1.5W after 30% f pwer shrink fr newer technlgy. 16 IEEE P802.3ck Task Frce

17 References [1] T. O. Dicksn, et al., "A 1.8pJ/b 56Gb/s PAM-4 Transmitter with Fractinally Spaced FFE in 14nm CMOS," ISSCC, pp , Feb [2] Y. Frans, et al., "A 56-Gb/s PAM4 Wireline Transceiver Using a 32-Way Time-Interleaved SAR ADC in 16-nm FinFET," IEEE JSSC, vl. 52, n. 4, pp , Apr [3] J. Im, et al., A 40-t-56Gb/s PAM-4 Receiver with 10-Tap Direct Decisin-Feedback Equalizatin in 16nm FinFET, ISSCC, pp , Feb [4] P. Upadhyaya, et al., A Fully Adaptive 19-t-56Gb/s PAM-4 Wireline Transceiver with a Cnfigurable ADC in 16nm FinFET, ISSCC, pp , Feb [5] L. Wang, et al., A 64Gb/s PAM-4 Transceiver Utilizing an Adaptive Threshld ADC in 16nm FinFET, ISSCC, pp , Feb [6] E. Depali, et al., A 4.9pJ/b 16-t-64Gb/s PAM-4 VSR Transceiver in 28nm FDSOI CMOS, ISSCC, pp , Feb [7] C. Menlfi, et al., A 112Gb/s 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS, ISSCC, pp , Feb [8] [9] [10] A. Mmtaz, An 80 mw 40 Gb/s 7-Tap T/2-Spaced Feed-Frward Equalizer in 65 nm CMOS, IEEE JSSC, Vl. 45, N. 3, Mar [11] M. Chen et al., "A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technlgy", IEEE JSSC, vl. 47, n. 3, pp , Mar [12] E. Mammei et al. Analysis and Design f a Pwer-Scalable Cntinuus-Time FIR Equalizer fr 10 Gb/s t 25 Gb/s Multi-Mde Fiber EDC in 28 nm LP CMOS, IEEE JSSC, vl. 49, n. 12, pp , Dec IEEE P802.3ck Task Frce

18 Thanks! 18 IEEE P802.3ck Task Frce