Microelectronic Circuits II. Ch 6 : Building Blocks of Integrated-Circuit Amplifier

Transcription

1 Micrelectrnic Circuits II Ch 6 : Building Blcks f Integrated-Circuit Amplifier 6.1 IC Design Philsphy 6.A Cmparisn f the MOSFET and the BJT 6.2 The Basic Gain Cell CNU EE 6.1-1

2 Intrductin Basic building blcks f IC (Integrated Circuit) Amplifiers - design philsphy f integrated circuits : difference frm discrete circuits - cmparisn between MOSFET & BJT circuits à Appendix 6.A - basic gain cell f IC amplifiers à current-surce-laded cmmn-surce (cmmn -emitter) amplifier - cascde amplifier & cascde current surce - current mirrrs circuits à biasing and lad elements IC Design Philsphy - limited chip area à avid large-valued resistrs & capacitrs (cupling & bypass) - use MOS transistrs nly & small MOS capacitrs in the picfarad - Present CMOS IC prcessing technlgy (2009) * 45-nm minimum channel length * dc vltage supply : 1 à reduced pwer dissipatin * verdrive vltage : 0.1 ~ 0.2 à currently the mst widely used IC technlgy fr analg, digital & mixed circuit - Biplar circuit * higher utput currents * higher reliability : suitable fr autmtive industry CNU EE 6.1-2

3 Typical values f MOSFET parameters Table 6.A.1 Typical alues f CMOS Device Parameters 0.8µm 0.5 µm 0.25 µm 0.18 µm 0.13 µm Parameter NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS NMOS PMOS t x (nm) C x (ff/µm 2 ) µ(cm 2 / s) µc x (µa/ 2 ) t0 () DD () A (/µm) C υ (ff/µm) CNU EE 6.1-3

4 Typical alues f MOSFET Parameters Typical values f MOSFET parameters (submicrn MOS) - Classificatin by the minimum allwed channel length L min : L 0.8 mm à 0.13-mm cmmercially available à 90-, 65, 45-nm prcess (22-nm) - Reduced L min à higher speed r wider bandwidth, 2.3 billin transistrs nt ne chip - Oxide thickness, t x à mm ( mm) - C x ~ 1/t x à increased C x - Increased transcnductance parameters k n/ m n C x, k p/ m p C x à achieves required level f bias current at lwer verdrive vltage à higher transcnductance - Threshld vltage tn & tp : à 0.3 ~ Pwer supply DD : 5 à 1.3 fr 0.13-mm prcess à reduced pwer dissipatin à much larger number f transistrs in the IC chip - Overdrive vltage O : 0.1 ~ 0.2 ( GS t + O ) à saturatin mde : DS > O - prnunced channel length mdulatin effect à A/ decrease, A A/ L decrease à lw utput resistance - higher perating speeds & wider amplifier bandwidth : f T ~ 10GHz CNU EE 6.1-4

5 Typical values f IC BJT parameters Table 6.A.2 Typical alues fr BJTs¹ Standard High-ltage Prcess Advanced Lw-ltage Prcess Parameter npn Lateral pnp npn Lateral pnp A E (µm 2 ) I S (A) β 0 (A/A) A () CE0 () τ F 0.35ns 30ns 10ps 650ps C je0 1pF 0.3pF 5fF 14fF C µ0 0.3pF 1pF 5fF 15fF r x (Ω) CNU EE 6.1-5

6 Typical alues f IC BJT Parameters Typical values f IC BJT parameters (lw vltage prcess) - standard, ld prcess : high-vltage (H) prcess advanced, mdern prcess : lw-vltage (L) prcess - lateral pnp is much inferir t the vertical npn : lw b & large frward transit time t F à higher C de à unity-gain frequency f T is 2 rders f magnitude lwer than npn - dramatic reductin in device size in the advanced lw-vltage prcess à scale current I S reduces by 3 rders f magnitude à base width W B : rder f 0.1 mm à dramatic increase in speed : t F 10 ps (H prcess t F 0.35 ns) à f T : 10 ~ 20 GHz (H prcess 400~600 MHz) - Early vltage A : 35 - Cllectr-emitter vltage : 8 (H prcess : 50 r s) à pwer supply : 15 à 5 r 3.3 CNU EE 6.1-6

7 NMOS npn Circuit Symbl T perate in the Active Mde, tw cnditins have t be satisfied (1) Induce a channel : υ GS t, t Let υ GS t + υ O (2) Pinch-ff channel at drain : υ GD < t r equivalently, υ DS O, O (1) Frward-bias EBJ : υ BE BEn, BEn 0.5 (2) Reverse-bias CBJ : υ BC < BCn, BCn 0.4 r equivalently, υ CE 0.3 CNU EE 6.1-7

8 NMOS FET PMOS FET CNU EE 6.1-8

9 BE > 0 : frward biases EBJ CB > 0 : reverse biases CBJ : switch ff : amplifier : switch n CNU EE 6.1-9

10 Operating cnditins - active mde r active regin : active mde in BJT : saturatin mde in MOSFET - threshld t in MOSFET ~ BE(n) in BJT (almst same) - pinching ff the channel in MOSFET drain ~ reverse biased CBJ in BJT à i D is nearly independent f v D à i C is nearly independent f v C - Asymmetry f BJT à BC(n) is nt equal t BE(n) Symmetrical MOSFET à same t at surce & drain - active mde peratin in BJT & MOSFET à v DS, v CE must be at least 0.1 ~ 0.3 CNU EE

11 NMOS npn Current-ltage Characteristics in the Active Regin 1 W ( ) 2 æ u ö DS id mncx ugs - t ç 1+ 2 L è A ø i G 1 W 2 æ u ö DS mncx uo ç L è A ø 0 i i C B ube / T I Se 1+ i c / b æ u ö CE ç è A ø Lw-Frequency Hybridπ Mdel CNU EE

12 Current ltage Characteristics - i D v GS in MOSFET : square-law characteristic i C v BE in BJT : expnential characteristic (mre sensitive) - Effects f the devices dimensins n its current 1) BJT : area f emitter-base junctin (EBJ), A E à I S variatin in a relatively narrw range : 10 t 1 2) MOSFET : aspect rati W/L variatin in a wide range : 1.0 t 500 à significant design parameter - Dependence f i D (i C ) n v DS (v CE ) in the active regin : channel length mdulatin in MOSFET & base-width mdulatin in BJT à finite input resistance r in the active mde à A in BJT : prcess-technlgy parameter & N relatin w/ dimensin A in MOSFET A/ L : L is design parameter - Gate current in MOSFET 0 & R in lking int the gate infinite finite base current in BJT : i B i C /b & finite R in lking int the base CNU EE

13 Ex. 6.A.1 (a) NMOS w/ W/L10 in 0.18 mm prcess. Find O & GS fr I D 100mA, N channel-length mdulatin 1 æ W ö 2 ( ) I m C 2 ç L è ø D n x O O O 0.23 GS tn + O by I D, W/L & m n C x 387 ma/ 2 frm Table 6.A.1 (b) Find BE fr npn transistr fabricated by L prcess & w/ I C 100mA, N base-width mdulatin I C I e S BE / T by I C, I S 6x10-18 A frm Table 6.A.2 BE ln CNU EE

14 NMOS npn Lw-Frequency T Mdel Transcnductance g m ( ) g I / / 2 m D O æ W ö g ( m C ) ç L è ø m n x O æ W ö g 2( m C ) ç I L è ø m n x D g I / m C T CNU EE

15 Lw-Frequency Small-Signal Mdels - BJT mdel finite base current (finite b) à r p in the hybrid-p mdel à unequal i E & i C in the T mdel, a < 1 - LF mdel f MOSFET BJT w/ b inf. (a1) - pen-circuit vltage gain frm G(B) t D(C) w/ grunded S(E) : -g m r g m r : maximum gain available frm a single transistr f either type à intrinsic gain A 0 - Bdy effect in the MOSFET bdy (substrate) : 2 nd gate bdy-surce vltage v bs à drain current g mb v bs (g mb : bdy transcnductance) g mb cg m (c 0.1 ~ 0.2) Transcnductance - g m in BJT I C / T ( T ~ 25 m at R.T à depend nly n I C ) - g m in MOSFET depends n I D, O & W/L 1 st : similar t BJT g m but small ( O /2 ~ 0.05 ~ 0.15) 2 nd : prprtinal t O fr a given W/L. higher g m by higher O but O is limited by DD 3 rd : prprtinal t I D fr a given W/L. g m in BJT is directly prprtinal t I C CNU EE

16 NMOS npn Output Resistance r L r I r / I ' A A / D I D A C Intrinsic Gain A 0 g m r ( ) A / / 2 A A A ' 2 AL O O ' 2 A 2mn x I C WL D A 0 A / T Input Resistance with Surce (Emitter) Grunded r p b /g m CNU EE

17 Output resistance - rati f A t the bias current (I D r I C ) - r is inversely prprtinal t the bias current Intrinsic gain A 0 - A 0 f BJT : rati f prcess parameter A (35 t 130) & physical parameter T à independent f the device junctin area & f the perating current (1000~5000/) - A 0 f MOSFET 1 st : denminatr O /2 is a design parameter. (>> T ) numeratr A is prcess- & device-dependent, steadily decreasing à 20 ~40/ fr a mdern shrt-channel technlgy 3 rd : A 0 fr a given A/, m n C x & W/L is inversely prprtinal t I D A 0 vs. I D plt - gain A 0 increase as I D is lwered - higher gain A 0 at the lwer bias currents à lwer g m, lwer capacitive lad drive capability, decrease in bandwidth CNU EE

18 Ex. 6.A.2 Cmpare g m, R in at G (B), r & A 0 fr 0.25-mm NMOS and L-tech. npn Tr. Assume I D (I C ) 100mA. Fr L0.4mm, W4mm NMOS, specify O. Fr NMOS 1 æ W ö 2 ( ) I m C 2 ç L è ø D n x O O Thus, O 0.27 æ W ö g 2( m C ) ç I L è ø m n x D mA / R in A0 gmr / Fr npn transistr r ' AL kW I 0.1 D g m IC 0.1mA 4mA/ T 100 Rin rp b0 / gm 25kW 4mA/ r A kW I 0.1mA C A0 gmr / CNU EE

19 NMOS npn high- Frequency Mdel CNU EE

20 CNU EE

21 High-Frequency Operatin - unity-gain frequency (transitin frequency) f T * a measure f the intrinsic bandwidth f the transistr itself w/ capacitive lad effect * inversely prprtinal t the square f L fr MOSFET & W B fr BJT * f T f BJT is entirely prcess determined but f T f MOSFET is prprtinal t O : higher-lw frequency gain by lw O but wider bandwidth by high O è trade-ff between gain and bandwidth * f T f npn Tr. in L prcess : 10 ~ 20 GHz, NMOS in 0.18-mm prcess : 5~15GHz Effect f a capacitive lad n the bandwidth f CS (CE) amplifier - Assume frequencies f interest << f T à neglects the transistr internal capacitances - CS amplifier w/ capacitive lad C L * vltage gain frm gate t drain 1 r sc gmr L -g A u 1 - m O -g mgs ( ro // CL ) gs gs 1+ sclr r + - gain A v at lw frequency : g m r A 0 - freq. respnse f single-time-cnstant (STC) lw-pass type w/ a break (ple) freq. at 1 w P C r L CNU EE sc L

22 - unity-gain frequency r, gain-bandwidth prduct w t : rati f g m and C L * the gain crsses the 0-dB line at w t 1 gm wt A0w P ( gmr ) w t C r C - Fr a given C L, higher g m à larger gain-bandwidth prduct à bandwidth increases as bias current is increased L CNU EE L

23 Design Parameters - design parameters fr BJT : I C, BE, & I S (r area f emitter-base junctin A E ) * I C is expnentially related t BE (D BE 60m à 10 changes in I C ) * A E can vary ver the narrw range à I C is nly effective design parameter - design parameter fr MOSFET : I D, O, L & W * trade ff in L value - higher speed (wider bandwidth) à lwer L - higher intrinsic gain à larger L - L : 25% t 50% greater than L min * O : range f 0.2 ~ 0.4 * fr a given L & O, I D is prprtinal t W/L - I D (r W/L) : N bearing n A 0 & f T - I D affects g m à gain-bandwidth prduct - dc gain remains unchanged, increasing W/L (r I D ) increases bandwidth prprtinally (g m ~ I D & r ~ 1/I D ) CNU EE

24 Ex. 6.A.3 (a) npn transistr in L prcess w/ C m~c m0. Find g m, r, A 0, C de, C je,c p, C m, f T & f t in 1-pF lad capacitance fr I C 10mA, 100mA & 1mA. g m IC IC A 35 40I A/ r I I W C A0 T C C A / T C t g I I F C 2C je0 10 ff de F m C C + p de je Cm 0 5fF C C C f T 2p g m m m ft p CL 2p 1 10 ( Cp Cm ) g g I C g m (ma/) r (kω) A 0 (/) C de (ff) CNU EE C je (ff) C π (ff) C µ (ff) f T (GHz) f t (MHz) 10µA µA mA

25 (b) NMOS in 0.25-mm prcess w/ L0.4mm, O Find W/L, g m, r, A 0, C gs, C gd,c p, f T & f t in 1-pF lad capacitance fr I D 10mA, 100mA & 1mA. 1 W I m C 2 L 2 D n x O 1 W 1 W I 2 L 16 L D g m I D I D 8I D A/ / / 2 O r ' AL W A0 gmr 16 / I I I D D D 2 2 C gs WLCx + C u W W 3 3 C C 0.6W gd u f T 2p g m ( C gs + C gd ) f t g m 2pC L I D W/L g m (ma/) r (kω) A 0 (/) C gs (ff) C gd (ff) f T (GHz) f t (MHz) 10µA µA mA CNU EE

26 Basic Gain Cell CS and CE amplifier with Current-surce lads - basic gain cell in an IC amplifier CS r CE transistr laded with a cnstant-current surce à replace R D & R C with cnstant-current surce - difficulty fr R with precise values in IC à current surces using transistrs - current surce CS & CE amplifiers w/ a very high (ideally infinite) lad R à much higher gain current-surce laded r active laded CNU EE

27 CS & CE Amplifier w/ Current-Surce Lads Small-signal analysis f the active-laded CS & CE amplifiers - Q 1 is biased at I D I & I C I - DC bias vltage DS & GS ( CE & BE ) are determined by negative feedback à MOSFET is biased in saturatin regin & BJT is in active regin à refer t active regin fr MOSFET & BJT - Small-signal equivalent circuit : ideal current-surce à infinite resistance à pen circuit - active-laded CS amplifier R A -g r R in v - active-laded CE amplifier m r R A -g r R r in r p v m - bth vltage gains g m r à maximum gain btainable in a CS r CE amplifier à intrinsic gain A CNU EE

28 CNU EE Intrinsic Gain A Intrinsic gain f BJT - Early vltage A : 5 ~ 35 (100 ~ 130), thermal vltage T : rm temperature à A : 200 ~ 5000 / & independent f transistr junctin area & its bias current T A m C A T C m r g A I r I g Intrinsic gain f MOSFET - Overdrive vltage O : 0.15 ~ 0.3 à O /2 ~ 3 t 6 higher than T - A is increased by using a lnger L & lwer O à decrease in amplifier bandwidth à A : 20 ~ 40 /, an rder f magnitude lwer than a BJT O A O A D A D A D x n O D m L A I L I r I L W C I g / / 2 2 ) ( 2 2 m

29 Effect f Output Resistance f Current-Surce Lad Current-surce lad à PMOS transistr biased in the saturatin regin t prvide the required current I CNU EE

30 Effect f Output Resistance f Current-Surce Lad - Q 2 large-signal MOSFET mdel: I 1 m p 2 æw ö ( C ) ç [ - - ] x è L ø 2 DD G tp 2 r 2 A2 I - current-surce lad has a finite utput resistance r 2 such as (b) - ltage gain is reduced t g m1 (r 1 r 2 ) frm g m1 r 1 v A º -g ( r r ) v v i m If Q 1 & Q 2 has the same Early vltage, r 1 r 2 & half gain A v 1-2 g m r A CNU EE

31 Increasing Gain f the Basic Cell Hw can we increase the vltage gain btained frm the basic gain cell? - raise the level f the utput resistance f bth the amplifying & lad transistr - CS amplifying Tr. Q 1 + utput equivalent circuit - A black bx between D f Q 1 & a new utput terminal d 2 - The black bx passes the same Q 1 utput current g m1 v i but with the utput resistance increased by a factr K à current buffer CNU EE

32 Increasing Gain f the Basic Cell The black bx passes the current g m1 v i right thrugh but raise the resistance level by a factr K à current buffer - Current buffer passes the current but raises the resistance level à cmmn gate (CG) r cmmn base (CB) amplifier : unity current gain - ltage buffer passes the vltage but lwers the resistance level à surce (CD) & emitter (CE) fllwer - Hw t raise the utput resistance f the amplifying transistr and current-surce lad à use a current buffer - Placing a CG (r CB) circuit n tp f the CS (r CE) amplifying transistr t implement the current-buffering actin à cascding CNU EE