0.5 µw Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process

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1 J. Lw Pwer Electrn. Appl. 2012, 2, ; di: /jlpea OPEN ACCESS Article Jurnal f Lw Pwer Electrnics and Applicatins ISSN µw Sub-Threshld Operatinal Transcnductance Amplifiers Using 0.15 µm Fully Depleted Silicn-n-Insulatr (FDSOI Prcess Pitr Olejarz 1, Kyungchul Park 2, Samuel MacNaughtn 2, Mehmet R. Dkmeci 3 and Sameer Snkusale 2, * Electrical and Cmputer Engineering, Nrtheastern University, Bstn, MA 02155, USA; lejarz.p@neu.edu NanLab, Electrical and Cmputer Engineering, Tufts University, Medfrd, MA 02155, USA; s: kyungchul.park@tufts.edu (K.P.; samuel.macnaughtn@tufts.edu (S.M. Center fr Bimedical Engineering, Department f Medicine, Brigham and Wmen s Hspital, Harvard Medical Schl, Bstn, MA 02115, USA; mdkmeci@rics.bwh.harvard.edu * Authr t whm crrespndence shuld be addressed; Sameer.Snkusale@tufts.edu; Tel.: ; Fax: Received: 15 March 2012; in revised frm: 8 May 2012 / Accepted: 8 May 2012 / Published: 18 May 2012 Abstract: We present a lw vltage, lw pwer peratinal transcnductance amplifier (OTA designed using a Fully Depleted Silicn-n-Insulatr (FDSOI prcess. Fr very lw vltage applicatin dwn t 0.5 V, tw-stage miller-cmpensated OTAs with bth p-channel MOSFET (PMOS and n-channel MOSFET (NMOS differential input have been investigated in a FDSOI cmplementary metal xide semicnductr (CMOS 150 nm prcess, using 0.5 V threshld transistrs. Bth differential input OTAs have been designed t perate frm the standard 1.5 V dwn t 0.5 V with apprpriate trade-ffs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 db-bandwidth/pwer metric f 9.6 db/39.6 KHz/0.48 µw at 0.6 V and 46.6 db/45.01 KHz/10.8 µw at 1.5 V. The PMOS input OTA has a simulated metric f 19.7 db/18.3 KHz/0.42 µw at 0.4 V and 53 db/1.4 KHz/1.6 µw at 1.5 V with a bias current f 125 na. The fabricated OTAs have been tested and verified with unity-gain cnfiguratin dwn t a 0.5 V supply vltage. Cmparisn with bulk prcess, namely the IBM 180 nm nde is prvided and with relevant discussin n the use f FDSOI prcess fr lw vltage analg design.

2 J. Lw Pwer Electrn. Appl. 2012, Keywrds: sub-threshld; weak inversin; analg design; OTA; lw pwer; FDSOI 1. Intrductin The grwth in the area f prtable bisensrs, handheld wireless devices and implanted medical devices has created mre interest in lw pwer circuits [1]. Advances in CMOS technlgy have allwed fr lwer dynamic pwer dissipatin, higher speed f peratin, higher density and many ther advantages. Silicn-On-Insulatr (SOI technlgy is being prpsed as the next nde in the design f lw pwer digital Very Large Scale Integratin (VLSI circuits. This technlgy allws fr further decrease in pwer and thus heat dissipatin by, first, extending the trend in minimizing the vltage supply and, secnd, by reducing the capacitance; as the insulated lcalized bdy reduces the capacitance and thus minimizes the required charge t create the channel. These tw benefits lwer the dynamic pwer, which fr digital circuits is apprximately prprtinal t CV 2 f, where C is the sum ttal f all the capacitances in the circuit, V is the pwer supply, and f is the frequency f peratin. We als expect that these benefits will carry ver t analg circuits if apprpriate analg-favrable ptins such as high transcnductance, higher utput impedance, etc. can be prvided in these prcesses; thus eventually allwing ne t achieve a mixed-signal system n chip (SC slutins. Whereas the devices in the standard bulk CMOS prcess are fabricated n the silicn bulk/substrate, the devices in the SOI are fabricated n a thinner silicn layer, which is separated frm the bulk by an insulatin layer. The main advantage will be the reduced capacitance, hence increased speed, and reduced cupling r interference thrugh the substrate that reduces verall nise. Lw pwer amplifiers in standard SOI prcesses have been demnstrated in previus studies [2,3]. The SOI prcess cmes in tw types: the partially depleted SOI (PDSOI prcess and the fully depleted SOI (FDSOI prcess. In FDSOI, the tp silicn layer is much thinner than in PDSOI (<100 nm vs. >100 nm. The PDSOI prcess als exhibits a flating bdy effect, as the regin under the channel is partially depleted f charges, leading t sme charge accumulatin. Since the bdy is nt cnnected t any ptential, the accumulated charge alters the threshld vltage f the devices and culd result in transistrs exhibiting large threshld vltage variatin within the same die. In FDSOI, the thinness f the silicn under the channels results in full depletin and n charge accumulatin, and while the bdy is still flating, the effect n the threshld vltages f the transistr is unifrm acrss the die. This makes FDSOI an ideal chice fr analg circuitry where prcess variatins can result in high ffsets r cmmn mde nise. Bth prcesses have been ptimized and brught t market fr digital designs. In such designs, where ne cares merely whether the switch is turned n r ff, the flating bdy r a kink effect in such SOI prcesses causes nly minr degradatin, such as a shift in threshld vltage. This may limit the speed f peratin f the device by affecting the delay f the lgic cell and may affect the nise margin [4]. Hwever simple design appraches suffice t mitigate such issues in digital applicatins. In analg design such shifts may result in nn-linearity effects, nise degradatin and dynamic range especially in lw vltage implementatins where vltage headrm is nt sufficient.

3 J. Lw Pwer Electrn. Appl. 2012, FDSOI is nw als an analg cmpatible prcess as dides, capacitrs and resistrs are part f the available technlgy. Given that nt much has been studied in terms f analg design, we are planning n studying basic analg blcks in such a prcess. Furthermre, these prcesses are being ptimized fr very lw supply vltages fr bth digital and analg circuitry. Lw pwer applicatins such as bimedical implantable devices and thers applicatins require high energy efficiency and perating the transistrs in saturatin regin is nt t favrable. Sub-threshld regin r weak inversin regin prvides the best ptin fr the highest energy efficiency when the frequency r bandwidth is nt an imprtant requirement [5]. Besides the benefits f supply vltage and thus pwer reductin in weak inversin peratin, sub-threshld peratin can als prvide the highest transcnductance (g m fr a given drain current [6]. Fr the chsen prcess, as well as the IBM 180 nm nde, we bserve a high number f g m /I d in weak inversin, as shwn in Figure 1. The IBM 180 nm prcess was chsen as this technlgy has already been validated fr analg design in the sub-threshld peratin with cnventinal bulk devices [7]. Given the benefits f sub-threshld peratin, ur fcus in this paper is n verifying its suitability in realizing a tw stage peratinal amplifiers with ultra-lw pwer f less than 0.5 µw in a sub-threshld regin ptimized 150 nm FDSOI CMOS digital prcess. Figure 1. g m /I d curve f PMOS and NMOS devices fr MITLL 150 nm FDSOI and IBM CMOS 180 nm. 2. Analysis and Simulatin Results 2.1. FDSOI vs. PDSOI vs. Bulk Prcess Analg design has been prven rbust in standard digital bulk prcesses fr decades, but as the technlgy migrates t Partially Depleted Silicn-n-Insulatr (PDSOI and then nt FDSOI, an

4 J. Lw Pwer Electrn. Appl. 2012, investigatin f the merits f FDSOI fr analg amplifiers is timely. The merits f the technlgy are many, frm the prven shrinking f the CMOS device, the lwer leakage current, less shrt channel effects (SCE, lwer expected V th variatins due t lwer dpant fluctuatins, lwer vltage supply and thus lwer expected pwer cnsumptins. Figure 2 belw displays the cmparisn between bulk PDSOI and FDSOI. Figure 2. Cmparisn between bulk PDSOI and FDSOI silicn prcesses [8]. When cmpared t the PDSOI technlgy, the FDSOI prcess is free f the flating bdy effect and has higher immunity t the kink effect. The kink effect which is due t impact inizatin can be bserved when a discntinuity ccurs in the Ids vs. V ds curve fr higher V ds vltages in strng inversin, where the current increases at a faster rate beynd a certain V ds [4]. This is due t an increase in the bdy ptential, and hence it is mre prevalent in PDSOI than in FDSOI. The kink effect needs t be cnsidered in analg design as it may cntribute t device V th mismatch. With SOI, smaller junctin capacitance results in lwer leakage current, due t less junctin area and the nn-existence f a leakage path t the substrate as the bulk is separated frm the device by an xide layer. Steep sub-threshld slpe fr high gain (and energy efficiency may therefre be achieved in the FDSOI prcess which is impssible in the standard bulk prcess due t the inherent bdy effect. Simulatin results were carried ut t evaluate the benefit f the MITLL FDSOI XLP 150 nm nde prcess when cmpared t IBM s Bulk prcess at the 180 nm nde. The threshld vltages were fund t be 0.22 V fr the NMOS and 0.27 V fr the PMOS in the bulk IBM 180 nm prcess and apprximately 0.45 V 0.5 V in the FDSOI prcess. This digital prcess was f interest as, nt nly was it capable f ultra-lw pwer peratin, but it came with available resistrs and capacitrs that made the biasing and cmpensatin f analg cells pssible. The prcess als claimed an anmalusly steep sub-threshld slpe [9] and the kink effect was nly present abve a V ds f 1.1 V. Keeping devices belw that bias vltage culd thus minimize any kink effects. The sub-threshld slpe and the g m /I d ratis were cmpared fr bth PMOS and NMOS devices. Bth NMOS and PMOS device used have a width f 5 µm and a length f 1 µm. Minimum lengths were avided t mitigate sme shrt channel effects and because cre analg blcks rarely rely n minimum length fr matching purpses. Frm Figure 1, the g m /I d f the FDSOI prcess is maximized fr weak inversin with a max rati f apprx. 42; which is much higher than in the strng inversin regin where the g m /I d varies between 1 and 10 (V gs V th > 0.1 V. When cmparing t IBM s 180 nm bulk CMOS prcess, the g m /I d rati fr very lw I d is 28 fr the NMOS and 32 fr the PMOS. As displayed in Figure 1, the

5 J. Lw Pwer Electrn. Appl. 2012, FDSOI prcess prves t be superir at very lw Id fr bth MOS devices that makes it an excellent chice fr very lw pwer applicatin. The sub-threshld slpe factr is a significant parameter fr the weak inversin peratin f a device in the intended V range f peratin. Its theretical lwer limit is 60 mv/dec, the slpe factr S can be btained in the fllwing way [10]: S = ln10 ( dvgs d ln I d (1 At very lw V gs f 0.25 V, the slpe f the FDSOI prcess is 50 mv/dev fr the NMOS and 52 mv/dev fr the PMOS device. Fr the Bulk prcess, it is fund t be 82 mv/dev fr bth f the NMOS and the PMOS device. Figure 3 displays the lgarithmic drain current versus V gs, displaying that the FDSOI prcess can prvide a superir sub-threshld slpe t the 180 nm bulk prcess at a supply vltage f 0.5 V. As such the FDSOI prcess was the right chice t investigate sub-threshld analg design. Figure 3. Sub-threshld slpe f FDSOI and Bulk CMOS devices (VDD = 0.5 V. Other advantages f the FDSOI prcess include reduced crsstalk, eliminatin f latch-up hazards, better transistr islatin (e.g., nise immunity, lwer junctin capacitance, and lwer surce-drain leakage [6]. These are all due t the reduced cupling t the substrate, as in effect all the devices are islated frm the bulk; and the n-type and p-types devices are mre islated frm each ther. The main disadvantages f the FDSOI prcess when cmpared t the bulk are the higher csts, which wuld cme dwn as the prcess becmes mainstream, the V T sensitivity t the silicn thickness, the higher series resistr and the flating bdy effects [6]. It is hwever imprtant t realize

6 J. Lw Pwer Electrn. Appl. 2012, that, as with any new technlgy, the ttal cst f prductin cmes dwn nce the technlgy becmes mainstream and is being mass prduced Design f Tw-Stage Differential Pair OTAs In this paper, ur gal was t utilize this advanced FDSOI prcess t realize a cmplete peratinal transcnductance amplifier with bth PMOS and NMOS input transistrs and explre the pssibility f aggressively scaling its supply vltage. A PMOS differential pair as well as a NMOS differential pair, as shwn in Figures 4 and 5, respectively, were designed and ptimized t wrk in the sub-threshld regin as well as in strng inversin. Simulatin results pint t a nminal threshld vltage f apprximately 0.45 V 0.5 V fr the chsen device sizes. Bth designs are tw-stage Miller cmpensated OTAs designed t perate ver a 0.5 V 1.5 V range. The PMOS design has its bias current generated ff chip, fr fine tuning f the device n the bench fr ptimal peratin. Its PMOS differential pair as well as the NMOS lad devices use a length f 500 nm, guaranteeing a minimum f matching (prprtinal t ( W * L, while minimizing the vltage f peratin. The NMOS design has its bias current generated n chip with a 1 MΩ resistr t GND. Its bias is set t (VDD VGS/R b fr the chsen VDD. The NMOS differential pair uses a length f 450 nm and the PMOS lad devices use a length f 300 nm. Figure 4. PMOS input differential Amplifier. Figure 5. NMOS input differential Amplifier.

7 J. Lw Pwer Electrn. Appl. 2012, Althugh the minimal length fr this technlgy is 150 nm, n devices in either amplifier used a length f less than 300 nm. This reduces channel length mdulatin and increases utput impedance. Mrever it prvides better matching (prcess variatin is inversely prprtinal t the area and minimizes shrt channel artifacts such as leakage and secnd rder V T dependencies. Only the ESD prtectins structure at each pin ff PMOS dide t VDD and ff NMOS dide t GND use the minimum length f 150 nm expecting these wuld turn n first during an ESD event. The equatins f intrinsic parameters fr a device in sub-threshld regin with sufficient drain-surce bias are as fllw: I D ( VGS VTh nut = I 0 e, D W L KT U T =, 1 < n < 3 q (2 I D g m =, nut g r m = 1 nλu T (3 Leading t the gain f the OTAs t be the fllwing [11]: Avp = g Avn = g Q7 g m m = n MP5 g = n n m rq7 rq 4 rq5 rq10 Q5 ( ( r Q7 + r Q4 r Q5 + r Q10 ( U 1 ( λ + λ ( λ + λ 2 Q7 Q5 T Q7 Q4 Q5 Q10 n m r MP5 r MN 4 r MP3 r MN5 MN5 ( ( r MP5 + r MN 4 r MP3 + r MN5 ( U 1 ( λ + λ ( λ + λ 2 MP5 MN5 T MP5 MN 4 MP3 MN5 (4 (5 Since the amplifiers presented here are differential pairs, in layut all the transistrs have their surce lcal-bdy tied t eliminate any ptential flating bdy effects and t ensure better matching, linearity and mre stable V T ver vltage [12], thus minimizing the disadvantages f the FDSOI prcess frm an analg design standpint. Hwever, we expect that even if such surce bdy cnnectins were nt made, that such metrics wuld be better than in a PDSOI prcess. Since these were designed t perate at ultra-lw pwer, self-heating and temperature cncerns were nt imprtant. Furthermre the kink effects are usually bserved at vltages abve 1 V, thus the risk f kink effect can be mitted as devices were perating belw the vltage f cncern and were ptimized t wrk in sub-threshld. In essence, the technlgy seemed ideal fr ultra-lw vltage and lw pwer peratin Simulatin Results Bth OTAs were simulated with Spectre in a Cadence envirnment using BSIMSOI mdels with varius supplies fr varius biasing cnditins. Bias current is 125 na fr PMOS differential pair OTA. Tables 1 and 2 summarize the varius perating cnditins. AC respnses are presented in Figure 6 and transient results in Figure 7. All simulatins were carried with 1 pf lad.

8 J. Lw Pwer Electrn. Appl. 2012, Table 1. PMOS differential pair OTA simulatin results. VDD (V CM (V Gain (db PM (deg 3dB BW (khz Ttal I (µa Table 2. NMOS differential pair OTA simulatin results. VDD (V CM (V Gain (db PM (deg 3dB BW (khz Ttal I (µa It can be bserved that in bth designs, the gain decreases with a decreasing supply vltage, falling drastically when the devices run ut f headrm and even belw the sub-threshld saturatin (V DS < 3 KT/q ~ 75 mv. It is als wrth pinting ut that fr the NMOS design where the current is cntrlled ff chip; as expected, the gain is higher fr a lwer current as the devices are biased further in the weak inversin regin. Fr the lwest specified vltage and current bias, the amplifiers can reach an ultra-lw pwer f 0.5 µw; hwever, the gain is relatively lw in the 10 db range. With a higher current, the gain increases t 46.6 db fr the NMOS pair amplifier and 55.8 db fr the PMOS differential pair. The results are cmparable with prir wrk [2,3,13]. In a standard SOI prcess, an OTA gain f 44 db was achieved fr a pwer f 3.6 µw when the supply was 1.2 V [2], while in anther FDSOI 180 nm implementatin an OTA with a gain f 64.5 db when the supplies were ±0.75 V fr a current draw f 472 µa and a pwer dissipatin f 708 µw was designed [13]. What is unique in this paper is that the results shw that similar perfrmance can als be achieved in a fully depleted prcess with ptential fr even lwer pwer cnsumptin due t better sub-threshld slpe. Neither amplifier was ptimized fr minimal nise cntributin, as the primary gal was t drive the OTAs in deep sub-threshld while cnsuming ultra-lw pwer. Nise ptimizatin is left fr a future exercise. In bth designs, the main cntributin f nise was flicker nise as the differential amplifier pairs are small: W/L (NMOS_OTA = 9 µm/450 nm and W/L (PMOS_OTA = 10 µm/500 nm. Fr a Supply vltage (VDD f 1.5 V and a cmmn vltage (V cm f 0.75 V, the input referred nise fr the PMOS OTA is nv/sqrt(hz fr a bias current f 1 µa and it is nv/sqrt(hz fr a bias current f 125 na. Fr a VDD f 0.5 V and a V cm f 0.15 V, the input referred nise fr the PMOS OTA is 99.4 nv/sqrt(hz fr a bias current f 1uA and it is nv/sqrt(hz fr a bias current f 125 na. Fr a VDD f 1.5 V and a V cm f 0.75 V, the input referred nise fr the NMOS OTA is nv/sqrt(hz and it is nv/sqrt(hz fr a VDD f 0.6 V and a cm f 0.3 V. Nise results are reprted at 10 khz.

9 J. Lw Pwer Electrn. Appl. 2012, Figure 6. AC respnse (a PMOS differential pair fr VDD = 0.4 V, CM = 0.15 V, I bias = 125 na; (b NMOS diff pair, VDD = 0.6 V, CM = 0.3 V. (a (b

10 J. Lw Pwer Electrn. Appl. 2012, Figure 7. Transient respnse (a PMOS amplifier; (b NMOS amplifier in unity gain cnfiguratin. (a 3. Experimental Results (b Bth amplifiers were fabricated n a chip in the MITLL XLP FDSOI 150 nm nde. The micrphtgraph f the fabricated chip is displayed in Figure 8. All the pins fr bth amplifiers were brught ut t pads, allwing fr pssible pst prcessing, as well as fr creating multiple cnfiguratins in the lab. Figure 10(a belw displays transient results fr the PMOS differential pair in unity gain cnfiguratin as in Figure 9, while Figure 10(b displays the transient step respnse fr the NMOS

11 J. Lw Pwer Electrn. Appl. 2012, differential amplifier. The bserved currents are much higher than anticipated and the utput becmes nisy when the supply is lwered. Bth amplifiers wrk dwn t 0.6 V in the lab, ffset errr seems t be the cause f lwer supply perfrmance. The PMOS differential pair is being mnitred by setting the bias current n the bench but wrking biasing currents are much higher than simulatin results predict. As such it culd be expected that a flating bdy culd nly further deterirate the matching, this experiment is left fr a future wrk. Other wrk in the FDSOI prcess have demnstrated the perfrmance f an RF amplifier nt t be degraded fr lwer VDD supplies when the bdy is left flating [14], but here the matching f the differential pairs is f primary cncern. Bth devices rely n capacitrs fr their cmpensatin, the NMOS diff pair als relied n resistrs fr cmpensatin and current generatin. Frm the early results, it can be inferred that the capacitrs and resistrs wrked well and suggests that the MITLL 150 nm SOI prcess is an analg design cmpatible prcess. The bserved ffset and pr yield f functinal devices led us t cnclude that much needs t be dne t ptimize this prcess fr predictable and stable analg peratin. Figure 8. Micrphtgraph f the entire chip (2 mm 2 mm. Figure 9. Schematic f Unity-Gain buffer cnfiguratin fr test set-up.

12 J. Lw Pwer Electrn. Appl. 2012, Figure 10. Measurement f transient respnse fr Unity Gain buffer cnfiguratin (a PMOS differential pair, VDD = 1.2 V; (b NMOS differential pair, VDD = 0.8 V. OUTPUT INPUT (a (b 4. Cnclusins A pair f NMOS and PMOS differential input amplifiers were designed and ptimized t wrk frm belw 0.5 V t 1.5 V in an ultra-lw pwer FDSOI 150 nm prcess. Bth designs have their surce bdy cnnectin tied t minimize any V T mismatch. Simulatin results shw that a sub-threshld ptimized FDSOI device can prvide the capability f lw pwer analg circuit design. Bth designs were tested in the lab with mixed results, primarily attributed t the prcess being nt fully mature. Besides the ffset errrs and nise present, which culd be due t the setup, the FDSOI XLP 150 nm prcess can be a viable prcess fr analg circuitry. As this nde matures and yield imprves, we expect t implement mre designs in the future that will shed mre light n the prcess and its utility fr bimedical applicatins. Acknwledgments The authrs wuld like t thank the Massachusetts Institute f Technlgy Lincln Labratries (MITLL fr the chip fabricatin in the XLP FDSOI 150 nm prcess. References 1. Uchiyama, A.; Baba, S.; Nagatm, Y.; Ida, J. Fully Depleted SOI Technlgy fr Ultra-Lw Pwer Digital and RF Applicatins. In Prceedings f the IEEE Internatinal SOI Cnference, Niagara Falls, NY, USA, Octber 2006; pp Eggermnt, J.-P.; De Ceuster, D.; Flandre, D.; Gentinne, B.; Jespers, P.G.A.; Clinge, J.-P. Design f SOI CMOS peratinal amplifiers fr applicatins up t 300 C. IEEE J. Slid-State Circuits 1996, 31 (2, Silveira, F.; Flandre, D.; Jespers, P.G.A. A g m /I d based methdlgy fr the design f CMOS analg circuits and its applicatin t the synthesis f a silicn-n-insulatr micrpwer OTA. IEEE J. Slid-State Circuits 1996, 31 (9,

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