Four Switch Three Phase Inverter with Modified Z-Source

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2 Fur Switch Three Phase Inverter with Mdified Z-Surce Ragubathi. D, Midhusha. S and Ashk Rangaswamy, Department f Electrical and Electrnics Engineering, Sri Shakthi Instititute f Engineering and Technlgy, Cimbatre, INDIA Abstract The prpsed tplgy cmbines the advantages f a traditinal fur switch three phase inverter with the advantages f z-surce impedance netwrk. This system gives new inverter cnfiguratin which can perfrm the peratin f a chpper and vltage surce inverter with lw cst and maximum pwer. And als switching stress is reduced by the switched inductrs cncept, which will cause the equipment ageing. Here the current can flw in the zer vectrs als, because any ne f the three phase is cnnected t the midpint f the tw dc link capacitrs. The need fr variable speed infuses a greater fcus t invite state f art cntrl mechanisms. It is the ability f clsed lp algrithm that allws the mtrs t enjy speed cntrl ver a designed perating range. The results were btained by using the MATLAB simulatin. IndexTermst; z surce inverter, fur switch three phase inverter, vltage sags. I. INTRODUCTION The variable speed drive (VSD) cntinues t evlve as a technlgy and recgnize the entire perspective f the drive industry. The primary functin rients t cnvert electrical pwer t the usable frm fr cntrlling speed, trque and directin f ac mtr. The emergence f pwer electrnic cnverters espuses a new dimensin and prvides and prvides measures t arrive at the sphisticated nature f utilities. Thugh the hsts f methds are in existence t cntrl the speed f the drive mtrs, still better techniques are required t effectively assuage the preferred speed and meet the needs f new and existing circuit applicatins. T reduce the cst f the inverter and t bst up the vltage, this switched inductr z-surce fur switch inverter which gives the chpper peratin includes and prvides the gd slutin. These switched inductrs are mainly used t high bsting the vltage peratin and prtect the switches during the sht thrugh perid. T achieve high level bst cnversin withut using chpper, this cnverter was designed. In a traditinal vltage surce inverter, the tw switches f the same phase leg can never be gated n at the same time, because, that peratin wuld cause a shrt circuit (shtthrugh) t ccur that wuld destry the inverter. And als there is n greater utput vltage than the input DC bus vltage. These drawbacks can be vercme by the new fur switch three phase mdified Z-surce inverter that uses an impedance netwrk (Z-netwrk) t replace the traditinal dc link. The Z-surce inverter beneficially infuses the shtthrugh states t step up the dc bus vltage by gating n bth the switches f a same leg. Therefre, the mdified Z-surce inverter can step up step dwn the vltage t a desired utput vltage that is greater than the given input dc bus vltage. The reliability f the inverter is imprved t prtect the circuit; during sht thrugh state the circuit shuld nt be destryed. Thus it ffers high reliable, lw-cst and single-stage structure fr buck bst pwer cnversin. Cnventinally, three phase, six switch inverters have been widely emplyed fr variable speed inductin mtr drives. These cnventinal inverters have few de merits, that are the lsses f the six switches, the cmplexity f the cntrl algrithms and gate drive circuits t prvide six PWM lgic signals. Sme effrts have been made n the applicatin f fur switch, three phase inverter fr uninterruptible pwer supply and variable speed drives recently. Few merits f the fur switch three phase inverter ver the traditinal six switch three phase inverter such as, lwer cst due switch reductin, minimized switching lsses, fewer gate drive circuits t supply lgic signals fr the switches, easiest cntrl algrithms t prduce PWM signals, very less chances f damaging the switches due t lesser interactin amng switches. The fur switch three phase inverter with mdified Z-surce shwn in Fig.1, that emplys the mdified impedance netwrk t replace the cnventinal dc link. The fur switch three phase inverter with mdified Z- surce beneficially uses the sht-thrugh states t increase the dc bus vltage by gating n bth the switches f a same leg. Currently, there are tw existing inverter tplgies used fr adjustable speed drives; The cnventinal three phase PWM inverter and three phase PWM inverter with a dc-dc bst Cnverter. The cnventinal PWM inverter tplgy prduces high stresses t the switching devices and mtr and the cnstant pwer speed rati f the mtr can be limited. The dc t dc bsted utput with PWM inverter tplgy can gradually reduce the stresses and limitatins, thugh the stresses are alleviated, it suffers frm the prblems such as high cst and mre cmplexity included with the tw-stage pwer cnversin. The newly prpsed fur switch three phase mdified Z-Surce Inverter fed IM drive has the great feature that it can bst up the utput vltage by applying sht thrugh state, which was nt emplyed in traditinal vltage surce inverters. This great featured fur switch three phase mdified Z- surce inverter prvides a cheaper, simpler, single stage apprach fr applicatins f inductin mtr drives systems. 98

3 Fig.1fur switch three phase inverter with mdified z surce Inverter II. MODELING OF THE DRIVE SYSTEM A. Fur switch three phase inverter mdel The full drive system mdeling has the mdeling f the inverter and mdified Z surce inverter that are discussed in belw The main pwer circuit f the fur switch three phase inverter fed inductin mtr drive is shwn in Fig.. fur switches q 1, q, q 3 and q 4 and DC link capacitrs C 1 and C are emplyed in this circuit. The three phase AC supply is rectified by the cnverter switches. The rectified utput cnnected t the mdified z surce. The mdified z surce is cnnected with the pwer circuit. Phase a and b are taken frm legs, which have the switches. Phase c is cnnected in the midpint f the tw dc link capacitrs. Fur switches r dides are generated the line t line vltages, V 13 and V 3 whereas V 1 is generated accrding t Kirchhff s vltage law frm a split-capacitr bank in the dc-link. The cnductin states f the pwer switches are included with binary variables frm q 1 t q 4. Therefre, a binary value 1 indicates a switch is n, while indicates the switch is in ff. The cmplementary pairs are q 1 q 3 and q q 4 and, as a cnsequence, q 3 = (1-q 1 ) and q 4 = (1-q ). The assumed stiff vltage available acrss the tw dc-link capacitrs, are V c1 = V c = V dc, where V dc crrespnds t a stiff dc-link vltage. The ple vltages V 1, V, V 3 are depending n the switching states f the pwer switches in the inverter. They can be expressed in terms f the binary variables q 1 and q, and the dc-link vltage as fllws (, ), (, 1), (1, ), and (1, 1) are the fur switching states f the fur switch three phase inverter. Here the mtr lad is replaced by the resistive lad. In the case f the six switches cnverter, switching states (, ) and (1, 1) are represented as zer-vectrs, these zer vectrs cannt supply the dc-link vltage t the lad, s that current cannt flw thrugh the lad. In this fur switch three phase inverter, any ne phase f the mtr is always cnnected t the midpint f the dc-link capacitrs, s that current can flw thrugh the lad even at the zer-vectrs. During the switching states f (, 1) and (1,) the phase which is cnnected t the midpint f dc-link capacitrs is uncntrlled and the resultant current f the ther tw phases flw thrugh this phase. The capacitr vltages are equal when the lad is ideally symmetric. S that, during (, 1) and (1, ) vectr states current cannt flw. The large variatins f the vltage acrss the tw dc-link capacitrs caused by ne phase current circulating thrugh the capacitive bank, That will make the inverter utput current t get significant ripples, distrtins, and unbalances. The unequal lading f the split dc link capacitrs can be achieved by Tw f the inverter switching states (1, 1), (, ). This causes ne half f the link t discharge at a faster rate than the ther, resulting in the generatin f a vltage imbalance.. Fig.. Inverter Switching State (,) V 1 = V = v dc, when q 1 = q = ; V 1 = v dc, V =, when q 1 = 1, q = ; V 1 = q 1 v dc V = q v dc (.1) (.) V 1 = V = V dc, when q 1 = q = 1; V 1 =, V = V dc, when q 1 =, q = 1; V 3 = (.3) The phase t neutral vltage can be defined as fllws: V 1 = V 1 V n.4 99

4 V = V V n (.5) V 3 = V 3 V n (.6) Nrmally the inductin mtr lad phase vltages are balanced V an + V bn + V cn = V n = V dc 6 (q 1 + q ) (.7) The phase t neutral vltage can be derived as fllws Substituting Equatins (.7) and (.1) in (.4) V 1 = V 1 V n V 1 = V dc 6 4q 1 q 1 (.8) The same prcedure is fllwed t arrive at V and V 3 Fig. 3: Equivalent circuit f the impedance-surce inverter V = V dc 6 4q q 1 1 (.9) V 3 = V dc 6 q 1 q 1 (.1) TABLE 1 - Switching Functins and the Output Vltages frm Inverter: Switchin g Switch n Functin q T 1 = q1, T 3 = q, T 4 T q1 T T 4 1 T T 3 1 T 1 T T 1 T 3 Output Vltage Vectr V1 V V3 6 V dc V dc 6 6 V dc V dc C. Analysis Of The Z-Surce Netwrk In impedance netwrk, fur switch three phase inverter with inductin mtr lad, the dc vltage is fed t the Impedance netwrk cnsisting f fur equal inductrs (L1, L, L3, and L4) and tw equal capacitrs (C1, C). The netwrk inductrs are cnnected in series arms and capacitrs are cnnected in diagnal arms. The mdified Z netwrk bucks r bsts the input vltage depending upn the bsting factr. This netwrk als acts as a secnd rder filter.. The inverter main circuit cnsists f fur switches. Gating Signals are generated frm the Discntinuus Pulse Width Mdulatin. Assume the inductrs (L1, L, and L3andL4) and capacitrs (C1 and C) have the same inductance and capacitance values respectively. Frm the abve equivalent circuit: V C1 = V C = V C V L1 = V L = V L3 = V L4 = V L V L = V C V d = V c V i = The entries in Table1 relates t the utput vltage vectr crrespnding t each switching functin B. Mdified z surce mdel The mdified z surce inverter avid the prblems arised in the traditinal surce inverters. This z surce inverter emplys the switched inductr impedance netwrk cupled with inverter main circuit t the pwer surce. This inverter has unique features cmpared with traditinal vltage surce inverter and current surce inverters. The peak dc-link vltage acrss the inverter bridge is: V i = V C V 1 = V c V = T. V T 1 T = B. V Where: B = T T 1 T i.e., 1 B = A bst factr The utput peak phase vltage frm the inverter: V ac = M. V i Where, M is the mdulatin index. M 1-D where amplitude f referencewavefrm M = amplitude f carrier wavefrm 91

5 In this surce: V ac = M. B. V / In the traditinal surces: V ac = M. V Fr Z-Surce: V ac = M. B. V The utput vltage can be stepped up and dwn by chsing an apprpriate Buck-Bst factr (BB): BB = B.M (it varies frm t α) The capacitr vltage can be expressed as: V C1 = V C = V C = 1 T T. V /(1 T T ) The buck-bst factr BB is determined by the mdulatin index m and the bst factr B. The bst factr B can be cntrlled by duty cycle f the sht thrugh zer state ver the nn-sht thrugh states f the PWM inverter. The sht thrugh zer state des nt affect PWM cntrl f the inverter, because it equivalently prduces the same zer vltage t the lad terminal. The available sht thrugh perid is limited by the zer state perids that are determined by the mdulatin index. III. REQUIREMENT OF THE INDUCTORS AND CAPACITORS IN Z SOURCE NETWORK In the traditinal vltage surce inverter vltage ripples are suppressed, in the current surce inverter the current ripples are suppressed. The mdified Z-surce netwrk is a cmbinatin f fur inductrs and tw capacitrs. In this cmbined circuit, the Z-surce netwrk is the energy strage/filtering element fr the mdified Z- surce inverter. This mdified Z-surce netwrk prvides a secnd-rder filter and is mre effective t suppress vltage and current ripples than capacitr r inductr used alne in the traditinal inverters. Therefre, the smaller inductrs and capacitrs are required cmpare than the traditinal surce inverters. Detailed design guide and frmulae f the mdified Z-surce netwrk will be presented in a near future paper. When the fur inductrs (L1, L, L3 and L4) are small and near t zer, the Z-surce netwrk reduces t tw capacitrs (C1andC) in parallel and becmes a traditinal V-surce. Cnsidering additinal filtering and energy strage prvided by the inductrs, the mdified Z- surce netwrk shuld require less capacitance and smaller size cmpared with the traditinal vltage surce inverter. Similarly, when the tw capacitrs (C1 and C) are small and near t zer, the mdified Z-surce netwrk reduces t fur inductrs (L1, L, L3 and L4) in series and becmes a traditinal current surce. Cnsidering additinal filtering and energy strage by the capacitrs, the Z-surce netwrk shuld require less inductance and smaller size cmpared with the cnventinal current surce inverter. IV. RESULTS AND DISCUSSIONS In rder t verify the perfrmance f the inverter cnfiguratin and its cntrl strategy is develped by mat lab sftware. Inductin mtr current wavefrms and vltage wavefrms f the Fur Switch three phase mdified Z-Surce inverter are identical cnditins with traditinal six switch three phase inverter. It is evident that starting phase current is in the acceptable range. The steady state three phase current shwn in Fig. 5 indicates almst balanced cnditins f the fur switch three phase inverter which is als verified by six switch three phase inverter respnse. The effectiveness f the Z-Surce Inverters is prven by n versht, n undersht and zer steady-state errr f the speed respnse. It is fund that the perfrmance f the fur switch three phase inverter based drive is much clse t that f the traditinal 6 switches three phase inverter. The analysis and simulatin results shw that this inverter can dramatically reduce the cmplexity f the cntrl algrithms and cst. Vltage stress f the inverter is reduced. This stress reductin will prtect the inverter. S that this switched inductrs type fur switch three phase inverter reduced the switching stress and avid the ageing in the drive system. The utput vltage f the fur switch three phase with mdified z surce inverter is shwn fig.9. The three phase utput vltage and current wave frms are shwn in fig.5 and the speed curve f the inductin mtr is shwn in fig.6. Here the inductin mtr acts as a three phase lad. Fig 4 fur switch three phase mdified Z surce inverter vltage wave frm fig 5 utput vltage and current wavefrms 911

6 Fig 6 Fur switch three phase mdified z surce inverter speed respnse Frm the abve three figures (fig 4, fig 5, fig 6)the cncepts has been prven t design this switched inductr fur switch three phase inverter which will reduce the ttal cst f inverter inclusive f chpper peratin. The fllwing table will shw the perfrmance f the prpsed inverter. By grading the mdulatin index the utput vltage is ging t be cntrlled with bsted value. TABLE Perfrmance f Fur Switch Three Phase Inverter With Mdified Z surce. Mdulatin Index Input Vltage, In vlts Output Vltage, In vlts Fig.7. cmparisn between six switch (G1) and fur switch three phase inverter (G) In fig. 7 the tw inverter utputs are cmpared and it shws its perfrmance. Here the input vltage is cnstant (1v). The utput is varied with the mdulatin index V l t s V l t s Mdulatin index G G1 H H1 Sme the graph results are shwn belw, this graph results shwn the cmpared utput between tw inverters and the gain imprved. Grading and degrading will decide the cntrl technique. The fllwing results give the step up perfrmance. The variatins in capacitr and inductr having the step up and step dwn peratin. By reducing the inductr value t zer, we can perate this inverter as vltage surce inverter and als by degrading the capacitr value t zer; this inverter acts as current surce inverter Mdulatin index Fig.8. cmparisn between fur switch inverters with (H) and withut (H1) mdified Z surce In the abve fig.8 the perfrmance variatins in the tw inverters are shwn. H1-fur switch three phase inverter withut mdified Z surce H-fur switch three phase inverter with mdified Z surce Fr mdulatin index 1, the mdified z surce inverter utput vltage is greater than the fur switch inverter withut 91

7 mdified z surce. V l t s Fig.9. cmparisn between six switch inverter and mdified z surce inverter K1-six switch three phase inverter utput perfrmance curve K-fur switch three phase mdified z surce inverter utput perfrmance curve K K1 graph fur switch three phase inverter having the similar perfrmance f six switch three phase inverter. S that fur switch three phase inverter is efficient ne than the six switch inverter. In fig.8 fur switch three phase inverter with(h) and withut mdified z surce(h1) are cmpared and the results are shwn as graph. Frm this graph, fur switch three phase inverter with mdified z surce having the mre advantages than the withut mdified z surce inverter. The inputs fr the bth inverters are cnstant (1v). Frm this graph, the mdified fur switch inverter has been prven t have better quality t bst up the vltage withut the chpping circuit inclusive f fewer cmpnents. Present days the six switch three phase inverters are used, fr that fur switch three phase inverter mdified z surce (K) is cmpared with the six switch inverter withut z surce (K1) in fig.9. By emplying the mdified z surce the vltage can be bsted in high level because f the sht thrugh peratin. Here als the utput vltage can be cntrlled fr ur desired vltage value, by varying the mdulatin index and the bst factr. This bst factr is fully depends n the sht thrugh perid. Three inverters utput vltages are cmpared with the input vltage fr varius mdulatin indexes in fig.1. Frm these graph results this fur switch three phase inverter has prved itself as a better inverter than thers. V l t s Mdulatin index Output1 Input Output Output3 Fig.1. cmparisn f inverter utput with the cnstant input vltage Input- cnstant vltage (1v). Output1-fur switch three phase inverter with mdified z surce inverter. Output-six switch three phase inverter. Output3-fur switch three phase inverter withut mdified z surce. In fig. 7 the six switch three phase inverter(g1) and fur switch three phase inverter withut z surce(g) are cmpared, and perfrmance shwn as graph. Frm the fig 7 V. CONCLUSION This study has demnstrated that the cmpnent minimized mdified Z-surce inverter tplgy is a gd alternative technlgy t the traditinal inverter fr mre efficient, mre reliable and less cst cnversin systems. The perating principle and analysis have been given the current harmnics cntent simulatin results verified the peratinal and demnstrated the prmising features. In summary, the cmpnent minimized Z-surce inverter ASD system has several unique advantages that are very desirable fr many ASD applicatins:. It can prduce any desired utput ac vltage, even greater than the line vltage Prvides ride-thrugh during vltage sags withut any additinal circuits and energy strage Minimizes the mtr ratings t deliver a required pwer Reduces in-rush and harmnic current Unique drives features include buck-bst inversin by single pwer-cnversin stage, imprved reliability, strng EMI immunity and lw EMI. The Z-surce cnverter emplys unique impedance netwrk (r circuit) t cuple the inverter main circuit t the pwer surce, thus prviding unique features that cannt be bserved in the traditinal dc-ac cnverters. It can bst the input vltage withut chpper circuit, increase efficiency and reduce cst with minimized gate cmpnent cunt. The switching stress is reduced, which will make the cmpnent t get premature t failure. S the switches are prtected frm the switching stress. 913

8 References [1] F. Z. Peng, Z-Surce Inverter, IEEE Transactins n Industry Applicatins, Vl 39 N, March/April 3. Wuhan, China. [] Peng,F.Z., Miasen Shen and Zhaming Qian, 4. Maximum bst cntrl f the z-surce inverter. Prceeding f the IEEE PESC. [3] Justus Rabi, B. and R. Arumugam, 5. Harmnics study and cmparisn f z-surce inverter with traditinal inverters. Am. J. Applied Sci., : Drives Cnference Seattle, WA., pp: [4] Nasir Uddin, M., T.S. Radwan and M.A. Rahman, 4. Perfrmance analysis f fur switch 3-phase inverter fed IM drives. Prceeding f the 3rd IEEE Internatinal Cnference. [5] M. Shen, J.Wang, A. Jseph, F. Z. Peng, L. M. Tlbert, and D. J. Adams, Maximum cnstant bst cntrl f the Z- surce inverter,. Presented at the IEEE Industry Applicatins Sc. Annu. Meeting, 4. [6] Ph Chiang Lh, D. Mahinda Vilathgamuwa, Yue Sen Lai, Gek Tin Chua and Yunwei Li Pulse-Width Mdulatin f Z-Surce Inverters IEEE Transactin n Pwer Electrnics, Vl., N. 6, Nvember 5. [7] S. Thangaprakash, A. Krishnan. Z-surce Inverter Fed Inductin Mtr Drives a Space Vectr Pulse Width Mdulatin Based Apprach Jurnal f Applied Sciences Research, Vl 5, N. 5: , 9 [8]Bse BK. Adjustable Speed AC Drive Systems. New Yrk: IEEE Press; 198. [9] Van der Breck HW, Van Wyk JD. A cmparative Investigatin f a Three Phase Inductin Machine Drive with a Cmpnent minimized Vltage-fed Inverter under different Cntrl ptins. IEEE Transactins n Industrial Applicatins 1984;Vl, N : [1] Van Der Breck HW, Skudelny HC. analytical analysis f the harmnic Effects f a PWM AC drive. IEEE Transactins n Pwer Electrnics 1988; 3:16 3. [11] Blaabjerg F, Freyssn S, Hansen HH, Hansen S. Cmparisn f a Space Vectr Mdulatin Strategy fr a Three Phase standard and a cmpnent Minimized vltage surce Inverter. In: prceedings f EPE cnference; [1]The switched inductr cncept has been studied frm the generalized multicell switched inductr and switched capacitr z surce inverter, IEEE, ICSEE cnference prceedings. 914