Full-Bridge DC-DC Converter Using a ZVS-PWM Commutation Cell

Transcription

1 Full-Bridge D-D nverter Using a ZVS-PWM mmutatin ell DNIZAR RUZ MARTINS and FRNANDO. ASTALDO Department f lectrical ngineering Pwer lectrnics Institute Federal University f Santa atarina P. O. Bx Flrianóplis, S BRAZIL Abstract: - A Full-Bridge D-D cnverter using the ZVS-PWM cell t achieve sft switching cmmutatin is prpsed. xperimental results btained frm a labratry prttype rated 1500 W are als presented. It is demnstrated that the inclusin f the auxiliary switches des nt mdify the PWM switching pattern. Bench tests n the prttype cnfirm that the prpsed circuit exhibits high efficiency and behaves as a cnstant vltage surce ver an extended pwer utput range. Key-Wrds: slar energy, phtvltaic cell, static inverter. 1 Intrductin In the D-D cnverters the increase f the switching frequency has been used as a prcedure t imprve the pwer density f such cnverters. Hwever, many intrinsic characteristics f the available semicnductr devices limit, in practice, the switching frequency. The Phase-Shift Full-Bridge cnverter can be a gd chice in several applicatins [1]; their high lsses in switching, hwever, decrease the perating frequency, if n auxiliary cmmutatin prcess is used. The first attempt t crrect this situatin was the Full-Bridge ZVS-PWM cnverter [] as a gd chice t implement a high-frequency, high-pwer feed-vltage cnverter. The perating principle arises n a resnance prcess between the series inductr and the parasitic capacitances f the switches t achieve a ZVS cnditin f peratin. Althugh this cnverter presents a PWM cntrl characteristic, a duty cycle lss may ccur, due t the resnant inductr. In additin, auxiliary cmmutatin circuits must be emplyed, if a wide range f lad current is required [3], thereby increasing cnductin lsses. Other prblems may ccur: fr example, utput rectifier stresses are always present, due t the dide reverse recuperatin prcess cmbined with the leakage inductance f the pwer transfrmer. The use f auxiliary resnant elements fr prmting sft switching results in lsses in these cmpnents, due t the assciated current level. Pwer flw circulate s thrugh resnant inductrs [4]. On the ther hand, the use f these elements may cause vltage r current stress, s that saturable cmpnents must be emplyed t prevent vltage stress [5]. The emplyment f auxiliary circuits prmtes sft switching with reduced stress n the semicnductr devices, achieving higher switching frequency. Regardless f thse characteristics, the auxiliary cmmutatin circuits can als be applied in PWM cnverters withut mdificatin in the switching pattern, since the auxiliary circuits are made active nly during the switching intervals. Hwever, these circuits can induce sme lsses by cnductin and cmmutatin, if n ne specified strategy is used [6]. In this case, althugh mre devices are necessary t build a cnverter with sft switching, the pwer prcessed by the auxiliary switches is lw in cmparisn with the ttal prcessed pwer and the MI level is reduced, leading t a high interest in such techniques. An auxiliary cmmutatin circuit, using the ZVS- PWM mmutatin ell, was presented in [7]. An peratin strategy was elabrated t permit ZVS cmmutatin fr the main switches and ZS fr the

2 auxiliary nes. This cell des nt intrduce vltage r current stress n the cmpnents and imprves the ttal efficiency f the cnverter. New tplgies were generated fr applying this cell t cnverters [8]. The prpsed cnverter emplys the ZVS-PWM cmmutatin cell assciated with the classical Full- Bridge Phase-Shift PWM D-D nverter t achieve sft switching, imprving the verall efficiency and saving the duty cycle relatinship. Furthermre, the implementatin f a wide range lad peratin with lw stress ver the cmpnents wuld be a desirable characteristic. There are n cmpnents assciated with the auxiliary nes placed alng the lad pwer path, therefre the lsses are minimal. Principle f Operatin The prpsed circuitry is shwn in Fig. 1. As we can see, the auxiliary cmmutatin circuit is cnnected t each arm f the Full-Bridge cnve rter. Sme studies abut this cell have been presented in [7, 8]. The main characteristic arises frm the fact that the auxiliary cmmutatin cell will aid the cmmutatin prcess f the switches by delivering pwer, that wuld be lst, cming back t the surce, imprving the efficiency f the cnverter. Due t the fact that these auxiliary circuits act nly during the switching intervals f the Full-Bridge cnverter, they d nt affect the PWM characteristic cntrl f the cnverter. The prpsed circuit als implements the sft switching fr bth main and auxiliary switches fr a whle lad cnditin peratin, as well as serving as a vltage surce ver a extended lad range. On the ther hand, the majr prblem that ccurs in such cnverters - the reverse recvery f the rectifier dides cmbined with the leakage inductance f the pwer transfrmer - are als present, even thugh a cmmutatin cell is used. The main switches are S1, S, S3 and S4. The sft switching technique makes use f the resnance between the intrinsic capacitance f tw semicnductr switches and an inductr in the cmmutatin cell. In this way, tw ZVS-PWM cells are used: the first cell, cmpsed f the auxiliary switches Sa1 and Sa4 with the inductr lre, and the secnd ne, f Sa and Sa3 with the inductr lrd. ach cell has als ne auttransfrmer (Ae and Ad n Fig. 1), with the same winding rati Ns/Np, dented by a. The main switches perate as dual thyristrs, which means that a cmmutatin prcess nly ccurs if a ZVS cnditin is reached, while the auxiliary switches perate at ZS cnditin. The prcessed pwer is delivered t the lad by the pwer transfrmer TL and tw dides Dr1 and Dr. In Fig. 1, the lad is represented by a current surce I. The pwer prcessed by the auxiliary circuitry is reduced, because it acts nly during the switching interval. The pwer transfrmer is represented, including its leakage inductance Ld. All the references t current directins and vltage plarity are defined as shwn in Fig. 1. The cmmand signals are generated, as shwn in Fig. 6. In the prpsed cnverter the pwer is transferred t the lad by the displacement between the drives f the switches placed diagnally, in this way btaining an equivalent PWM signal. The tw arms f the cnverter wrk under different perating cnditins. Fr the drive sequence shwn in Fig. 6, the cmmutatin f the main switches n the left arm always ccur when the cnverter advances frm the pwer transfer stage t the free-wheeling stage. This cmmutatin prcess is aided by the lad current. The pwer transfer stage will be called the active stage, and the free-wheeling state the passive stage. The cmmutatin f the switches n the right arm is achieved when the cnverter advances frm the passive t the active stage. During this cmmutatin, the lad current flws thrugh the rectifier dides Dr1 and Dr, which means that there is n lad current fr cmplementing the cmmutatin prcess. As a cnsequence, under such cnditin the auxiliary circuit shuld prvide the energy required fr the cmmutatin prcess. Fr that reasn, this cmmutatin prcess will be called a critical cmmutatin. Under these cnditins, there must be a strage energy prcess in the cell assciated with the right arm, s that the cmmutatin prcess can be reached. The increased current in the lrd inductance will prvide the necessary energy strage. This current is called ib (bsted current), and increases linearly due t the delay in firing signals f auxiliary switches Sa and Sa3. This delay time must be previusly prgrammed if a wide lad range is required. As a cnsequence, a fixed ib will be reached by the lrd ahead f the cmmutatin prcess. If this value is nt adequate, the ZVS cnditin is nt evaluated, therefre as we are using dual thyristr, the prpsed cnverter will nt wrk prperly. It shuld be said that an adequate value f ib must be chsen, if perating frm zer at full-lad cnditin is required. As the lad current aids the left arm switches t prmte their cmmutatin, the presence f the cell means that the

3 cnverter may perate at full range lad, i.e. frm n lad t full lad, withut lsing any f its characteristics, such as PWM cntrl and sftswitching. Da1 Sa1 S1 S i(s1) v(s) Sa Da i(tl) Ae lre Ld v(tl) lrd Ad Np Ns Ns * * i(ld) N1 * i(lr) Np i(lr) TL * * i(sa4) * * N i(sa3) v(sa4) v(s4) Da4 Sa4 S4 I S3 Sa3 Da3 Dr1 v(i) Dr Fig. 1 Prpsed circuit. 3 Mathematical Analysis Fr the analysis f the peratin stages f the cnverter, the fllwing initial cnsideratins will be pstulated: -The switches have a bidirectinal characteristic n the current, with null cnductin resistance and null cmmutatin delays; -The utput filter will be represented by a current surce reflected int the primary side f the transfrmer; -The pwer transfrmer has a winding rati f N/N1 and a leakage inductance dented by Ld; -The auttransfrmers have a null magnetizing inductance and act as vltage surces with plarity alternatin. Bth auttransfrmers have the same winding rati f a=ns/np; -The drive pulses f the auxiliary switches are synchrnized with the drive pulses f the main switches. The analysis will be carried ut fr a half cycle f the peratin prcedure. Fr practical purpses, bth resnant inductrs lre and lrd are the same value and equal t lr. The cmmutatin cell is cnsidered, fr the sake f analysis, as an equivalent circuit with an equivalent inductr lr and a capacitr. The parameters n (1) and () are assciated with such equivalent circuit. Z0 = w0 = lr 1 lr (1) () In this equivalent circuit, the currents and vltages can be nrmalized with the general expressins f (3) and (4): i v i Z = 0 (3) v = (4) The lad current can be reflected int the primary circuit with (5): N I I 0 0 N1 = (5) 3.1 Operatin Stages Fig. 6 shws the intervals f time and the main wavefrms fr a half cycle functining f the cnverter. t: At the start f the analysis, the cnverter is suppsed t be in the passive stage, where n pwer is transferred t the lad. The switches S1 and S are n. Idem fr Dr1 and Dr. t t t1: The switch Sa3 is gated n at t. There must be a delay time befre firing S3 s that the value ib can be reached. The current thrugh the inductr lrd rises linearly frm zer t ib. The dide Da is n, in view f the induced plarity n the auttransfrmer Ad. An induced vltage f value (a.) is placed against the flw path f this current. An equivalent circuit fr this stage can be drawn, see Fig.. q. (6) determines the time interval f this stage. lrd i(lr) a. Fig. quivalent circuit fr interval t t t1. ib. lr t1 t 0 = ( 1 a) (6) t1 t t: In t1 the switch S is gated ff. Simultaneusly, S3 is gated n and therefre, since it perates as a dual thyristr, a cmmutatin prcess must ccur befre S3 is effectively gated n. The TL pwer transfrmer remains shrt-circuited by the rectifier dides. The charge n the assciated capacitance f S increases, while the charge n the

4 assciated capacitance f S3 decreases. At the beginning f this stage, the I lad current stred n Ld helps the cmmutatin prcess, until an inversin n the current thrugh Ld ccurs. Frm the circuit fr this stage, an equivalent circuit can be generated (Fig. 3), where the main equatins are (7) and (8). v ( t) = v ( cs w t) + Z ( I + ib) sinw. t (7) th Z [ilr( t) ild ( t ) ] = Z (I + ib)csw.t + v.sinw.t (8) 0 th 0 The fllwing parameters f the equivalent circuit can be defined: v S1 I' S4 0 ild(t) Ld lr vc(t) ilr(t) ib a. Fig. 3 quivalent circuit fr interval t1 t t. th = ( a) Ld lr + Ld lr Ld Leq = lr + Ld 1 (9). (10) Leq Z =. (11) w = 0 1. L. eq (1) This stage will end when the transfrmer current ild(t) reaches the lad current I in ppsite directin. This will happen at t. The time interval fr this stage can be calculated subsequently by (13), where a can be btained frm (14). α t t1 = w. I. w0. Ld = vth( sin ) + Z ( I + ib)( 1 cs ) (13) α α α (14) In t, the vltage acrss the capacitr 3 and the current n inductr lrd can be calculated with (15) and (16). vth ilr I I ib Z sin = +( + )csα + α (15) vc = v ( cs ) + Z ( I + ib) sin th 1 α α (16) quatins (15) and (16) can be nrmalized, resulting in (17) and (18). These values will be required t evaluate the calculatins in the next stage. ilr Z ilr =. 0 (17) vc vc = 0 (18) t t t3: The current thrugh Ld is clamped at the value f the lad current reflected int the primary circuit. As a cnsequence, at the end f this interval the switch S3 shws a zer-vltage cmmutatin, if there are cnditins fr such. At this stage, we can say that the prpsed cnverter will perate adequately fr the ib that was chsen. If an inadequate perating cnditin is reached, the ib value must be increased. An equivalent circuit is shwn in Fig. 4. The main equatins f this stage are (19) and (0). ilr( t) = I + ( ilr I )cs w t + ( a vc ) sinw t 1 (19) vc( t) = a ( a vc ).cs w t + ( ilr I ) sinw t (0) (1-a) ilr ilr(t) vc vc(t) I'. Fig. 4 quivalent circuit fr interval t t t3. Frm (19) and (0), (1) can be btained, shwing the cnditin fr the zer-vltage cmmutatin fr any lad current. If this inequality is nt balanced, the cmmutatin cell will nt perate. Therefre, (1) means that if there is nt a suitable value fr ib, under all lad cnditins, the cnverter can nt perate adequately. As we can see frm Fig. 3, the lad current reflected int the primary, affects the cmmutatin prcess. In a practical cnverter, the current ib must be preset at a cnvenient value, i.e., ne that wuld carry thrugh sft switching fr an

5 verall lad range. It is imprtant t say that the adequate value fr ib depends n the lad current. High values fr ib decrease the cmmutatin time, althugh they increase the cnductin lsses. At this pint, a cmprmise shuld be made, between efficiency and secure peratin under all lad cnditins. A gd strategy wuld be t hld a lad current, s that a preset ib value can be emplyed, imprving the efficiency f the cnverter. In a practical cnverter, this value can be adjusted by a delay time circuitry. As a suggestin fr future imprvements, digital techniques might be used, s as t raise efficiency thrugh dynamic cntrl. ilr I > a 1+ ( 1 a). vc vc (1) The time interval can be calculated by () and indicates the ZVS cmmutatin is reached. w.( t3 t) = π tan () ild I' tan 1 a vc 1 1 ' ( ild I ) + ( 1 a vc ) a t3 t t4: At time t3, the cmmutatin prcess between S and S3 is cncluded. S3 as a dual thyristr is ready t gate n, s that the cnverter mves frm its passive state t the active ne, while cnducting S1 and S3. The resnant inductr lrd is demagnetized thrugh the auttransfrmer, delivering the stred energy back t the primary surce. Once the inductr lrd is cmpletely demagnetized, the switch Sa3 can be pened under zer current. In practice, Sa3 can be pened after t4, when a ZS cmmutatin fr the auxiliary switches is reached. The time interval f this stage can be calculated with (3). While the resnant inductr current is higher than the reflected lad current, the intrinsic dide f the auxiliary switch is n. a (4) (5) D = t 5 t 4 =. fs.( t5 t4 ) Ts/ a. lre ilr(t) vc(t) I' Fig.5 quivalent circuit fr interval t5 t t6. V = D.. N N1 t5 t t6: At this stage the cnverter is advanced frm the active t the passive state. T reach this stage, the switch S1 is gated ff, S4 in dual thyristr mde is gated n, while Sa4 is gated n t activate the cmmutatin cell. The dide Da1 ges int the cnductin mde. The snubber capacitr assciated with S1 will keep the vltage lw, decreasing the lsses during the cmmutatin. As a result, the cmmutatin prcess is perfrmed under cnstant lad current. At t6, the switch S4 cmmutates under zer vltage. As we can see, the cmmutatin prc ess is aided by lad current, and the shrter the interval time, the higher the lad current. The prpsed cnverter can perate withut lad, which means that the left cell must be cupled t it. An equivalent circuit fr this stage (see Fig. 5) leads t the fllwing equatins: ilr( t) = ( 1 a) sinw t I ( 1 cs w t) vc( t) = ( a)( cs w t) + I sinw t 0 0 (6) (7) The time interval fr this stage is calculated with (8). w.( t t ) = I + ( ild0 I ) + ( 1 a vc0) a a (3) I a I a a w t t ( 1 ) 0.( 6 5) = cs I + ( 1 a) (8) t4 t t5: During this stage the energy is transferred t the lad. The switches S1 and S3 cnduct the lad current. The duty cycle is given by (4) and the average lad vltage is calculated by (5). t6 t t7: At the end f the cmmutatin prcess, the lad begins a free-wheeling state, while the resnant inductr lre is demagnetized thrugh the auttransfrmer. When the inductr lre is cmpletely demagnetized, the switch Sa4 can be gated ff under

6 zer-current cnditin. The time interval fr the freewheeling stage is calculated by (9). 1 a w t t a sin 1 I 1 a I a( 1 a) I I 1 a I a( 1 a) 0.( 7 6) = cs + + ( 1 ) I a a + ( 1 ) I + ( 1 a) (9) t7 t t8: The cnverter is in the free-wheeling state, the switches S3 and S4 are n, and n pwer is transferred t the lad. A nn-demagnetized current, caused by the leakage inductance f the pwer transfrmer, remains flwing in the path frmed by S3 and S4. The time interval fr that stage is calculated with (30). As a result f the additinal ib current, the main switches f the cnverter are subjected t additinal current stresses. Thse stresses, n the right arm switches, can be calculated with (31). (30) (31) 1 D t7 t8 = f s iadd rms = ib..( 1 t0) fs t 3 Ae, Ad: Np/Ns = 30/10 n ferrite cre -30/14 (Thrntn) Bench tests with the prttype demnstrate that the switches can perate at high frequency with sft cmmutatin ver an extended lad range, frm nlad t full lad cnditin. The experimental wavefrms shwn here were evaluated fr nminal lad. The current and vltage n the main switches f the right arm are shwn in Fig. 7. An additinal current is bserved in the current signal due t the cmmutatin cell actin. In Fig. 8, a detailed view f the same signals is presented, shwing zer vltage switching. Fig. 9 shws the cmmutatin under zer-current n the auxiliary switches f the right arm. We are using an ib value that assures the adequate peratin fr full lad cnditin. During the whle bench testing time, all the switching was ZVS fr main switches and ZS fr auxiliary nes. The use f Msfets fr the auxiliary switches Sa1-Sa4, may increase a little the pwer lsses, because the intrinsic utput capacitance f them is quickly discharged internally when they turn n. The prttype efficiency is shwn in Fig. 10. The maximum measured efficiency was 93%, at full lad cnditin. 4 xperimental Results A prttype rated 1500 W was built t evaluate the prpsed circuit. The main specificatins are: - D input vltage: 300 V - D utput vltage: 60 V - D utput current at full lad: 5 A - Switching frequency: 75 khz - Auttransfrmer vltage rati: 3:1 - fficiency: abut Pwer Transfrmer vltage rati N1/N: 16/4 - Transfrmer Leakage Inductance:.3 µh - apacitance f the Switches: 3.5 nf The pwer circuit dia gram f the cnverter, shwn in Fig. 1, cnsists f the fllwing parameters: S1-S4: APT 400 (Advanced Pwer Technlgy) Sa1-Sa4: IRF 740 (Internatinal Rectifier) Da1-Da4: MUR 440 (Mtrla) Dr1,Dr: MUR 1530 (Mtrla) lre: 10µH, 8 turns n ferrite cre -30/7 (Thrntn) lrd: 10µH, 15 turns n ferrite cre -30/7 (Thrntn) TL: Np/Ns = 16/4 n ferrite cre -65/39 (Thrntn)

7 Vc(S1) Vc(S3) Vc(S) Vc(S4) i(tl) i(ld) V(S3) Vc(Sa1) i(lrd) i(sa3) i(da) I.Ns/Np Vc(Sa3) Vc(Sa) Vc(Sa4) i(da3) i(sa) i(lrd) -I.Ns/Np The peratin f the auxiliary cmmutatin cells des nt induce stress vltage acrss the switches f the main and auxiliary circuitry; Althugh there are sme cnductin lsses impsed by cells, the efficiency f the cnverter was very high at full lad cnditin; The cmmutatin prcess can be emplyed with any f the knwn pwer switch technlgies, such as IGBTs, GTOs and BJTs. As a result f such characteristics, it can be cncluded that the prpsed cnverter is especially suitable fr high pwer applicatins. (ib+i.ns/np) i(s) I.Ns/Np i(s3) i(s) i(s3) V(S4) i(lre) i(sa1) i(da4) i(lre) i(sa4) i(da1) v(s) i(s) I.Ns/Np i(s1) i(s1) i(s4) i(s4) i(s1) i(s4) V(TL) -.Ns/Np V(I) t t1 t t3 t4 t5 t6 t7 t8 Fig. 6. Main Wavefrms f the nverter. Fig. 7 Zer-vltage switching n S. Scales: Vltage = 100 V/div; urrent = 5 A/div; Time = µs/div i(s) v(s) 5 nclusin The ZVS-PWM cmmutatin cell was applied t a Full-Bridge PWM D-D nverter. valuatin f a prttype based n the new circuit shwed that the prpsed circuit has sme utstanding characteristics: The cmmutatin lsses are minimum, because the main switches perate under zer-vltage cnditin, and the auxiliary switches at zer-current cnditin; The rms current thrugh the auxiliary switches is present nly fr a shrt interval during the cmmutatin cycle; as a result, the cnductin lsses n thse switches and n the assciated devices are kept at a lw value; The ZVS and ZS characteristics f the switches are present in all lad cnditins f the cnverter; Fig. 8 Detail f the turn-ff f S. Scales: Vltage = 50 V/div; urrent = A/div; Time = µs/div

8 i(sa) v(sa) Fig. 9 Zer-current switching n Sa. Scales: Vltage = 100 V/div; urrent = 1 A/div; Time = µs/div [6] J.G. h, J.L. Sabaté, and F. Lee, Nvel Full- Bridge Zer Vltage Transitin PWM D-D nverter fr High Pwer Applicatins, Prceeding f the I AP, 1994, pp [7] I. Barbi and D.. Martins, A True PWM Zer- Vltage Switching Ple With Very Lw Additinal RMS urrent Stress, Prceeding f the PS 91, 1991, pp [8] D.. Martins, F. M. Seixas, J. A. Brilhante and I. Barbi, A Family Of D-D PWM nverters Using A New ZVS mmutatin ell, Prceeding f the PS 93, 1993, pp fficiency % I Fig. 10 Prttype efficiency. References [1] Unitrde, Switching Regulated Pwer Supply Design Seminar Manual, [] J.A.Sabaté, V. Vlatkvic, R.D. Ridley, F.. Lee, and B.H. h, Design nsideratins fr High- Vltage High-Pwer Full-Bridge Zer Vltage Switched PWM nverters, Prceeding f the I AP, 1990, pp [3] J.L. Freitas, G. Gabiatti, and I. Barbi, On the Design and xperimentatin f a High Perfrmance 5A/48V Rectifier Unit, Prceeding f I INTL 9, 199, pp [4] P.D. Mschpuls, G. Zigas, and Js; A Fixed Frequency ZVS High Pwer PWM SMR nverter With Zer T Rated Lad Variatin apability, Prceeding f the INTL, 199, pp [5] J.G. h, J.L. Sabaté, G. Hua, and F.. Lee, Zer Vltage and Zer urrent Switching Full-Bridge PWM nverter fr High Pwer Applicatins, Prceeding f the I PS, pp 1994,