DESIGN CONSIDERATIONS AND PERFORMANCE EVALUATION OF A 3-kW, SOFT-SWITCHED BOOST CONVERTER WITH ACTIVE SNUBBER

Transcription

1 EIGN ONIERATION AN PERFORMANE EALUATION OF A 3kW, OFTWITHE BOOT ONERTER WITH ATIE NUBBER Yungtaek Jang and Milan M. Jvanvić ELTA Prducts rpratin Pwer Electrnics Labratry P.O. Bx 1173, 5101 avis rive Research Triangle Park, N 7709, UA hauhun Wen ELTA Electrnics Inc. 3, Tung Yuan Rad, hungli, Taiwan, R.O.. Abstract The paper prvides a cmplete design prcedure f a highpwerfactr (HPF) bst cnverter which emplys an active snubber t reduce reverserecvery related lsses f the bst rectifier and achieve zervltage switching (Z) f the bst switch. The lsses are reduced by inserting an inductr in the series path f the bst rectifier t reduce the di/dt rate during its turnff. Extensive experimental evaluatins f the perfrmance f a 3kW prttype fr telecmmunicatin applicatins perating frm a 0 rms ± 0% input are presented. The evaluatin results demnstrate that the HPF bst cnverter can perate at 100 khz switching frequency with an efficiency in the 9497% range at full pwer. 1. Intrductin A cntinuuscnductinmde (M) bst cnverter is the preferred tplgy fr implementing the frntend cnverter with active inputcurrent shaping t the mst telecmmunicatin pwer supplies. Hwever, since the dcutput vltage f the bst cnverter must be higher than the peak input vltage, the utput vltage f the bst inputcurrent shaper is relatively high. ue t the high utput vltage, the cnverter requires the use f a highvltage, fastrecvery bst rectifier. At high switching frequencies, fastrecvery rectifiers prduce significant reverserecveryrelated lsses when switched under hard switching cnditins [1]. These lsses can be significantly reduced and, therefre, a high efficiency can be maintained even at high switching frequencies by emplying a sftswitching technique [][8]. Recently, a new sftswitched bst cnverter and its variatins have been prpsed in [7]. The prpsed scheme emplys an auxiliary active switch with a snubber inductr and a capacitr t frm an active snubber that is used t cntrl the di/dt rate f the bst rectifier current and t create cnditins fr zervltage switching (Z) f the bst switch and the auxiliary active switch. This technique reduces the reverserecveryrelated lsses by cntrlling the di/dt rate f the rectifier current with a snubber inductr which is cnnected in series with the path f the bst switch and rectifier. In additin, the energy stred in this inductr is used t discharge the utput capacitance f the bst switch t zer prir t the switch turnn, thus its capacitive turnn switching lss is eliminated. The series cnnectin f the auxiliary switch and the clamp capacitr, which is used t prvide the discharging path f the snubber inductr current when the main switch is turned ff, is cnnected t the utput capacitr. In this paper, a cmplete design prcedure f this sftswitched bst cnverter fr telecmmunicatin applicatins and extensive experimental evaluatins f its perfrmance are presented. The evaluatin was perfrmed n a 3kW prttype perating frm a 0 rms ± 0%, singlephase input vltage. The evaluatin results shw that the input current shaping using the sftswitched bst cnverter can be perfrmed with less than 5% TH at full utput pwer and the nminal input vltage. In additin, experimental results demnstrate that current harmnics f the input current satisfy the IE10003 standard ver the entire input vltage and utput pwer ranges. The experimental HPF bst cnverter perates with an efficiency range f 9497% at full pwer and 100 khz switching frequency.. Review f ftwitched Bst nverter with Active nubber [7] The circuit diagram f the bst cnverter which emplys the active snubber fr reverserecverylss reductin is in Fig. 1 L L 1 F Bst pwer stage with active snubber. I O O R L

2 I in i L L i 1 i 1 O ss (a) [T 0,T 1] (b) [T 1,T 3] Fig. implified circuit diagram f the prpsed bst pwer stage shwing reference directins f currents and vltages. (c) [T,T ] 3 4 (d) [T,T ] 4 5 ss shwn in Fig. 1. The circuit in Fig. 1 uses a snubber inductr L, which is cnnected in series with the bst switch and rectifier, t cntrl the di/dt rate f the rectifier when bst switch is turned n. In additin, the series cnnectin f auxiliary switch 1, clamp capacitr is used t discharge the energy stred in the inductr t the utput after 1 is turned ff. ide is emplyed t eliminate the parasitic ringing between the junctin capacitance f rectifier and the snubber inductr by clamping the ande f t grund. Figs. and 3 shw the circuit diagram f the simplified cnverter and the tplgical stages f the circuit during a switching cycle, respectively. T simplify the analysis f peratin, it is assumed that the inductance f bst inductr L is large s that it can be represented by cnstantcurrent surce I in, and that the utputripple vltage is negligible s that the vltage acrss the utput filter capacitr can be represented by cnstantvltage surce O. The bst and auxiliary switches in Fig. 3 never cnduct simultaneusly. In fact, the prper peratin f the pwer stage, i.e., the peratin which reduces reverserecvery related lsses and enables sft switching, requires apprpriate dead times between the turnff f bst switch and turnn f auxiliary switch 1, and vice versa. Befre main switch is turned ff at t = T 0, the entire input current, I in, flws thrugh inductr L and switch. At the same time, rectifier is ff with a reverse vltage acrss its terminals equal t utput vltage O. Auxiliary switch 1 is als ff, blcking the vltage O, where is the vltage acrss clamp capacitr. After switch is turned ff at t = T 0, the current which was flwing thrugh the channel f the MOFET f switch is diverted t the utput capacitance f the switch, O, as shwn in Fig. 3(a). As a result, the vltage acrss switch starts t increase linearly due t the cnstant charging current I in. At the same time, vltage 1 acrss switch 1 decreases at the same rate. Because inductr current i L cntinues t charge O after v reaches O, cntinues t increase abve O, causing the current thrugh inductr L t start decreasing due t a negative vltage acrss its terminals. This tplgical stage ends at t = T 1, when vltage 1 reaches Fig. 3 (e) [T 5,T 6] (f) [T 6,T 7] (g) [T 7,T 8] (h) [T 8,T 9] Tplgical stages f the prpsed bst pwer stage. zer, i.e., when the antiparallel dide f switch 1 starts cnducting. At that mment, the remaining inductr current i L is diverted int clamp capacitr, as shwn in Fig. 3(b). uring the tplgical stage shwn in Fig. 3(b), inductr current i L cntinues t decrease as the energy stred in L cntinues t be transferred int clamp capacitr. This tplgical stage ends at t = T 3, when i L reaches zer, and the antiparallel dide f auxiliary switch 1 stps cnducting. T achieve Z f 1, it is necessary t turn n the transistr f switch 1 while its antiparallel dide is cnducting. If the transistr f switch 1 is turned n prir t t = T 3, inductr current i L will cntinue t flw after t = T 3 in the ppsite directin thrugh the clsed transistr f switch 1, as shwn in Fig. 3(c). uring this tplgical stage, the energy stred in clamp capacitr during interval [T 1 T 3 ] is returned t the inductr in the ppsite directin. This interval ends at t = T 4 when auxiliary switch 1 is turned ff. When, at t = T 4, 1 is turned ff, i L is frced t flw thrugh utput capacitance O f bst switch, as shwn in Fig. 3(d). ince in this tplgical stage i L discharges O, bstswitch vltage decreases twards zer. As a result, the antiparallel dide f will start cnducting as shwn in Fig. 3(e). T achieve Z f switch, it is

3 necessary t turn n the transistr f switch during the time interval [T 5 T 6 ], when the antiparallel dide f is cnducting. If the transistr f is turned n during this interval, i L will cntinue t increase linearly after t = T 6, as shwn in Fig. 3(f). At the same time, rectifier current i will cntinue t decrease linearly. The rate f the i decrease is determined by the value f L inductance because di dt O =. (1) L T reduce the rectifierrecvered charge and the assciated lsses, a prper L inductance needs t be selected. Generally, a larger inductance, which gives a lwer di /dt rate, results in a mre efficient reductin f the reverserecveryassciated lsses [1]. The linear increase f i L shuld stp at t = T 7, when i L reaches the inputcurrent level I in, and rectifier current i falls t zer. Hwever, due t the residual stred charge, rectifier current i starts flwing in the reverse directin, as shwn in Fig. 3(g), prducing an versht f the switch current ver the I in level. Withut L, this reverserecvery current wuld be many times larger. Once the rectifier has recvered at t = T 8, the entire input current I in flws thrugh switch (Fig. 3(h)), until the next switching cycle is initiated at t = T 9. Besides the stred charge that needs t be recvered befre fastrecvery rectifier can blck vltage, the rectifier pssesses a junctin capacitance. In a practical bst circuit, this capacitance interacts with the snubber inductance causing an undesirable parasitic ringing f the rectifier vltage after the rectifier has recvered. As explained in [7] and [8], the ringing can be cmpletely eliminated by the additin f dide, shwn in Fig. 1. ling Frce nvectin 3. esign f Active nubber ircuit Figure 4 shws typical stred charge f a fastrecvery rectifier vs. the rate f rectifiercurrent change di /dt. T reduce the reverserecveryrelated lsses, the di /dt rate f the majrity f fastrecvery rectifiers shuld be kept belw apprximately 100 A/µs [1]. Generally, slwer rectifiers require slwer di /dt rates than faster rectifiers t achieve the same level f reductin f the reverserecveryrelated lsses. As a rule f thumb, the practical range f snubber inductance L is frm t µh t 0 µh. As can be seen frm Fig. 4, stred charge Q rr f a fastrecvery rectifier at 15 A and with di /dt = 1000 A/µs is apprximately 500 n which is fur times greater than the stred charge with di /dt = 100 A/µs. In fact, withut a snubber, the rate f rectifiercurrent change is mainly decided by parasitic inductance L P f the trace between bst switch and rectifier, which is generally less than several hundreds nan henry. As a result, the rate f rectifiercurrent change f the bst rectifier withut a snubber inductr is apprximately 000 A/µs ( O /L P = 400/ ). T reduce the stred charge which is directly prprtinal t reverserecveryrelated lsses, snubber inductr L must be added. Generally, the maximum value f snubber inductance L is limited by the vltage stress n switch and auxiliary switch Qrr [n] esign f a 3kW, HPF Bst Rectifier 3.1 pecificatins The 3kW, HPF bst experimental rectifier was designed fr the fllwing specificatins i = 15 A i = 30 A Input ltage in : 1phase, 0 (LL,rms) ± 0% Line Frequency f L : Hz TH: < 5% Pwer Factr: > 0.99 (100% lad) Output ltage 0 : 400 dc ± % (0 100% lad) Pwer P 0 : 3 kw Ripple ltage:< 6.5 peakpeak (300/360 Hz) witch Frequency f : 100 khz Fig. 4 i = 5 A ,000 di /dt [A/us] Typical stred charge f a fastrecvery rectifier vs. di /dt at 15, where di /dt is the rate f rectifiercurrent change thrugh zer crssing [1].

4 1. As can be seen frm Fig., the vltage stress f switches and 1 are the same and equal t O. uring the perid when bst switch is n, auxiliary switch 1 blcks the vltage which is the summatin f the clamp capacitr vltage and the utput vltage. Bst switch blcks the same vltage when auxiliary switch 1 is n. mpared t the crrespnding stress in the cnventinal, hard switched bst cnverter, the vltage stress f bst switch in the prpsed cnverter is higher fr the amunt f clamp vltage. T keep the vltage stress f switches and 1 within reasnable limits, it is necessary t prperly select clampvltage level. lampcapacitr vltage, can be expressed as = LfI O O, () where f is the switching frequency. etailed derivatins and explanatins can be fund in [7]. Accrding t Eq. (), is the maximum at full lad I (max) and lw line in(min), since switching frequency f and utput vltage O are cnstant. Fr given input and utput specificatins, i.e., fr given I (max), in(min), f, and O, the vltage stresses n the main and auxiliary switches can be minimized by minimizing snubber inductr L. Frm the specificatins, the minimum input vltage in(min) = 176, the maximum utput current I O(max) = 7.5 A, switching frequency f = 100 khz, and utput vltage O = 400. T limit the maximum vltage stress f switches belw 85% f the vltage rating f a 500 switch, the maximum clampcapacitr vltage (max) shuld be less than 40. As a result, the value f snubber inductr L was chsen t be apprximately 5 µh. This value results in 80 A/µs di /dt rate. ince the average vltage acrss the clampcapacitr is independent frm the size f the clamp capacitr as shwn in Eq. (), the value f can be designed t minimize the switchfrequency vltage ripple. The energy stred in the snubber inductr cntributes t the vltage ripple during a switching cycle. The maximum switchfrequency vltage ripple (PP) can be expressed as in L = IO. (3) P ( P) (max) The chice f fur. µf ceramic capacitrs in parallel fr the clamp capacitr limits the magnitude f the maximum peaktpeak ripple vltage t apprximately 5. T achieve Z f main switch, it is necessary that the energy stred in L at the mment auxiliary switch 1 is turned ff be larger than r equal t the energy required t discharge utput capacitance O f switch frm O dwn t zer, i.e., if 1 1 LI O(max) O( O ), (4) then the switch vltage will reach zer. ince the energy stred in L is prprtinal t the square f the utput (lad) current, it is easier t satisfy the Z cnditin at heavier lads than at lighter lads. As a result, at light lads switch des nt perate with Z. On the ther hand, auxiliary switch 1 perates with Z in virtually the entire lad range, because it uses energy stred in bst inductr L, which is much larger than that stred in snubber inductr L, t discharge its utput capacitance. Fr L = 5 µh, the bst switch perates with zervltage switching dwn t 30% f the full lad at the minimum line. In inputcurrentshaping applicatins, the circuit in Fig. 1 needs an additinal rectifier t prevent the vltage acrss clamp capacitr frm becming negative. Namely, due t the varying line vltage and cnstant utput vltage, the duty cycle f the bstcnverter inputcurrent shaper varies. It is clse t 100% arund the zer crssings f the line vltage, and it is smallest at the peak f the line vltage. When the line vltage is arund zer, the energy stred in the bst inductr is small even with the switch duty cycle clse t 100%. As a result, after switch is turned ff, the inductr stred energy is nt sufficient t charge utput capacitance O f up t O, and frce the cnductin f the antiparallel dide f auxiliary switch 1. ince arund zer crssings f the line vltage antiparallel dide f 1 des nt cnduct, cnsequently, capacitr des nt charge t the psitive directin. Hwever, clamp capacitr may be reversely charged fr a brief duratin f switch 1 cnductin near zer crssing. If becmes negative, n reset vltage fr the cre f the snubber inductr will be available, and the cre wuld saturate. T prevent frm becming negative, clamp dide 1 (typically the chttky type) shuld be added t the active clamp as shwn in Fig mpnent emicnductrs The peak vltage stress n switch is apprximately 440 as shwn in ectin 3.. The peak current stress n, which is equal t the peak input current is apprximately 5.7 A at full lad and lw line. An IXFN 48N50 MOFET frm IXY ( E = 500, I 5 = 48 A, R = 0.1 Ω) was used fr bst switch. T use a cmmn heatsink fr bst switch, active snubber switch 1, and utput dide, devices f the similar package were selected. ince the peak vltage stress n snubber switch 1 is equal t the bst switch, An IXFN 44N50 MOFET frm IXY ( E = 500, I 5 = 44 A, R = 0.1 Ω) was used fr 1.

5 ince, utput dide must blck the utput vltage f 400 and must cnduct a peak lad current f 7.5 A, a EI x6106 dide frm IXY ( RRM = 600, I FAM = 60 A, t rr = 35 ns) was used fr utput dide. T reduce the cnductin lss f the utput dide, a device which has higher current rating than the designed maximum current was selected. The vltage stress f clamp dide is the same as utput vltage O. Hwever, since the circulating current thrugh L lp is small, the pwer dissipatin f clamp dide is negligible [7]. Threrfre, a RHRP860 dide frm Harris ( RRM = 600, I FAM = 8 A, t rr = 30 ns) was used fr. Fr 1 which carries nly transient current during inputvltage zer crssing and prevents the reverse vltage f clamp capacitr, a MBR10100 chttky dide frm Mtrla ( RRM = 100, I FAM = 10 A) was selected. Bst inductr ince the desired inductance f bst inductr L is 0.45 mh, bst inductr L was built using tw tridal cres attached in parallel (Magnetics, Klµ 77110A7) and 55 turns f magnet wire (AWG #13). Tw tridal cres are used in parallel t reduce the flux density and number f turns f the winding. nubber inductr The desired inductance f the snubber inductr is 5 µh t btain the desired di/dt and limit the clamp capacitr vltage. nubber inductr L was built using tw tridal cres attached in parallel (Magnetics, MPP 55550A) and 9 turns f magnet wire (AWG #13). apacitrs Fur. µf, 100, ceramic capacitrs in parallel are used fr the clamp capacitr t limit the magnitude f the maximum peaktpeak ripple vltage t apprximately 5. ince the peak clamping capacitr vltage is apprximately 40 fr this prttype, 100 ceramic capacitrs are utilized. 4. Experimental Results The perfrmance f the bst cnverter with the active snubber was evaluated n a 3 kw (400 / 7.5 A), linevltage ( ac ) pwerfactrcrrectin circuit perating at 100 khz. The cmpnent values f the experimental circuit are shwn in Fig. 5. The cntrl circuit was implemented with the averagecurrent PF cntrller U3854. The T440 driver is used t generate the required gatedrive signal fr the main switch. The T49 driver with an islatin transfrmer are used t generate the required gatedrive signal fr the auxiliary switch. With the selectin f L = 5 µh, the di/dt turnff rate f the rectifier was limited t di /dt = O /L = 80 A/µs. In additin, the maximum vltage f clamp capacitr, which ccurs at the minimum line vltage and full lad, was limited t apprximately 40. With (max) = 40, the maximum vltage stresses n the switches were limited t O (max) = 440. Figure 6 shws the gatedrives, mainswitch draintsurce, and bst rectifier vltage wavefrms f the experimental cnverter perating at the minimum line ( in min = 176 ac ) and full pwer f 3 kw. As can be seen frm Fig. 6(a), the vltage stress n the main switch is apprximately 430. Als, frm Fig. 6(b), which shws an enlarged turnn transitin f the wavefrms in Fig. 6(a), it can be seen that bst switch turns n when the vltage acrss it is zer. As a result f the zervltage switching f, its turnn utputcapacitance discharge lss is eliminated. Fr L = 5 µh, the experimental cnverter can perate with zervltage switching dwn t 30% f the full lad at the minimum line vltage. 176 ac 64 ac in BO508 EMI filter L 0.45 mh L RHRP860 5 uh IXFN48N50 MBR IXFN44N50 1 EIx6106 4x. uf /100 4x470 uf / dc R L O Fig. 5 Experimental 3 kw, bst pwer stage with activeclamp snubber.

6 G1 [0 /div] G [0 /div] I L [50 A/div] EFFIIENY [%] ac ( Ts = 44, Ts1 = 4, Td = 4 ) ( Ts = 68, Td = 57 ) ( Ts = 84, Ts1 = 69, Td = 53 ) [100 /div] ac G1 [0 /div] G [0 /div] I L [50 A/div] [100 /div] in = 176 ac P O = 3 kw f 100 kh (a) (b) zer vltage switching Fig. 6 Oscillgrams f gatedrive vltages G and G1, snubber inductr current I L, and bstswitch draintsurce vltage wavefrms at lw line (176 ac ) and full pwer (3 kw): (a) µs time base; (b) 500 ns time base Fig. 7 w/ snubber w/ snubber ( Ts = 9, Td = 65 ) Fs = 100 khz = OUTPUT POWER [kw] Measured efficiencies f the experimental cnverter with (slid lines) and withut (dashed lines) active snubber at the minimum and maximum line vltages as functins f the utput pwer. Nte that the maximum pssible utput pwer fr the implementatin withut the snubber is limited t.4 kw. Figure 7 shws the measured efficiencies f the experimental cnverter with (slid lines) and withut (dashed lines) the active snubber at the minimum and maximum line vltages as functins f the utput pwer. As can be seen frm Fig. 7, fr bth line vltages the active snubber imprves the cnversin efficiency in the entire measured pwer range (1 kw t 3 kw). Nevertheless, the efficiency imprvement is mre prnunced at the minimum line and higher pwer levels where the reverserecvery lsses are greater. pecifically, at the maximum line (65 ac ), the efficiency imprvement at 3 kw is 0.7%. Hwever, at the minimum line, the implementatin withut the active snubber cannt deliver mre than apprximately.4 kw due t the thermal runaway f the switch caused by excessive reverserecvery lsses. Even at P O =.4 kw, the active snubber imprves the efficiency by apprximately 1%, which translates int apprximately 0% reductin f the lsses. Figure 8 shws the measured temperatures f the experimental cnverter with (slid lines) and withut (dashed lines) the active snubber at the minimum line vltage as functins f the utput pwer. The ambient temperature was apprximately 9 during the measurement. As can be seen frm Fig. 8, at the same pwer levels, the temperatures f the semicnductr cmpnents in the implementatin with the active snubber are significantly lwer than thse in the implementatin withut the snubber. As indicated in Figs. 7 and 8, at the maximum line (65 ac ) and full pwer (3 kw), the case temperatures f the bst rectifier and bst switch in the implementatin with the snubber are T d = 4 O and T = 44 O, respectively, whereas the crrespnding temperatures in the implementatin withut the snubber are T d = 57 O and T = 68 O. imilarly, at the minimum line vltage (176 ac ) and full pwer, the rectifier and switch temperatures in the implementatin with the snubber are T d = 53 O and T = 84 O. As can be seen frm Figs. 7 and 8, the implementatin withut the snubber cannt deliver the full pwer f 3 kw at the minimum line because the rectifier becmes thermally unstable at apprximately.4 kw. In fact, fr the implementatin withut the snubber the temperature f the bst rectifier is T = 9 O at.4 kw, which is

7 TEMPERATURE [deg] Fig. 8 w/ snubber w/ snubber utput dide in = 176 ac, = 400 dc bst switch snubber switch OUTPUT POWER [kw] Measured switch temperature f the experimental cnverter with (slid lines) and withut (dashed lines) active snubber at the minimum line vltage as functins f the utput pwer. significantly higher than the temperature f the rectifier (T d = 60 O ) in the implementatin with the snubber at the same utput pwer. Figure 9 shws the measured wavefrm f the input line current f the prttype rectifier delivering 3 kw at 0 input vltage. ince the maximum duty cycle is nt limited by the additin f the active snubber circuit, the input current wavefrms with and withut the active snubber circuit are nearly identical. i in in 5. nclusin An activesnubber technique which reduces the reverserecveryrelated lsses and reduces the capacitivedischarge turnn switching lss f the bst cnverter has been described. Als, a cmplete design prcedure f a HPF bst cnverter with the active snubber circuit and extensive experimental evaluatins f its perfrmance n a 3kW prttype fr telecmmunicatin applicatins are presented. The evaluatin results demnstrate that the HPF bst cnverter at 100 khz switching frequency perates with an efficiency in the 9497% range at full pwer. The results f the experimental evaluatin have shwn that the prpsed activesnubber technique can significantly extend the maximum pwer range at which a fastrecvery rectifier can be reliably applied. References [1] Y. Khersnsky, M. Rbinsn,. Gutierrez, New fast recvery dide technlgy cuts circuit lsses, imprves reliability,'' Pwer nversin & Intelligent Mtin (PIM) Magazine, pp. 16 5, May 199. [] R. treit,. Tllik, High efficiency telecm rectifier using a nvel sftswitched bstbased input current shaper,'' Internatinal Telecmmunicatin Energy nf. (INTELE) Prc., pp , Oct [3] G. Hua,.. Leu, F.. Lee, Nvel zervltagetransitin PWM cnverters,'' IEEE Pwer Electrnics pecialists' nf. (PE) Rec., pp , June 199. [4].. Martins, F.J.M. de eixas, J.A. Brilhante, I. Barbi, A family f dctdc PWM cnverters using a new Z cmmutatin cell, IEEE Pwer Electrnics pecialists' nf. (PE) Rec., pp , June [5] J. Bassett, New, zer vltage switching, high frequency bst cnverter tplgy fr pwer factr crrectin,'' Internatinal Telecmmunicatin Energy nf. (INTELE) Prc., pp , Oct [6].M.. uarte, I. Barbi, A new family f ZPWM activeclamping dctdc bst cnverters: analysis, design, and experimentatin," Internatinal Telecmmunicatin Energy nf. (INTELE) Prc., pp , Oct [7] M.M. Jvanvi}, A technique fr reducing rectifier reverserecveryrelated lsses in highvltage, highpwer bst cnverters, IEEE Applied Pwer Electrnics (APE) nf. Prc., pp , Mar [8].M.. uarte, I. Barbi, An imprved family f ZPWM activeclamping dctdc cnverters, IEEE Pwer Electrnics pecialists' nf. (PE) Rec., pp , June Fig. 9: Input vltage in (100 /div) and input current i in (0 A/div) wavefrms at in = 0 rms, TH = 3.6%, PF = 99.3.