Design and Implementation of High Frequency Isolated AC-DC Converter for Switched Mode Power Supplies

Transcription

1 Design an Implementatin f High Frequency Islate AC-DC Cnverter fr Switche Me Pwer Supplies Dr. R. Kalpana, Prf. G. Bhuvaneswari, Prf. Bhim Singh an Saravana Prakash P Abstract In this paper the esign an implementatin f DC- DC cnverter base SMPS fr a telecmmunicatin system is presente. A high frequency transfrmer is use t prvie the galvanic islatin between the input an utput. A cmplete esign methlgy f high frequency transfrmer use fr fullbrige buck erive tplgy is presente. The perating mes, analysis, an esign cnsieratins are explaine fr the prpse cnverter. Simulatin an experimental results are als presente t emnstrate the perfrmance f the prpse cnverter. Keywrs High frequency islatin; Single-stage cnverter; Pwer factr crrectin (PFC); Full-brige buck cnverter; SMPS I. INTRODUCTI The use f three-phase ac-c cnverters fr telecmmunicatin pwer supply system [1] have le t an increase harmnic cntent being injecte int the utility mains an lw pwer factr, bth cause by the nn-linear la behavir f cnventinal ie-rectifiers. Telecmmunicatin pwer supplies have t cnfirm t lw THD input ac mains current an high PF as per IEC [2] an IEEE stanars [3]. The avantage f reucing the stress n the evices by single stage PFC an sft switching techniques are iscusse in the literatures [4] & [5]. A three-phase cnverter using single-phase mular rectifier tplgy has the merits f simple cntrl. They are becming ppular fr lw-vltage r meium-pwer supply applicatins [6]-[8]. In this paper, a high frequency (HF) islate ac-c cnverter with input pwer factr almst unity is presente. The single-phase mule is perate frm 230, 50Hz input t give regulate utput f 325 with a switching frequency f 35 khz. The circuit cnfiguratin, esign an implementatin f the cnverter using igital cntrller is presente. Finally, simulatin an experimental results are presente t emnstrate its satisfactry perfrmance. II. PROPOSED CERTER TOPOOGY FOR SMPS Fig. 1 shws the switche me pwer supply tplgy fr telecm pwer supply applicatins with the full-brige buck c-c cnverter incrprating PFC. A. Operatin Principle f the DC-DC Cnverter Fr three phase peratin the three set f single phase cnverter can be use. Fig. 2a shws the ne single-phase /14/$ IEEE Fig. 1 Schematic iagram f the HF islate c-c cnverter cnverter mule which is use fr the steay state analysis an esign purpse. It has a c vltage surce frm the iebrige rectifier with a series inuctr feeing t the full-brige c-c cnverter. The full-brige buck cnverter has fur IGBT switches (S1, S2, S3 an S4) an it is feeing t the high frequency transfrmer fr prviing galvanic islatin. The switches are alternatively in each half f PWM peri with the cntrlle with f pulse ecie by uty rati frm the PI cntrller. The peratin f the cnverter fr ne half-cycle using the equivalent circuits is explaine in the fllwing sectin. B. Analysis an Design f the DC-DC Cnverter In this sectin, the steay state analysis f the prpse cnverter is carrie ut t btain the require esign equatins an the parameters f the cnverter. Fr the esign an analysis f the full-brige cnverter, it is cnsiere that all the switches are ieal. The full-brige cc cnverter has tw intervals f peratin in each half cycle. T perate at CCM, the current shul nt tuch zer at the en f interval 1. Fig. 2 shws the basic circuits f a fullbrige buck c-c cnverter fr the tw intervals. In interval 1, S1 an S4 are n. In interval 2 all the fur switches are ff. The tw interval f peratin are explaine in etail as belw. Interval 1: T <t<dt s In this interval, tw iagnal switches S1 an S4 are an elivering energy t the la thrugh a high frequency transfrmer an tw ies. Fr this purpse the circuit mel as shwn in Fig. 2b is cnsiere. p (1) s1(n s1/n p) ; s2(n s2/n p) (2) The vltage acrss the utput inuctr, is as, (N /N ) - (3) s1 p c

2 Fig. 2a Schematic iagram fr analysis single-phase mule full-brige bst cnverter (b) Interval 1 (c) Interval 2 where, p is the vltage acrss the primary wining f the high frequency transfrmer. s1 an s2 are the vltages acrss the secnary winings f the high frequency transfrmer. is the input c vltage fr the full-brige c-c cnverter. is the vltage acrss the utput inuctr. c is the c utput vltage acrss the la. N p, N s1 an N s2 are the number f turns f the primary an secnary winings f the high frequency transfrmer. The rate f rise f the inuctr current i is given as, i (N s1/n p)-c (4) t The change in the inuctr current uring the n peri is as, ( n - ) ( Δ i ) (Δ t) c O N O N ( n - ) ( Δ i ) D T c O N S where, n(n s1 /N p ) (N s2 /N p ) an uty cycle, D(2T /T s). Interval 2: DT s <t< T s /2 In this interval all switches are ff uring the peri DT s < t < (T s /2) an the la current flws thrugh the ies. The equivalent circuit can be rawn as shwn in Fig. 2c. The rate f change f utput inuctr current is i -c (7) t (5) (6) The change in inuctr current uring the ff peri is as, -c ) OFF (Δ t) (8) OFF Ts T OFF -T 0.5Ts-T (9) 2 T OFF(0.5-D )T (10) s Substituting equatin (10) in equatin (8), the change in the inuctr current is btaine as, -c (11) ( Δ i ) O FF (0.5- D )TS Uner steay state cnitin, the change in the inuctr current is zer ver a half peri T s /2. ) + ) OFF0 (12) Substituting equatin (6) an (11) in equatin (12) as, ( n - c)d TS -(0.5- D )cts + 0 (13) On slving, eqn. (13) results in c2n D (14) Frm equatin (14) it is knwn that the utput vltage can be varie by ajusting the uty rati f the switch (D) an the high frequency transfrmer turns rati (n). During the peri the inuctr current increases linearly as, ( n - c) ) (Δ t) (15) ( n - c) I, max-i, min T (16) ( n - c) ) ripple T (17) Similarly, uring the peri when all the switches are ff, the current in the inuctr reuces as per eqn. (11). -c I, min-i, max (0.5- D)T (18) S c I, max-i, min (0.5- D)T (19) S c ) ripple (0.5- D)T (20) S Therefre the value f the inuctr is given as, (0.5- D )cts (21) ) ripple Fig. 3 shws the utput inuctr current an amplifie utput vltage typical wavefrms in CCM. The ripple vltage acrss the filter can be calculate as, Δ QCΔ (22) where, is the utput ripple vltage. This can be cnsiere as, Δ Q Δ (23) C The change in the charge Q can be calculate frm the area f the triangle representing the psitive current as shwn in Fig. 3 an expresse as, 1 T Δ i s Δ Q * * (24)

3 [{( ) (60) (29) (10e -6 )} / 4] 21.75µH Apprximating the calculate value, an inuctr f 20µH is chsen. Inuctrs with EE shape 65/39 n ferrite cre; tw turns with a 20 SWG wire is chsen fr the harware implementatin. Fr btaining the value f capacitr the fllwing values are use; 1% f the utput vltage c 60, therefre 0.6.The value f the utput capacitr C frm equatin (30) is as, C (D T s I c / ) (30) [{(0.5) (29)(10e -6 )(200)}/0.6] 4833µF An electrlytic capacitr f 7x680 µf, 100 capacitance which easily meets the minimum requirements is chsen fr the harware. Fig. 3 Characteristic wavefrms f the full-brige buck c-c cnverter The bunary between the CCM an DCM, by efinitin the inuctr current i reuces t zer at the en f the ff peri. At this bunary the average inuctr current is, Δi I I (25) 2 Substituting equatin (25) in equatin (24), the change in the capacitr charge is given by, 1 Ts Δ Q * *I (26) 2 4 Substituting equatin (26) in eqn. (23), the utput vltage ripple is given as, TI s Δ (27) 8C Therefre, the utput capacitr can be fun frm the ripple vltage as, TI s C (28) 8 (Δ ) ripple Equatin (28) is the bunary between CCM an DCM. The magnitue f utput vltage ripple is reuce by prperly esigning the cnverter cmpnents. The basic equatin fr the current flwing thrugh the inuctr is, ( I / T), n rearranging ( I / T) T cmpute the value f inuctance {(0.5-D) c T s /( i ) ripple } (29) where the uty rati D is cnsiere t be 0.45,utput c vltage c 60, a current I c 200A; switching frequency f s 35kHz, T s 29e-6 sec; ripple current is 2% f the la current, ( i ) ripple 4A. Substituting these values in equatin (29) the value f the inuctr is fun t be; C. Design f High Frequency Transfrmer The esign f high frequency transfrmer use fr fullbrige buck erive tplgy is presente in this sectin. The purpse f a high frequency transfrmer in SMPS is t transfer pwer efficiently an instantaneusly frm an electric surce t an external la. In ing s, the high frequency transfrmer als prvies imprtant aitinal capabilities: (i) The primary t secnary turn s rati can be establishe efficiently t accmmate wiely ifferent input an utput vltage levels. (ii) Separate primary an secnary winings facilitate high vltage input/utput islatin, especially imprtant fr safety applicatins. The steps fr esigning a high frequency transfrmer fr switch me pwer supplies are utline belw. The apprach presente here is lgical an a step by step prceure is illustrate by cnsiering full-brige buck c-c cnverter as an example. Step 1: Define the switche me pwer supply parameters pertaining t the high frequency transfrmer esign. Circuit tplgy: full-brige buck c-c cnverter Pwer Output, P 2kW; Transfrmer switching frequency f s 35kHz; Input vltage, in 560; Output vltage, 20, Output current I 100A Step 2: Define the abslute uty cycle limit an nminal D max at input vltage in-d. D max 0.5; D min 0.45 Nminal input vltage in-d in D max (560) (0.5) 280 Step 3: Calculate the nminal utput vltage by incluing the ie vltage rps. As there are tw rectifier ies at the secnary sie, a vltage rp f 1.6 is ae t the utput vltage. Nminal utput vltage -D Step 4: Calculate the turn s rati n f the high frequency transfrmer. n ( in-d / -D ) (280/21.6) apprximate t 13 turns acrss each secnary wining. The pssible chices f turn s rati are 26:1, 210:8. Since, the high frequency transfrmer is fllwe by centretappe ie rectificatin it has ne primary an tw secnary winings. Primary wining f 210 turns an secnary

4 wining f 8 turns, each secnary wining f 4 turns is the pssible chice f turns chsen fr the esign f high frequency transfrmer. Step 5: Calculate the current flwing thrugh each wining f the high frequency transfrmer. Nminal utput current I -D I D max (100) (0.5) 50A Nminal input current, I in-d (I -D /n) (50/13) 3.84 Therefre the primary current flwing thrugh the high frequency transfrmer is 4A. Step 6: The final step is the cre material, shape an size selectin fr the high frequency transfrmer. The cre material is selecte apprpriate fr the esire high frequency transfrmer. With pwer ferrites, higher frequency materials have higher resistivity, hence lwer ey current lsses. It is the best chice in transfrmer applicatins except fr mechanical ruggeness. It usually nees sme guiance in making an initial estimate f the cre size apprpriate fr the applicatin f switche me pwer supply requirements. One wiely use meth, with many variatins, is base n the cre area pruct A p, btaine by multiplying the effective cre magnetic crss-sectin area A e by the winw area A w available fr the wining. The fllwing frmula prvies a simple inicatin f the area pruct require: 4/3 A p A w A e P 4 cm (31) K u ΔB fs where, K u is the cre utilizatin factr. It is assume as fr full-brige an half-brige c-c cnverter. B is the flux ensity. A value can be chsen in between Tesla fr limiting the cre saturatin. It is assume as 0.25 Tesla. Therefre, the cre area pruct is 4/3 3 12x10 cm 3 (0.017)(0.25)(35x10 ) 31.69cm 4 4 The winw cnfiguratin is als cnsiere t be extremely imprtant. The winw shul be as wie as pssible t maximize wining breath an minimize the number f layers. This results in minimize leakage inuctance. The U an I cre shape is chsen fr the high frequency transfrmer. They have large winw area in relatin t cre size, an the winw has the esirable wie cnfiguratin. Fr the U 126/91/20 cre, the area pruct can be btaine frm the manufactures ata sheet. Fr the f U shape cre the fllwing cre parameters are btaine. Effective vlume cm 3 ; Effective length 48cm; Effective winw area f the cre, A w 5.6 cm 2 ; Effective cre magnetic crss-sectin area, A e 5.6 cm 2 The effective pruct area f the specifie cre is A p A w A e cm 4. It is bserve that the pruct area f the specifie U cre clsely matches with the pruct area f the cre that has been fun frm the initial estimate values (31.69 cm 4 ). In U series cre this is the nearest pssible value t the require A p. S this cre is selecte fr the esign. The etails high frequency transfrmers are as specifie belw: Transfrmer cre: Cre Material: Ferrite; Cre type, Family: UI series, tw U cres; Cre Size: 126/91/20mm fr ne U cre, 126/182/20mm fr tw U cres. Input vltage: 560, 4A; Output vltage: 20 acrss the secnary wining, 10 acrss the each secnary wining, 100A; Primary winings: Number f turns: 210 turns; SWG 18; Secnary Winings: Centre-tappe ie brige rectifier, tw secnary winings centre tappe, fur turns each wining, Wire strip: With20mm, thickness 0.5mm, Area10mm 2 III. CTRO SCHEME FOR THE PROPOSED DC-DC CERTER FOR SMPS T erive the gating signals fr the sli-state IGBT switches fr the full-brige c-c cnverter the reference supply currents alng with sense supply currents are use in the current cntrllers, which irectly generate switching signals. A. Current- Me PWM Cntrller Fig. 4 shws the cntrl strategy fr the full-brige c-c cnverter base current cntrlle technique fr input current shaping an pwer factr crrectin. The vltage errr cntrl signal errr is generate by summing the reference c vltage set an the sense c utput vltage c is prcesse by a vltage prprtinal an integral (PI) cntrller as shwn in Fig. 4. This is multiplie with the reference c vltage sample frm the utput vltage f the ie-brige rectifier s that the current reference signal I ref is pruce which cntains shape infrmatin f the vltage, an the utput c magnitue infrmatin frm the current base PI cntrller. The feefrwar cnstant vltage K v an current sensing K i are given as, K v (1/ max ) an K i (1/I max ) (32) The sample c link current I is then cmpare with the reference current signal an the net errr signal between the tw is amplifie t generate the cntrl signal c an it is then cmpare with a high frequency triangular wave t generate PWM signal. Fig. 4 Schematic f current PWM cntrller

5 The full-brige c-c cnverter is perate at a switching frequency f 35 khz which is internally generate by DS1104S_DSP_PWM blck. The utput vltage is sense by ADC channel 6 f DSP-SPACE an it is given as the sense vltage signal t the PI cntrller as shwn in Fig. 6. Fig. 5 Schematic iagram f harware implementatin B. Harware Implementatin f DSP Cntrller fr SMPS The real time implementatin f igital cntrl fr a threephase switche me pwer supply is carrie ut using a fast igital prcessr (SPACE DS1104). It mainly cnsists f a MPC8240 prcessr with PPC603e cre an n-chip peripherals. This is a 64-bit flating pint prcessr with 250MHz central prcessr unit (CPU) clck frequency. It als cnsists f a slave DSP TMS320F240 f Texas Instruments. Fig. 5 shws the schematic iagram f harware implementatin. A DSP cntrller (DS1104 SPACE) cnsists f SPACE as a master prcessr an TMS320F240 as slave prcessr. The fllwing peripherals f the prcessr are use fr the implementatin. 1) 4-channel, 12-bit analg t igital cnverter (ADC) is use t input the sense utput vltage. 2) 8-channel, 16-bit igital t analg cnverter (DAC) is use t take ut the signals frm the SPACE. The DAC channels are use fr taking ut the PWM pulses being given t the rivers f the IGBT s f the full-brige cnverter. C. Real Time Meling Using DSPACE The PWM gating signal fr the full-brige c-c cnverter is built-up with the help f MATAB Simulink an DSPSPACE. The Real Time Interface (RTI) mel is built in realtime t generate gating signal fr full-brige c-c cnverter an als t regulate the utput c vltage f the SMPS. The PWM signal generate frm SPACE are fe t the IGBT switches thrugh an islatin an amplifier circuit. Fig. 6 shws the RTI mel evelpe in DSP-SPACE fr PWM generatin an PI vltage cntrl. The uty rati is prvie as the input t the main blck DS1104S_DSP_PWM. The PWM uty cycle signals are generate by cmparing a level cntrl signal ( c ) with a cnstant peak repetitive triangle signal ( tri ). The frequency f the repetitive triangle signal establishes the switching frequency. The slave DS1104S_DSP_PWM generates frequency 1.67Hz t 5MHz. I. PERFOMANCE OF THE PROPOSED DC-DC CERTER In this sectin, simulatin an experimental results f the prpse c-c cnverter are presente. The ynamic perfrmance f the c-c cnverter has been simulate by switching the la suenly frm the steay state cnitin. Fig. 7 als shws the ynamic perfrmance f the prpse c-c cnverter uner step la cnitins frm 100% t 20% la an vice versa. It can be bserve frm Table I that the prpse high frequency cnverter results in nearly unity pwer factr in the wie perating range f the la an the input ac mains current THD is between 3.6% an 5.2% uner this varying la cnitin. Mrever, the input vltage THD f the cnverter is als between 2.4% an 1.2% which is within the stanar limits. T stuy the perfrmance f the c-c cnverter fr SMPS, a single mule islate full-brige c-c cnverter is evelpe in the labratry with the esigne cmpnents as specifie in the previus sectin. The clse lp vltage cntrl f full-brige c-c cnverter is implemente using DSP-SPACE. TABE I. POWER QUAITY INDICES FOR THE PROPOSED AC-DC CERTER FED SMPS UNDER ARYING OAD CDITIS a (%) v THD (%) i THD (%) DPF DF PF Fig. 6 RTI mel f PWM signal generatin fr full-brige c-c cnverter Fig. 7 Simulate results f the prpse high frequency c-c cnverter input currents, c-link vltage, c-link current, utput current an utput vltage wavefrms.

6 Fig. 8a Fig. 8b Fig. 8 Wavefrms f PWM gating signals fr full-brige c-c cnverter Fig. 9a shws the high frequency transfrmer parameter switching frequency f 35kHz. Fig. 9b shws the input vltage t the high frequency transfrmer, peak t peak vltage f 323 square wave generate by the full-brige c-c cnverter thugh IGBT switching an input capacitr. Figs. 9c an shw the utput vltage f the high frequency transfrmer f peak t peak (acrss the tw utput secnary wining) an 6.16 peak t peak (acrss each secnary wining). The turn s rati f high frequency transfrmer being teste f 26:1 in the secnary wining an 4 turns fr each secnary wining. Fig. 10 shws the utput c vltage an current fr ifferent las uner steay state cnitin. The slier gain blcks in virtual instruments f DSP-SPACE Cntrl Desk sftware is use t vary the real-time gain an view the signals. In clse lp vltage cntrl the PI parameters are tune t btain the values an t maintain cnstant c vltage acrss the la. The clse lp cntrl is teste fr 4 cnitin. The parameters f the cntrller are given belw, Fig. 9a Fig. 9b K p 0.90 an K i 0.02 fr 4 Fig.11 shws the respnse f utput wavefrms ue t suen variatins in the la cnitin f 4. It can be bserve that the vltage is maintaine cnstant even thugh there is a suen variatin in the la. Thus PI cntrller implemente using DSP-SPACE wrks well fr regulating the c utput vltage. Fig. 9c Fig. 9 Wavefrms f vltage an current f the HFT Fig. 9. CCUSI An islate high frequency c-c cnverter base SMPS fr telecmmunicatin systems has been escribe an valiate by igital implementatin. An average current me cntrl technique has been use t the prpse cnverter t prvie g la regulatin. The prpse high frequency cnverter fr switche me pwer supplies has been perate at almst unity pwer factr, with lw THD, an high efficiency. In aitin, it has regulate utput vltage with wie range f the la variatins. Fig. 10a Fig. 10b Fig. 10 Wavefrms f utput c la vltage an current Fig. 11a Fig. 11b Fig. 11 Wavefrms f utput c la vltage an current The labratry mel evelpe SMPS is teste fr 35kHz switching frequency. The PWM switching signal generate by DSP-SPACE is given t the full-brige c-c cnverter using islatin ptcupler circuit 6N137. Figs. 8a an b shw PWM switching signal fr the full-brige c-c cnverter fr tw ifferent uty cycles f 0.5 an 0.2 at 35 khz respectively. I. REFERENCE [1] Abraham I. Pressman, Switching Pwer Supply Design, McGraw-Hill, Internatinal Eitins, New Yrk, [2] imits fr Harmnic current Emissins, Internatinal Electrtechnical Cmmissin Stanar , [3] IEEE Recmmene Practices an Requirements fr Harmnics cntrl in Electric Pwer Systems, IEEE Stanar, 519, [4] D. D.C. u, H. H.C. Iu, an. Pievalica, A single-stage AC/DC cnverter with high pwer factr, regulate bus vltage, an utput vltage, IEEE Trans. n Pwer Electrnics, vl. 23, n. 1, pp , Jan [5] H.M. Suryawanshi, M.R. Ramteke, K.. Thakre an.b. Brghate, Unity-Pwer-Factr Operatin f Three-Phase AC DC Sft Switche Cnverter Base On Bst Active Clamp Tplgy in Mular Apprach, IEEE Trans. In. Electrn. vl. 23, n. 1, pp , Jan [6] T. Nussbaumer an J. W. Klar, Imprving mains current quality fr three-phase three-switch buck-type PWM rectifiers, IEEE Trans. Pwer Electrnics, vl. 21, n. 4, pp , Jul [7] Y.K. Eric H, S.Y.R. Hui, an Yim-Shu ee, Characterizatin f Single- Stage Three-Phase Pwer-Factr-Crrectin Circuit Using Mular Single- Phase PWM DC-t-DC Cnverters, IEEE Trans. n Pwer Electrnics, pp , January [8] A. R. Brges an I. Barbi, "Three-phase single stage AC-DC buck-bst cnverter perating in buck an bst mes," in Prc. COBEP, pp , Sept