M. Darwish Brunel University/School of Engineering and Design, London, C. C. Marouchos Cyprus University of Technology/Electrical

Transcription

1 An nvestigatin f the Switched-apacitr ircuit as a Slid-State Fault urrent imiting and nterrupting Device (FD) with Pwer Factr rrectin Suitable fr w-vltage Distributin Netwrks.. Maruchs yprus University f Technlgy/Electrical Engineering, imassl, yprus christs.maruchs@cut.ac.cy G. A. Putrus Nrthumbria University, Newcastle-upnTyne NE18ST, U.K ghanim.putrus@unn.ac.uk M. Darwish Brunel University/Schl f Engineering and Design, ndn, UK Mhamed.Darwish@brunel.ac.uk F. Paterakis Technlgical Educatinal nstitute f Athens, Dep. f Electrnic Engineering, Greece,fpatera@teiath.gr Abstract The Switched apacitr (S) ircuit is investigated in this paper as a Slid-State Fault urrent imiter and interrupting device (FD) with pwer factr crrectin suitable fr lw-vltage distributin netwrks. t was applied s far successfully as a pwer factr and harmnic current cmpensatr and as a Switched apacitr ircuit inverter. n this applicatin it is inserted in series with the supply line, prviding bth pwer factr crrectin and limitatin f the current t a pre-set value in the event f a fault. nterruptin f the fault is als pssible by setting bth semicnductr switches in the ff state. Overvltage is present in S ircuits and they appear acrss bth the passive and active cmpnents. The prblem can be alleviated by ptimising the system peratin and system cmpnents. ndex Terms Switched apacitr, Duty ycle, Pwer factr, urrent limiter, Distributin netwrk. NTRODUTON Fault current limiting and interrupting can nly be achieved by inserting a device in series with the line [1]. n this way the level f the fault current is limited t a safe value fr the circuit breakers t perfrm the interruptin. Thus the rating f the transfrmers, circuit breaker s (Bs), buses and ther electric equipment at fault current is lwer. Slid State switches are used tgether with reactrs []. tuned circuits [3] in Fault urrent imiters. An islating transfrmer [4]-[5] ptin prviding flexibility in the chice f the V ratings f the cmpnents used is als an ptin, Fig. 4. The impedance f the Switched apacitr (S) ircuit can be set either inductive r capacitive at any value by setting the duty cycle f the semicnductr switches, Fig.. n the past it was emplyed fr pwer factr crrectin [6] and fr harmnic current cmpensatin [7]. n this applicatin, the Switched apacitr circuit ffers the capacitive series impedance during nrmal peratin in rder t either make the pwer factr unity r just imprve it. The fact that the pwer factr crrectin takes place in series Fig. 3, gives rise t the lad vltage, Fig. 5. During a fault the impedance f the S capacitr circuit can be set at any value in rder t limit the current t a safe and predetermined value. mpensatin f the pwer factr is dne by adjusting the impedance f the S ircuit t match the impedance f the lad. Specifically since mst f the lads are inductive, the reactance f the S circuit is set capacitive at a value t set the pwer factr at any value including unity. The entire lad current flws thrugh the passive and any active cmpnents f the Fault urrent imiter. n the case f the S ircuit, the full lad current flws thrugh the semicnductr switches, the capacitr and the inductr giving rise t a high vltage acrss the capacitr and lsses. The varius results fr all cases were btained thrugh PSM simulatins.. THE SWTHED APATOR RUT AS A URRENT M- TER AND POWER FATOR OMPENSATOR A. The switched capacitr circuit The semicnductr switches in a switched capacitr circuit are wrking in antiparallel Fig. 1. The current is diverted frm S t and thrugh the capacitr. n this way the ttal impedance f the switched capacitr circuit can be set either zer, capacitive r inductive and anything in between by setting the duty cycle f the switch, Fig.. The impedance f the circuit as a functin f the duty cycle f the semicnductr switch is derived accrding t [6] and [8] as K ( ) = + ω ω ZK r Where K is the duty cycle f, r represents the hmic resistance f the passive cmpnents and semicnductr switches, is the mains frequency, and are the values f the inductr and the capacitr in Fig. 1. The impedance Z f Fig. 1, is set accrding t (1) by the values f, and K. Fr =.5 and H =4F, it is inductive fr values f K less than.444 and capacitive fr values (1) /17/$ EEE

2 f K abve.444 as shwn in Fig.. Resnance is als pssible at K =.444 where the impedance f the circuit is reduced t the small hmic resistance r. An bvius applicatin f this circuit is as a pwer factr cmpensatr [6]. S 3.14 capacitive reactance. This is dne by setting the duty cycle f the switch in Fig. 3, t.4867 accrding t (1). Alternatively it can be read frm Fig.. The general vectr diagram is shwn in Fig. 5. Fig. 6a, displays the current uncmpensated at a pwer factr f.786 and in Fig. 6b, cmpensated at unity pwer factr. As expected the vltage acrss the lad will rise with the pwer factr crrectin. in(t) The switched apacitr circuit (t) S Fig.1. The switched apacitr circuit. =.5H =4F V ad(t) O A D Mechanism t apply shrt circuit inductive capacitive Fig. 3. The pwer circuit f the S current limiter and pwer factr cmpensatr. S The switched apacitr circuit (t) Fig.. mpedance f the switched capacitr circuit against K, the duty cycle f the switch. B. The switched capacitr circuit as a current limiter and pwer factr cmpensatr n this applicatin the switched capacitr circuit is inserted in series with the lad Fig. 3, prviding pwer factr crrectin and in the event f a fault it limits the current t a preset value. nterruptin f the fault is als pssible by setting bth semicnductr switches, S in the ff state. An islating transfrmer [5]-[7] ptin prviding flexibility in the chice f the V ratings f the cmpnents used is als an ptin, Fig. 4. The lad cnsists f a 4 resistr and.1h giving a lad pwer factr f.786 and a line current f 56A. The S ircuit inductance and capacitance are set in the first instance at.5h and the capacitr is 4F. ater n, anther set f and values is emplyed in rder t cntrl the vltage acrss the capacitr and the switches. n nrmal peratin the S circuit is acting as a pwer factr crrectr. The inductive impedance f the lad is matched t the impedance f the S circuit by chsing the apprpriate value f the duty cycle K. Specifically, the lad reactance is n rder t make the pwer factr unity the S circuit must prvide V ad(t) Fig. 4. The pwer circuit f the S current limiter and pwer factr cmpensatr with islating transfrmer. (t) V (t) Fig. 5. Vectr diagram fr setting the pwer factr. O A D Mechanism t apply shrt circuit

3 n the event f a fault there is the impedance f the S ircuit f 3.14 (ase A) t limit the current, Fig. 7a. As shwn at the beginning f the fault (t =1s) the current increases frm 5A t 15A but it decays quickly t 45A in less than a secnd. The final value f the current will be set by the S ircuit 3.14 impedance. The presence f the fault can be sensed by bserving the frequency spectrum f the fault current, Fig. 7b. A strng 59Hz harmnic appears during the fault. The reactin f the circuit t a fault is tested further by inserting the full capacitive reactance f the S ircuit (ase B) ne cycle after the ccurrence f the fault. This is the reactance f the 4F capacitr, Fig. 8a, displays the current befre and during the fault with its maximum value rising t 118A. The insertin f the 79.6 reactance is achieved by setting the duty cycle K f the semicnductr switch t ne as dictated frm (1) and Fig.. The fault current eventually decays t a value dictated by the 79.6 reactance i.e. 4A. A strng presence f a 11Hz harmnic Fig. 8b, is bserved during the fault. Finally the circuit is tested by inserting the full inductive reactance f the circuit (ase ) ne cycle after the ccurrence f the fault, Fig. 9a. t is raising the current t 14A with a strng decaying dc cmpnent, Fig. 9b. The fault current eventually decays t a value dictated by the reactance i.e. 14.8A. The insertin f the reactance is accmmdated by setting the duty cycle f the switch K t zer as dictated by (1). Furthermre, interruptin f the fault is pssible at any pint by switching ff bth switches, S. Of curse the fault current can be set t any value by adjusting K accrdingly Vin 4 5 NPUT VOTAGE NPUT URRENT Fig. 7a. urrent during fault cnditins ase A: N actin. =.5 = 4F Fig. 6a. The line current uncmpensated pf=.63. Vin 4 NPUT VOTAGE NPUT URRENT Fig. 6b. The line current cmpensated pf= 1. Fig. 7b. Frequency Spectrum f the current during fault cnditins ase A: N actin. =.5 = 4F Fig. 8a. The current during fault cnditins ase B: Maximum impedancecapacitive. =.5 = 4F

4 1 8 11Hz 87A acrss the capacitr and switches can be reduced further if a pwer factr less than unity is acceptable, Fig. 5. The capacitr vltage can be reduced by 3% and still retain a pf f.9 leading Hz 5.97A Frequency (Hz) Fig. 8b. Frequency Spectrum f the current during fault cnditins ase B: Maximum impedance-capacitive. =.5 = 4F Ratings f cmpnents f the switched capacitr and ptimizatin. The S circuit is characterized by vervltage phenmena acrss bth the passive and active cmpnents, Fig. 1. The vltage acrss the capacitr and hence the semicnductr switches is easily derived fr the fundamental cmpnent by cnsidering the current entering the switched capacitr as the rati f the supply vltage V t the impedance and the fact that the current () entering the capacitr is determined by the duty cycle K f [8]. Hence the vltage acrss the capacitr and the switches is given by (3) Fig. 9a. The current during fault cnditins ase : Maximum impedanceinductive. =.5 = 4F 8 6 D 78A The current entering the capacitr is V () t = K K r + ω ω The vltage acrss the capacitr is () 4 5Hz.7A V V() t = K K r + ω ω 1 ω During nrmal peratin when the S ircuit is perfrming nly pwer factr crrectin the vltage acrss the capacitr and hence the semicnductr switches can be much higher than the supply vltage, Fig. 1. This is basically determined by the / rati. As shwn in Fig. 1, there is a dramatic reductin f this vltage fr lwer ratis. Fr a 56A lad and pwer factr at.786, if unity pf crrectin is needed, utilizing high / rati where, =.5H and =4F, the vltage acrss the capacitr is raised t 9V given by (3), a vltage which is very high. This is decreased t 686V by a lwer / rati where, =.5H and =F. The vltage (3) Frequency (Hz) Fig. 9b. Frequency Spectrum f the current during fault cnditins ase : Maximum impedance-inductive. =.5 = 4F Frm the lad side, the utput vltage is increased because the pwer factr is cmpensated in series, Fig. 5. Specifically, with the high rati f ( =.5H =4F) the utput vltage is raised t 74V but reduced t 48V by setting the lwer / rati with pwer factr f.9 leading. Therefre with prper ptimisatin the utput vltage is expected t be within acceptable limits. Under these cnditins with leading pwer factr the S ircuit is als prviding leading KVA t the grid. Further ptimizatin is pssible.

5 Mre ptins t the designer are ffered by emplying the circuit f Fig. 4, where a transfrmer is used t cnnect the S circuit t the netwrk. The leakage inductance f the transfrmer can be utilized t replace the inductr in the pwer circuit f Fig. 3. ts turn rati can be arranged t accmmdate the vltage ratings f the capacitr and the semicnductr switches. (KV) =.5H =4F current. Of curse the frequency and magnitude f the harmnic depends n the values f. A drawback f this prepsitin is the fact that bth the semicnductr switch and the capacitr can be subjected t a vltage higher than the supply. t was shwn thugh that this becmes manageable by selecting a lwer / rati and further reductin is pssible by adpting a lwer but leading pwer factr than unity. Further ptimizatin is pssible by emplying a transfrmer t cnnect S t the line. Anther disadvantage is the increase f the lad vltage when the S is perfrming pwer factr crrectin. t might be an advantage in areas where the grid vltage is lw but this des nt happen always. Adpting a leading pwer factr less than unity (.9) can reduce it by 35%. The switching frequency f the semicnductr switches and S sets the vltage harmnics acrss the lad. Fr this reasn the switching frequency must be ptimized with the size f the passive filter against the switching lsses. Fig. 1. Vltage acrss the capacitr (KV) as a functin f K.. =.5H =F DSUSSON The S ircuit is emplyed in a new applicatin t crrect bth the pf and at the same time it is a slid-state fault current limiting and interrupting device (FD) fr lw vltage distributin netwrks. The S circuit is inserted in series with the pwer line and its current limiting ability lies in the fact that its impedance is smthly cntrlled by the duty cycle f its switches, K. Fr pwer factr crrectin the reactive impedance f the lad is cmpensated by the impedance f the S circuit. The ability f the circuit t cntrl the fault lies in the fact that there is always the reactive impedance f the S ircuit in series with the line at the cnnectin pint. While this circuit can be used in lw-vltage (V) systems as well, at this stage n cnsideratin has been taken t csts. Since, this limiter is nt in practical use yet the circuit is tested thrugh PSM simulatin under three cnditins. n the first case in the event f the fault n actin is taken and the current first rises frm 5A t 15A and quickly decays t 45A within ne secnd. n the secnd case the full impedance f the S circuit 79.6 is inserted with the current first rising frm 5A t 118A and quickly decays twards 4A. n a final test the full inductive reactance f the S circuit is inserted and the current first rises frm 5A t 14A and quickly decays twards 14.8A. n all three cases the value f the duty cycle K f the switch is set accrdingly. Actually the series impedance f the S circuit can be set t any value in rder t keep the current with any preset limits value by selecting the apprpriate value f K. The presence f a fault can be detected frm the strng 59Hz harmnic in the fault REFERENES [1] M. M. R. Ahmed, G. Putrus, i Ran and R. Penlingtn, "Develpment f a prttype slid-state fault-current limiting and interrupting device fr lw-vltage distributin netwrks," in EEE Transactins n Pwer Delivery, vl. 1, n. 4, pp , Oct. 6. [] Radmanesh, S.H.Fathi, and G.B.Gharehpetian, Nvel high perfrmance D reactr type fault current limiter, Elect. Pwer Syst. Res., vl. 1, pp , May 15. [3] H. Radmanesh, S. H. Fathi, G. B. Gharehpetian and A. Heidary, "A Nvel Slid-State Fault urrent-imiting ircuit Breaker fr Medium- Vltage Netwrk Applicatins," in EEE Transactins n Pwer Delivery, vl. 31, n. 1, pp , Feb. 16. [4] A. Abramvitz and K. Ma Smedley, "Survey f Slid-State Fault urrent imiters," in EEE Transactins n Pwer Electrnics, vl. 7, n. 6, pp , June 1. [5] Seyed Behzad Naderi, Mehdi Jafari, Mehrdad Tarafdar Hagh, ntrllable resistive type fault current limiter (R-F) with frequency and pulse duty-cycle, nternatinal Jurnal f Electrical Pwer & Energy Systems, Vlume 61, Octber 14, Pages 11-19, SSN [6]. Maruchs, M. K. Darwish and M. El-Habruk, "Variable var cmpensatr circuits," in EE Prceedings - Electric Pwer Applicatins, vl. 153, n. 5, pp , September 6. [7].. Maruchs, M. Evdkimu and M. Darwich, "Applicatin f the switched capacitr cmpensatr in clsed lp," 14 49th nternatinal Universities Pwer Engineering nference (UPE), luj-napca, 14, pp [8].. Maruchs, "The Switching Functin: analysis f pwer electrnic circuits," in ircuits, Devices and Systems Series 17, ndn: nstitutin f Engineering and Technlgy, 8.