Novel Approach to Design of a Class-EJ Power Amplifier Using High Power Technology F. Rahmani, F. Razaghian, A. R. Kashaninia

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1 Nvel Apprach t Design f a Class-EJ Pwer Amplifier Using High Pwer Technlgy F. Rahmani, F. Razaghian, A. R. Kashaninia Abstract This article prpses a new methd fr applicatin in cmmunicatin circuit systems that increase efficiency, PAE, utput pwer and gain in the circuit. The prpsed methd is based n a cmbinatin f switching class-e and class-j and has been termed class-ej. This methd was investigated using bth thery and simulatin t cnfirm 72% PAE and utput pwer f >39dBm. The cmbinatin and design f the prpsed pwer amplifier accrues gain f ver 15dB in the 2.9 t 3.5GHz frequency bandwidth. This circuit was designed using MOSFET and high pwer transistrs. The ladand surce-pull methd achieved the best input and utput netwrks using lumped elements. The prpsed technique was investigated fr fundamental and secnd harmnics having desirable amplitudes fr the utput signal. Keywrds Pwer Amplifier (PA), GaN HEMT, Class-J and Class-E, High Efficiency. M I. INTRODUCTION ODERN wireless cmmunicatin systems have experienced nging evlutin that emplys cmplex mdulatin designs that increase infrmatin n the high efficiency bradband bandwidth and desirable data rates [1]. The high demand f cnsumers fr smart phnes that are csteffective and preserve battery pwer has increased prgress in bradband bandwidth f systems with lumped elements at radi frequency. Pwer amplifiers fr different classes were investigated using pwer-cnsuming cmpnents fr RF wireless cmmunicatins and TV transmissin [2], [3]. Pwer amplifiers are usually the last stage f transmitter cnfiguratin and are imprtant cmpnents f RF circuits. The efficiency, utput pwer and bandwidth f the pwer amplifier directly affect the cmpnents f the system. High pwer efficiency decreases DC pwer cnsumptin and dissipates heat which significantly affects the ttal pwer cnsumed, stability, DC pwer supply and cling systems. Systems used in mdern generatin f wireless cmmunicatin systems handle wrldwide mutual cmmunicatin fr micrwave access and mdulated signals with bradband bandwidth. This means that the design f a bradband amplifier is mst imprtant fr such systems [1]. Wireless cmmunicatin systems require high pwer linear amplifiers t send a signal with minimum phase and amplitude F. Rahmani is with the Department f Electrnics, Central Tehran Branch, Islamic Azad University, Iran (crrespnding Rahmani t prvide phne: ; fax: ; sh10166r@yah.cm). F. Razaghian is with the Department f Electrnics, Suth Tehran Branch, Islamic Azad University, Iran ( razaghian@azad.ac.ir). A. R. Kashaninia is with the Department f Electrnics, Central Tehran Branch, Islamic Azad University, Iran ( ali.kashaniniya@iauctb.ac.ir). distrtin t a receiver. A useful design methd is ne that imprves efficiency and utput pwer simultaneusly using single r mixed classes f pwer amplifier. Mst pwer amplifiers are based n the cnfiguratins and perfrmance f such classes, which are classified as A, B, C, AB, D, F, F -1, S, E, J, etc. [5], [6]. The present study selected class-j and class-e t achieve higher efficiency and utput pwer. Class-J has linear prperties, because it is designed fr the bias pint f class- AB r class-b. F. Rahmani [6] and V Carruba [7] investigated mixed class-abj. The prpsed class-ej methd imprves the efficiency and utput pwer at higher frequencies than thse f class-abj. II. HIGH POWER GAN CGH40010F TRANSISTOR The GaN CGH40010F transistr mdel was selected fr design f the prpsed circuit because it has the unique ability fr high electrn mbility in GaN transistrs. This type f transistr was analyzed fr a 28V supply that represents general purpse bradband fr varius RF and micrwave applicatins. GaN HEMT transistrs prvide higher efficiency and gain with mre bandwidth than ther transistrs. The CGH40010F transistr is made fr linear circuits with cmpact dimensins. Cmparisns were carried ut between the different substrates f the pwer amplifier. TABLE I THE COMPARISON BETWEEN DIFFERENT SUBSTRATES FOR SELECTING THE BEST TRANSISTOR [8] Parameter Dimensin Cmparisn 1 Saturated Velcity ( 10 7 ) "cm/s" Si[1.08]<GaAs[1.3]<GaN[2.7] 2 High Electrn Mbility ( 10 3 ) "cm 2 /V/s" Si[1.5]<GaN[3]<GaAs[6] 3 Breakdwn E Field "MV/cm" GaAs[0.4]<Si[0.5]< GaN[3] 4 Band Gap Energy "ev" Si[1.13]<GaAs[1.4]<GaN[3.4] 5 Output pwer density "W/mm" Si[0.8]<GaAs[1.5]<GaN[7] Table I [8] shws that the GaN substrate is best fr design f high pwer circuits, which makes it a perfect chice fr design f class-ej. Fig. 1 shws the bias pint at I DS = 0.5A and V DS = 28V fr the GaN transistr in ADS (Advanced Design System) sftware. The prpsed circuit was designed fr a 3.2 GHz central frequency. T determine the central frequency f the class-ej circuit, as shwn in Table II, the stability factrs must always be StabFact >1 and StabMeas>0. TABLE II ANALYSIS OF THE STABILITY FACTORS Frequency StabFact StabMeas 3.2 GHz

Fig. 1 Definitin the bias pint f the GaN transistr Table III shws that the results f analysis f the S-parameter fr the selected transistrs was S(2,1) > S(1,2). This transistr has desirable parameters.

2 Fig. 1 Definitin the bias pint f the GaN transistr Table III shws that the results f analysis f the S-parameter fr the selected transistrs was S(2,1) > S(1,2). This transistr has desirable parameters. Tables I and II shw that the selected transistr is stable and has desirable stability factrs fr small signal analysis. TABLE III S-PARAMETERS ANALYSIS AT THE 3.2GHZ FREQUENCY S (1,1) = S (2,1) = S (1,2) = S (2, 2) = Fig. 2 shws the stability f the transistr based n surce and lad stability circles. If the surce and lad lines fall utside the Smith chart, the transistr will be stable. If the Smith chart includes these lines, the transistr will be unstable. The transistr in Fig. 2 is unstable at 1 t 3.2 GHz and is stable at 3.2 t 8 GHz. This indicates that the central frequency was selected prperly, because f lines fall utside the Smith chart. Fig. 2 Display stability f the transistr accrding t the lad and surce stability circles III.DESIGN OF CLASS-EJ A. Class-EJ Pwer Amplifier Class-E is a switching class. The results f simulatin shw analg wavefrms that can apprximately supprt a device with fewer switching characteristics in a linear regin. Class-E decreases the cnductin angle t deliver higher efficiency withut a cmplex circuit, such as an advanced class-f design. One advantage f a switching mde pwer amplifier such as class-e is its high perfrmance n a lw bias vltage supply. This class decreases pwer dissipatin ver ther switching mde pwer amplifiers at similar frequencies. Class-E is designed t prvide a circuit with smaller dimensins [4]. The basic thery f class-j is an ideal wavefrm frmed by cntrlled terminatin f fundamental impedance and harmnic impedances. Cripps [9] stated that class-j is a shrt circuit up t terminatin f the third harmnic impedance; this class has its wn bandwidth and the utput capacitr can be used as a shrt circuit in upper harmnics and als remain fundamental and secnd harmnics. The utput matching netwrk in the fundamental harmnic is slightly inductive and in the secnd harmnic is capacitive. The utput stage f the class-ej pwer amplifier uses class-j, because class-j is mre efficient than class-e in the first stage. Fundamental and secnd harmnic impedances in class-j is a cmplex number with real and imaginary parts, such as α+jβ. T imprve the perfrmance f the prpsed circuit and btain maximum efficiency, utput pwer and gain, class-e and class-j were merged t prduce the prpsed design f class-ej. This new class was designed with class-e and class-j having less input pwer and greater utput pwer. The main purpse f the tw-stage pwer amplifier is t increase gain and decrease input pwer (P in ) in the circuit. B. Bias Circuit The bias circuit was designed using a MOSFET transistr in the utput and input class-ej circuit. The bias circuit increases the input vltage n the gate f the GaN transistr. Fig. 3 shws that the gate vltage was 6.8 V with bias circuit but fr a class-ej withut a bias circuit, the gate vltage decreased t 5.5 V and the gate current was 0.62 A. Fig. 3 Current and vltage f gate diagrams f the transistr fr class-ej Fig. 4 indicates that the input bias circuit increased the gate supply vltage in the first stage f the class-ej pwer amplifier. Fig. 5 shws that the utput bias circuit in the secnd stage cnsisted f a 20nH chke inductr. One chke inductr was used in the utput bias circuit t decrease DC pwer in the drain f the GaN transistr. The1 Ω internal resistance frm the circuit was an ideal frm and apprached a real circuit. Each stage f the class-ej pwer amplifier cnsisted f tw bias circuits at the gate and drain f the transistrs. Tw f the fur bias circuits require explanatin in this study. 542

Fig. 4 The prpsed input bias circuit f class-e which is first stage f class-ej pwer amplifier Fig. 5 The prpsed utput bias circuit f class-j which is secnd stage f class-ej pwer amplifier C.

amplifier. The pwer-added-efficiency (PAE) and pwer delivered t the lad was btained by harmnic balance analysis cnsidering the 50 Ω utput resistance.

Table IV shws the ptimum impedance fr the input and utput f the first and secnd stages f the class-ej pwer amplifier and the values fr utput pwer and PAE frm the simulatin results fr the lad- and

12% Class-J - 14.08+j7.01 39.42 47.55% 9.60-j1.33-40.33 47.

3 Fig. 4 The prpsed input bias circuit f class-e which is first stage f class-ej pwer amplifier Fig. 5 The prpsed utput bias circuit f class-j which is secnd stage f class-ej pwer amplifier C. Input and Output Matching Circuit Lad- and surce-pull techniques are the best methds t determine input and utput matching circuits and btain ptimum impedance f the input and utput f the pwer amplifier. The pwer-added-efficiency (PAE) and pwer delivered t the lad was btained by harmnic balance analysis cnsidering the 50 Ω utput resistance. Matching circuit was dne with lumped elements based n the cnfiguratin f tw classes f pwer amplifier. Table IV shws the ptimum impedance fr the input and utput f the first and secnd stages f the class-ej pwer amplifier and the values fr utput pwer and PAE frm the simulatin results fr the lad- and surce-pull methds. TABLE IV OPTIMUM INPUT AND OUTPUT IMPEDANCE USING LOAD- AND SOURCE-PULL TECHNIQUE Class Z In Z Out P ut (dbm) PAE Class-E 8.64+j % j % Class-J j % 9.60-j % After btaining the ptimum impedances fr the input and utput f the tw-stage class-ej pwer amplifier, the best circuits with the smallest dimensins were designed using the Smith chart and the lumped elements were determined based n the cnfiguratins f class-e and class-j. The fllwing pints must be cnsidered fr the design f the class-ej circuit: 1. As shwn in Fig. 6, input resistance (R 1 ) is cnsidered as far as pssible small in the input matching circuit f the first stage, because it plays a majr rle in determining efficiency. 2. As shwn in Fig. 7, a series inductr (L 15 ) is required at the beginning f the utput matching design t create the highest harmnic impedance fr design f first stage utput matching fr the class-ej pwer amplifier. 3. Fig. 7 als shws that the parallel capacitr must be placed at the end f the secnd stage (class-j) because the impedance f the capacitr (C 6 ), inductr (L 1 ) and resistr (R 4 ) are calculated in parallel with C 4, decreasing input impedance and input pwer. Fig. 6 The input first stage class-ej pwer amplifier Fig. 7 The utput first stage and the input secnd stage f the class-ej 4. Fig. 8 indicates that there is a parallel capacitr (C 3 ) in utput class-j causing impedance t shrt-circuit at higher frequencies. Accrding t the equatin 1, the Z = jc 2πf upper secnd harmnics becmes ineffective. It is imprtant t determine the utput capacitr in the class-j f the class-ej pwer amplifier. The rati f capacitive reactance t lad resistance shuld be equal t r less than unity. In this paper, (1) and R = 50 Ω make the rati: X 5. In Fig. 8, efficiency increased and DC pwer decreased by resistance (R 2 ) in the utput bias f the secnd stage class-ej, because there was a lss in the series resistr that decreased the DC supply vltage and increased efficiency. L C ds R L = 3 (1) 543

TABLE VI COMPARISON OF SIMULATION RESULTS BETWEEN THE CLASS-EJ POWER AMPLIFIERS WITH DONE PREVIOUS WORKS Class Frequency Technlgy Vltage Supply Efficiency Year [Ref] E 2GHz GaN HEMT 50V 74.

3% This Wrk J 3.2GHz CGH40010F 28V 85.9% This Wrk EJ 3.2GHz CGH40010F 28V 87.8% This Wrk Fig.

4 TABLE VI COMPARISON OF SIMULATION RESULTS BETWEEN THE CLASS-EJ POWER AMPLIFIERS WITH DONE PREVIOUS WORKS Class Frequency Technlgy Vltage Supply Efficiency Year [Ref] E 2GHz GaN HEMT 50V 74.4% 2007 [10] E 2.14GHz GaN HEMT 40V 74% 2009 [10] J 2.14GHz GaN HEMT 30V 77.3% 2010 [10] J 1.15GHz CGH V 50-69% 2012 [11] J 2.3GHz CGH40010F 28V 60-75% 2013 [5] E 3.2GHz CGH40010F 28V 84.3% This Wrk J 3.2GHz CGH40010F 28V 85.9% This Wrk EJ 3.2GHz CGH40010F 28V 87.8% This Wrk Fig. 8 The utput secnd stage class-ej pwer amplifier After finding the knee vltage and accrding t the fllwing equatins, lad impedance was calculated fr the first and secnd harmnics. In these equatins, V k = 5.6 V and I max = A. Z = R + jr = j (2) F1 pt pt 3π ZF = j R 2 pt = j 56.5 (3) 8 ( ) 2 V V = = Ω (4) DC k R pt Imax IV.SIMULATION RESULTS FOR CLASS-EJ A. Simulatin Results When calculating the PAE, all the DC current f the circuit and drain efficiency is the suppsed utput DC current. The simulatin results are listed in Table V and shw the results btained frm the prpsed class-ej pwer amplifier. The gal f the prpsed PA is t decrease the input pwer t btain maximum PAE, efficiency and utput pwer. The desired results were achieved using the prpsed tw-stage PA circuit and by increasing the gain f the prpsed circuit. TABLE V COMPARISON OF SIMULATION RESULTS BETWEEN THE FIRST STAGE, SECOND STAGE AND FINAL CIRCUIT Parameter First Stage (Class-E) Secnd Stage (Class-J) Class-EJ P in (dbm) PAE (%) P ut (dbm) Gain (db) The best results fr the prpsed pwer amplifier btained the highest utput pwer, drain efficiency and PAE fr high pwer technlgies with the lwest input pwer. Table V indicates that the class-ej increased PAE and gain but decreased utput pwer. Table VI cmpares the simulatin results fr the class-ej pwer amplifier and dne previus wrks and indicates that the prpsed circuit is perfrmed better than the ther wrks. B. Analysis f Simulatin Results The utput parameters were analyzed and the results are investigated using the determined bandwidth. Fig. 9 shws that analysis f the first and third harmnics indicate very desirable utput pwer at the 2.9 t 3.5GHz bandwidth. The first harmnic f the utput spectrum at the fundamental frequency was dBm and the third harmnic at the same frequency was dBm. The mre negative the numerical value f the harmnics becmes, the better the perfrmance f the circuit. Fig. 9 Analysis f the utput spectrum parameter in the fundamental and third harmnics Fig. 10 (b) shws that the utput vltage wavefrm is similar t the sinusidal input vltage wavefrm; if the utput spectrum at the higher harmnics decreases, the utput wavefrm is similar t the sine wave. Fig. 10 (a) indicates a dwntrend f the utput spectrum frm the fundamental harmnic t the third harmnic and shws suitable matching in the input and utput f the prpsed circuit. If the utput capacitr is cnsidered t change, because it plays a majr rle in the design f the secnd stage (class-j), the values f the capacitr can be changed t a value in the range f 0.5 pf t 5pF. Fig. 11 shws the results fr the gain and utput pwer, after which the best value fr the utput capacitr culd be specified. The best value fr the utput capacitr (C 3 ) is 1.5 pf because f the utput pwer (P ut = dbm) and gain (G RF = 19.4 db) btained. The utput circuit f class-j was designed using the lad-pull methd, making the value f the utput capacitr equal t pf; the accuracy f the utput matching design was cnfirmed in this manner. 544

5 Wrld Academy f Science, Engineering and Technlgy Fig. 13 Output and input pwer at the 1dB gain cmpressin pint Fig. 10 (a) Output spectrum at the fundamental, secnd and third harmnic frequencies (b) The utput vltage sinusidal wavefrm The 27.5 dbm input pwer must be chsen frm a range f Pin = 20 t 30dBm t increase PAE t 70%. Fig. 14 and Table VII shws that utput parameters such as PAE, P_gain_transducer, PDC, Imax and Put are specified based n the 0.6 GHz bandwidth in the prpsed circuit. TABLE VII OUTPUT PARAMETERS ARE SPECIFIED BASED ON 0.6GHZ BANDWIDTH Frequency Output Pwer Output Pwer Max current (GHz) (dbm) (dbm) (A) Fig. 11 (a) Output vltage parameter t variatins f the utput capacitr (b) Gain parameter t variatins f the utput capacitr If the utput pwer des nt increase prperly fr the input pwer, the amplifier is in cmpressin mde, s the gain cmpressin pint must be calculated t limit the level f input pwer that will cause nnlinear harmnic distrtin. This pint is usually the input pwer that decreases the gain (1 db) t that f nrmal linear gain. Fig. 12 shws the utput spectrum f the class-ej pwer amplifier at the 1dB gain cmpressin pint. Fig. 14 PAE and P_gain_transducer at the 0.6GHz bandwidth Fig. 12 Output spectrum at the 1dB gain cmpressin pint The fllwing graphs and equatin illustrate the extractin f meaningful results frm the simulatin. T determine the input pwer leading t a gain cmpressin pint f 1dB, a marker is placed n each trace and they are mved s that their difference appraches 1dB. The fllwing plt shws the input and utput pwer at abut 1dB fr the gain cmpressin pint. Fig. 15 The input and utput vltage wavefrms Fig. 15 shws the input and utput vltage wavefrms and Fig. 16 shws the lad current wavefrm f the class-ej pwer amplifier. Current and vltage wavefrms at the utput stage f the class-ej pwer amplifier shuld have a phase difference f

6 [10] J. Mn, J. Kim and K. Bumman, "Investigatin f a Class-J Pwer Amplifier With a Nnlinear C ut fr Optimized Operatin", Micrwave Thery and Techniques IEEE Transactins, Vl. 58, Issue 11, , Nv [11] K. Mimis, K. A. Mrris, S. Bensmida and J. P. McGeehan, "Multichannel and Wideband Pwer Amplifier Design Methdlgy fr 4G Cmmunicatin Systems Based n Hybrid Class-J Operatin", Micrwave Thery and Techniques IEEE Transactins, Vl. 60, , August 2012, pp Fig. 16 The lad current wavefrm V.CONCLUSION This study develped a new apprach called the tw-stage class-ej circuit and analyzed it using ADS sftware. As gain increased t 17.2dB, the input pwer decreased 20dBm that is less than each stage. The prpsed pwer amplifier was designed fr minimum input pwer and maximum efficiency, s the input pwer f each pwer amplifier must have acceptable perfrmance. The 87% efficiency and 38.2dBm utput pwer was btained at the 2.9 t 3.5GHz frequency range fr the class-ej pwer amplifier. Matching circuit was dne based n the lad- and surcepull methds using lumped elements fr the best input and utput netwrks t increase drain efficiency and PAE. This new apprach was evaluated using a GaN CGH40010F transistr, because GaN substrates prduce high utput pwer in the prpsed circuit. This nvel methd was implemented using the class-e and class-j t achieve better perfrmance than previus wrks. The prpsed apprach will be able t use different substrates f transistrs and is designed by chsing classes having the greatest frequency bandwidth. REFERENCES [1] Z. Wang, G. Yang and F. Liu, "An Easily Implementable Structure fr Bradband High Efficiency Class-J Pwer Amplifier", IEEE Wrkshp n Electrnics, Cmputer and Applicatins, , [2] G. Liu, "Fully Integrated CMOS Pwer Amplifier", Ph.D. Thesis, Berkeley, Califrnia, 192, Dec [3] A. M. Eblabla, High Efficiency Class-F Pwer Amplifier Design, Wrld Academy f Science, Engineering and Technlgy, Issue 12, [4] A. G. d. M. Celh, "Mnlithic RF Class-E pwer amplifier n CMOS technlgies fr IEEE b/g applicatins", Technical Reprt N.?, Institute Superir Technician, Technical University f Lisbn, Octber [5] S. Rezaei, L. Belsttski and F. M. Ghannuchi, "1.6 GHz 3 GHz, 10W, 60% Efficiency Class-J PA fr Cgnitive Radi Applicatins", IEEE Cnference, 4, ,2013, pp [6] F. Rahmani, F. Razaghian and A. A. Kashaninia, High Pwer Tw- Stage Class-AB/J Pwer Amplifier with High Gain and Efficiency, Jurnal f Academic and Applied Studies (JAAS), Vl. 4(6), June 2014, pp [7] V. Carrubba, S. Marldt, M. Mußer, H. Walcher, M. Schlechtweg, R. Quay and O. Ambacher, "Dual-Band Class-ABJ AlGaN/GaN High Pwer Amplifier", IEEE Eurpean Micrwave Cnference (EuMC), Octber 2012, pp [8] S. Rezaei, L. Belsttski, F. M. Ghannuchi and P. Aflaki, "Integrated Design f a Class-J Pwer Amplifier", Micrwave Thery and Techniques IEEE Transactins, Vl.61, Issue 4, , April 2013, pp [9] S. Cripps, RF Pwer Amplifiers fr Wireless Cmmunicatins", 2nd ed. ISBN United States f America: Artech Huse, 1999,, pp

High Efficiency Frequency Tunable Inverse Class-E Amplifier in VHF Band

High Efficiency Frequency Tunable Inverse Class-E Amplifier in VHF Band Kumh Natinal Institute f Technlgy, 1 Yangh-Dng, Gumi, Gyungbuk, 730-701, Krea yungk@kumh.ac.kr Abstract This paper prpses the use