Implementation Of 12V To 330V Boost Converter With Closed Loop Control Using Push Pull Topology

Transcription

1 Implementatin Of 12V T 330V Bst Cnverter With Clsed Lp Cntrl Using Push Pull Tplgy Anande J.T 1, Odinya J.O.. 2, Yilwatda M.M. 3 1,2,3 Department f Electrical and Electrnics Engineering, Federal University f Agriculture, Makurdi, Nigeria. ABSTRACT There is a grwing need t reduce the size and weight f DC pwer supplies and at the same time imprve pwer supply efficiency, be it in the areas f electrnic pwer adapters r inverters. This paper presents a push pull tplgy f bst cnverter based n switched mde pwer supply. The cnverter utilizes an existing DC pwer supply capable f delivering 12V r a lead-acid battery f 12V as pwer input and transfrms it t 330V dc. This kind f utput vltage can be prcessed by inverter switches int an alternating AC signal. SG3525 pulse width mdulatr circuit cntrls the duty cycle f the MOSFET switches and implements clsd lp cntrl which reduces sensitivity f the system t parametric changes. The cmplete design is mdeled using prteus sftware and the utput verified practically. Keywrd: Push pull cnverter, pulse width mdulatr, inverter, SG3525, clsed lp cntrl 1.0 INTRODUCTION The push pull cnverter, a dc/dc transfrmer islated cnverter, is a tw frward cnverters derivative perating ut f phase[9] [4] [6]. A push-pull cnverter perates as an interleaved frward cnverter and is ideal fr higher pwer designs abve 200W[6]. The push-pull cnverter has all the benefits f a frward cnverter while exhibiting lwer input and utput ripple currents cmpared t the frward, thus having smaller filter cmpnents. The push-pull cnverter can perate ver the full duty cycle frm zer t ne.[5] [6] Duble-ended tplgies, such as push-pull, half-bridge and full-bridge, allw higher efficiencies and greater pwer densities when cmpared with cmmn single-ended tplgies including flyback and frward cnverters[1][3].therefre, duble-ended tplgies are increasingly ppular in many applicatins, especially telecm and autmtive. 2.0 PRINCIPLE OF OPERATION OF PUSH PULL CONVERTER The basic tplgy f Push Pull cnverter is shwn in figure1.the input DC vltage is switched thrugh the centertapped primary f the transfrmer by tw switches, Q1 and Q2, during alternate half cycles. These switches create pulsating vltage at the transfrmer primary winding. The transfrmer used prvides islatin between the input vltage surce V IN and the utput vltage V OUT. The switches Q1 and Q2 are driven by the cntrl circuit, such that bth switches shuld create equal and ppsite flux in the transfrmer cre. In the steady state f peratin, when the switch Q1 is ON fr the perid f T ON, the dt end f the windings becme psitive with respect t the nn-dt end. The dide D 5 becmes reverse-biased and the dide D 6 becmes frwardbiased. Thus, the dide D 6 prvides the path t the utput inductr current I L thrugh the transfrmer secndary N S2. As the input vltage V IN is applied t the transfrmer primary winding N P1, a reflected primary vltage appears in the transfrmer secndary. difference f vltages between the transfrmer secndary and utput vltage V OUT is applied t the inductr L in the frward directin

2 Fig. 1: Push Pull Cnverter Tplgy The inductr current I L rises linearly frm its initial t its peak value. During this TON perid while the input vltage is applied acrss the transfrmer primary N P1, the value f the magnetic flux density in the cre is changed frm its initial value f B 1 t B 2, At the end f the T ON perid, the switch Q 1 is turned OFF, and remains ff fr the rest f the switching perid T S. The switch Q 2 will be turned ON after half f the switching perid T S/2, Thus, during the T OFF perid, bth f the switches (Q 1 and Q 2 ) are OFF. When switch Q 1 is turned OFF, the bdy dide f the switch prvides the path fr the leakage energy stred in the transfrmer primary, and the utput rectifier dide D 5 becmes frward-biased. As the dide D 5 becmes frward-biased, it carries half f the inductr current thrugh the transfrmer secndary N S1, and half f the inductr current is carried by the dide D 6 thrugh the transfrmer secndary N S2. This results in equal and ppsite vltages applied t the transfrmer secndaries, assuming bth secndary windings N S1 and N S2 have an equal number f turns. Therefre, the net vltage applied acrss the secndary during the T OFF perid is zer, which keeps the flux density in the transfrmer cre cnstant t its final value B2. The utput vltage V OUT is applied t the inductr L in the reverse directin when bth switches are OFF. Thus, the inductr current I L decreases linearly frm its initial value. Table 1 shws the push pull parameters and specificatins Parameter Table 3: Push Pull Cnverter Specificatins value Input vltage nrminal Input vltage Mininum Input vltage maximum Output vltage maximum Output vltage minimum Output pwer Output current Input current nrminal Switching frequency 12V 9V 14V 330V 283V 100W 1A 8A 50kHz Switch Duty Cycle 45% 3.0 PUSH-PULL DESIGN CONSIDERATIONS

3 Vl-3 Issue The cnverter is supplied by a lw ESR capacitr C7 t lwer the battery bus ripple current and the EMI f the cnverter input. The cnverter s MOSFETs Q5 and Q6 are cntrlled by SG3525 current mde cntrller.because f the vltage surce character f the cnverter, the rectifier has t be a current type, which is why smthing chkes L 1 is used. Over vltage spikes acrss the rectifier dides, due t the dides reverse-recvery and transfrmer leakage, are clamped by RCD snubbers cnsisting f a R 6 - C 1 - D 6. C 4 Filters the utput vltage. Figure 23 shws the circuit implementatin D1 D3 D2 D4 D6 L1 B82422T1274J000 R6 100K C1 10p C4 220u OUT D E Rx R11 Q5 IRF540 SG1 R13 TR1 Ry C3 0.1u R1 1 C u 5 R2 7 6 R3 R SG3525 C5 470u C6 0.1u R4 R12 R14 Q6 IRF540 TRAN-2P3S C7 470u R8 Fig. 2: Circuit Implementatin f Push pull Cnverter Cntrlled By SG PUSH PULL CONVERTER DESIGN PROCEDURE Transfrmer T cme up with transfrmer design, the first task is t chse an apprpriate transfrmer cre. The cre size can be selected Based n manufacturer pwer-handling-capability cre tables. Subsequently, the maximum cre flux density travel ΔB is determined frm the cre manufacturer data sheet, then the apprximate number f turns can be calculated fr bth primary and secndary windings. Since the number f turns is usually an integer, the number is runded and the real flux density travel is calculated. If ΔB is belw a maximum limit with respect t the switching frequency (cre material dependent), winding turns and the crss-sectinal areas are calculated fr all respective windings Fr a 100W utput pwer cnsideratin, ETD44 cre can be selected. The parameters specificatin is as fllws: Cre factr, Effective vlume Effective lengthn, Effective area, Flux density travel = 400mT. Using faradays law f electrmagnetic inductin, the amunt f magnetic charge int the cre is given by (1) Where induced vltage, linkage flux in the cre, N number f turns, S Cre crss sectinal area, B flux density in the cre, Intergrating the induced vltage gives (2) Where is flux density travel. Since the induced vltage during the steady state peratin f the cnverter is cnstant and equal t input vltage, the magnetic charge in the cre is given by.t (3) Where is input vltage nrminal, is switching duty cycle, T is switching perid

4 Therefre, T calculate the number f primary turns, equatin (2) is rearranged t give Fr frward type cnverter, the turn rati f primary t secndary winding is given by (4) where is the duty cycle defined at maximum value f 98%, is the utput vltage taken at the maximum value f 330V, f 9V is the input vltage taken at a minimum value Therefre =37t MOSFET Switch selectin The vltage rating f MOSFETs in the design f pwer cnverters is based n vltage spikes that can pssibly ccur during MOSFET switch-ff. Of curse it als depends n the drain current, switching frequency, the input vltage, lad cnditins, and transfrmer prperties. Fr push-pull, a number f twice the input vltage is usually sufficient. IRF540 is a high speed switching N-channel MOSFET with,,. It is a chice in this design Rectifier dide selectin Rated dide vltage is given by the vltage wavefrm applied t the dide. As the rectifier is current-laded there is n natural clamp fr ver vltage spikes at the instant f a dide reverse recvery. That is why a suitable snubber has t be implemented in rder t cut-ff the excess energy that culd pssibly verheat the dide chip by internal avalanche. An ultra fast dide STTH10LCD06 is used with current rating f 10A, reverse vltage f 600V, and 100ns reverse recvery time. This dide is gd enugh fr 50kHz switching frequency Filter chkes A basic design cnsideratin when implementing a filter chke is t lk at the rectified current ripple. Fr an utput current level in the range f 1A, the relative ripple r i can be cnsidered in the range f 50 t 20%. Let r i equal 30% fr nminal cnditins. Then the filter chke inductance value is given by ( ) (5) where vltage acrss the chke during active cycle the time during active cycle current ripple nrminal input vltage transfrmer primary t secndary turn rati nrminal utput vltage maximum switching duty cycle relative current ripple nrminal utput current ( ) 7.7mH. Therefre a chke f 7.7mH inductance is wunded n a ferrite bead Push pull cntrl The cntrl f the utput vltage f the cnverter is made pssible by implementing a PWM cntrl scheme that switches the pwer MOSFETs ON and OFF at a desired frequency and changes the duty cycle f the cntrl signal based n the preset cnditins. SG3525 pulse width mdulatr cntrl circuit is implemented t achieve PWM cntrl

5 3.1.6 Frequency setting Frequency f peratin f SG3525 can be set by first chsing the value f the timing capacity and resistr C T and R T. Frm the C T, R T and R D curve f SG3525, the recmmended value fr C T is (1nf-0.2µf), R T is (2K-150K), R D is (10Ω-47Ω) C SS is (1µf. The switching frequency is given by (6) C T, R T Ω, R D. Therefre Output vltage cntrl The internal vltage reference f SG3525 is 5.1V n pin 16 n pin 2 (nn inverting terminal f the errr amplifier) equals V, therefre n pin 2 is 2.55V This vltage needs t be cmpared with the vltage n the inverting terminal f the errr amplifier. This is dne by using a vltage divider t feedback the utput vltage f the push-pull t pin 1 f SG3525. When vltage n the inverting pin (pin1) is greater than vltage n the nn inverting pin (pin2), duty cycle is decreased, similarly, when vltage n the nn inverting pin (pin2) is greater than vltage n the inverting pin (pin1), duty cycle is increased. Therefre, (44) 2.55, 2.55V(vltage n pin1), 330V(Nrnimal DC buck vltage at the cnverter utput) 4.0 RESULTS AND DISCUSSION The circuit was cnstructed and tested using digital strage scillscpe and vltmeter t bserve the gating signal as shwn in figure 3 and utput vltage f the cnverter as shwn in figure 4. Fig. 3: Cmplementary Gating Signals Generated By Sg

6 The SG3525 prduced a tw cmplementary gating signals that switches the tw MOSFET 180 ut f phase. Fig. 4: Cmplete Circuit Prttype Shwing DC Vltage Input And Output The circuit hwever respnded with the minimum input f 8.3Vdc when tested with variable DC vltage supply. The utput vltage was seen t be 328V. 5.0 CONCLUSION There are many tplgies that can be used t achieve DC t DC vltage cnvertin. Push pull cnverter tplgy is used in this research due t its simplicity and the ability t scale ut high thrughput. Frm the results generated, it is pssible t achieve higher vltage when the transfrmer turn rati is increased. 6.0 REFERENCES [1] A. Emadi, S. S. Williamsn, and A. Khaligh, Pwer electrnics intensive slutins fr advanced electric, hybrid electric, and fuel cell vehicular pwer systems, IEEE Trans. Pwer Electrn., vl. 21, n. 3, pp , May [2] A. Khaligh and Z. Li, Battery, ultracapacitr, fuel cell, and hybrid energy strage systems fr electric, hybrid electric, fuel cell, and plug-in hybrid electric vehicles: State f the art, IEEE Trans. n Vehicular Technlgy, vl. 59, n. 6, pp , Oct [3] Bb Bell (2006), Half-bridge tplgy finds applicatins in high density pwer cnverters. Available at accessed n 09 May, [4] Musumbiswal, Sidharthsabyasach A Study n Recent DC-DC Cnverters Internatinal Jurnal f Engineering Research and Applicatins (IJERA) ISSN: Vl. 2, Issue 6 Nv [5] PanXuewei A., naturally clamped zer current cmmuted sft-switching current fed Push pull DC/DC cnverter:analysis, Design, Experimental Results, IEEE Trans.Pwer Electrnics, [6] PanXuewei, Akshay K Rathre, Current-fed Sft-Switching Push-pull Frnt-end Cnverter Based Bidirectinal Inverter fr Residential Phtvltaic Pwer System, /TPEL , IEEE Transactins n Pwer Electrnics

7 [7] STMicrelectrnics (2000). Regulating Pulse Width Mdulatrs. SG3525A Data Sheet and Applicatin nte. Available at accessed n 15 June, 2017 [8] Swaminathan, B A nvel resnant transitin push-pull dc - dc cnverter Jurnal f the indian institute f science Vl 84, N 6 Nv-Dec 2004 [9] Thmas J. (ND). "Push Pull cnverter". Available at accessed n 25 June,