MX5A-12SA SMT Non-Isolated Power Module

Transcription

1 *RHS COMPLIANT Features Industry standard surface munt device RHS cmpliant* Output vltage prgrammable frm 0.75 V dc t 5.0 V dc via external resistr Up t 5 A utput current Up t 92 % efficiency Small size, lw prfile Cst-efficient pen frame design Lw utput ripple and nise High reliability Remte n/ff Output vercurrent prtectin (nn-latching) Cnstant switching frequency (300 khz) Wide perating temperature range MX5A-12SA SMT Nn-Islated Pwer Mdule Descriptin Burns MX5A-12SA is a nn-islated DC-DC cnverter ffering designers a cst and space-efficient slutin with standard features such as remte n/ff, precisely regulated prgrammable utput vltage and vercurrent and vertemperature prtectin. These mdules deliver up t 5 A f utput current with lad efficiency f 92 % at 5 V utput. Hw t Order M X 5A - 12 S A Cnfiguratin M = Surface Munt Device Internal Identifier Output Current (Amps) Input Vltage (V) Outputs S = Single (V) A = Adjustable Fixed utput vltage parts and ptinal features available; cntact factry. Abslute Maximum Ratings Stress in excess f abslute maximum ratings may cause permanent damage t the device. Device reliability may be affected if expsed t abslute maximum ratings fr extended time perids. Characteristic Min. Max. Units Ntes & Cnditins Cntinuus Input Vltage V dc Operating Temperature Range C See Thermal Cnsideratins sectin Strage Temperature C Electrical Specificatins Unless therwise specified, specificatins apply ver all input vltage, resistive lad and temperature cnditins. Characteristic Min. Nm. Max. Units Ntes & Cnditins Operating Input Vltage V dc Maximum Input Current A dc Over V in range, I max, V ut = 5 V dc Input N Lad Current V in = 12 V dc, I = 0 A, md. enabled, 26 ma -V ut = 0.75 V dc 70 ma -V ut = 5.0 V dc Input Stand-by Current 1.6 ma V in = 5.0 V dc, mdule disabled Inrush Transient 0.4 A 2 s Input Reflected Ripple Current 40 map-p Input Ripple Rejectin 30 db 120 Hz Cautin: The pwer mdules are nt internally fused. An external input line fast-blw fuse with a maximum rating f 6 A is required. See the Safety Cnsideratins sectin f this data sheet. Applicatins Intermediate Bus architecture Distributed pwer applicatins Wrkstatins and servers Telecm equipment Enterprise netwrks including LANs/WANs Latest generatin ICs (DSP, FPGA, ASIC) and micrprcessr pwered applicatins *RHS Directive 2002/95/EC Jan including Annex. 1

2 Electrical Specificatins (Cntinued) Characteristic Min. Nm. Max. Units Ntes & Cnditins Setpint Accuracy % V,set V in min, I max, T A = 25 C Tlerance % V,set Over all rated in ut vltage, lad and temperature cnditins Vltage Adjustment Range V dc Line Regulatin 0.3 % V,set Lad Regulatin 0.3 % V,set Temperature Regulatin 0.4 % V,set Output Current A dc Output Current Limit Inceptin (Hiccup Mde) 200 % I max Output Shrt Circuit Current 2 A dc V 250 mv Hiccup Mde Output Ripple and Nise Vltage 1 µf ceramic/10 µf tantalum capacitrs RMS mvrms 5 Hz t 20 MHz bandwidth Peak-t-Peak mvpk-pk External Capacitance - ESR 1 mω 1000 µf - ESR 10 mω 3000 µf Efficiency 81.5 % V,set = 1.2 V dc (V in = 5 V dc, T A = 25 C, Full Lad) 84.0 % V,set = 1.5 V dc 85.0 % V,set = 1.8 V dc 87.0 % V,set = 2.5 V dc 89.0 % V,set = 3.3 V dc 92.0 % V,set = 5.0 V dc Switching Frequency 300 khz Dynamic Lad Respnse 1 µf ceramic/10 µf tantalum capacitr 2.5 A t 5 A; 5 A t 2.5 A; 200 mv Peak Deviatin ( i/ t = 2.5 A/µs; 25 C) 25 µs Settling Time (V <10 % peak deviatin) 2 x 150 µf plymer capacitrs 2.5 A t 5 A; 5 A t 2.5 A; 75 mv Peak Deviatin ( i/ t = 2.5 A/µs; 25 C) 50 µs Settling Time (V <10 % peak deviatin) General Specificatins Characteristic Nm. Units Ntes & Cnditins Calculated MTBF 10,000,000 hurs Weight 2.2 g (0.08) (z.) 2

3 Feature Specificatins Characteristic Min. Nm. Max. Units Ntes & Cnditins Remte Enable Open = On (Lgic Lw) 0.4 V dc 10 µa max. Lw = Off (Lgic High) > V dc 1 ma max. Turn-On Delay and Rise Times Case 1: On/Off Lw V in Applied 2.5 msec Case 2: V in Applied, then On/Off Set Lw 2.5 msec Case 3: Rise 3.0 msec (10 %-90 % f V setting) Oversht 1 % V, set I max, V in =5.5, T A =25 C Overtemperature Prtectin 135 C See Thermal Cnsideratin sectin Input Undervltage Lckut -Turn-n Threshld 8.2 V -Turn-ff Threshld 8.0 V 3

4 Characteristic Curves The curves prvided belw are typical characteristics fr the MX5A-12SA mdules at 25 C. Fr any specific test cnfiguratins r any specific test requests, please cntact Burns. Efficiency (%) Vin=14 V Vin=12 V Vin=10 V Efficiency (%) Vin=14 V Vin=12 V Vin=10 V Output Current (A dc) Fig. 1 Efficiency vs. Output Current (V ut = 1.2 V dc ) Output Current (A dc) Fig. 4 Efficiency vs. Output Current (V ut = 2.5 V dc ) Efficiency (%) Vin=14 V Vin=12 V Vin=10 V Efficiency (%) Vin=14 V Vin=12 V Vin=10 V Output Current (A dc) Fig. 2 Efficiency vs. Output Current (V ut = 1.5 V dc ) Output Current (A dc) Fig. 5 Efficiency vs. Output Current (V ut = 3.3 V dc ) Efficiency (%) Vin=14 V Vin=12 V Vin=10 V Output Current (A dc) Fig. 3 Efficiency vs. Output Current (V ut = 1.8 V dc ) Efficiency (%) Vin=14 V 75.0 Vin=12 V Vin=10 V Output Current (A dc) Fig. 6 Efficiency vs. Output Current (V ut = 5.0 V dc ) 4

5 Characteristic Curves (Cntinued) Input Current (A)/ (Vdc) Iin, Adc 0.00 V, Vdc Input Vltage (V dc ) Fig. 7 Input Vltage vs. I and V (V = 2.5 V dc, I = 6.0 A) V (100 mv/div) Output Current I (1.3 A/div) : 100 mvlt 5 µs Output Current (1.3 A/Div): 2 Vlt 5 µs Time (5 µs/div) Fig. 10 Transient Respnse A - 5 A Step (V = 3.3 V dc) V (10 mv/div) V (100 mv/div) Full Lad: 10 mvlt 2.5 µs N Lad: 10 mvlt 2.5 µs Half Lad: 10 mvlt 2.5 µs Time (2.5 µs/div) Fig. 8 Typical Output Ripple and Nise (V in = 12.0 V, V = 0.75 V, I = 5.0 A) Output Current I (1.3 A/div) : 100 mvlt 5 µs Output Current (1.3 A/Div): 2 Vlt 5 µs Time (5 µs/div) Fig. 11 Transient Respnse - 5 A A Step (V = 3.3 V dc) V (50 mv/div) V (100 mv/div) Output Current I (0.9 A/div) Full Lad: 50 mvlt 2.5 µs : 100 mvlt 10 µs N Lad: 50 mvlt 2.5 µs Half Lad: 50 mvlt 2.5 µs Output Current (0.9 A/Div): 2 Vlt 10 µs Time (2.5 µs/div) Time (10 µs/div) Fig. 9 Typical Output Ripple and Nise (V in = 12.0 V, V = 3.3 V, I = 5.0 A) Fig. 12 Transient Respnse A - 5 A Step (V in = 12.0 V, V = 12 V dc, C ext = 2x100 µf Plymer Capacitrs) 5

6 Characteristic Curves (Cntinued) Output Current I (0.9 A/div) V (100 mv/div)????? : 100 mvlt 10 µs Output Current (0.9 A/Div): 2 Vlt 10 µs Time (5 µs/div) Fig. 13 Transient Respnse - 5 A A Step (V in= 12 V dc,v = 3.3 V dc, C ext = 2x100 µf Plymer Caps)??? : 1 Vlt 1 ms Input Vltage: 5 Vlt 1 ms?? : 1 Vlt 1 ms On/Off Vltage: 5 Vlt 1 ms Time (1 ms/div) Fig. 14 Typical Start-up using Psitive Remte On/Off (V in = 12 V dc, V = 3.3 V dc, I = 5 A) On/Off Vltage V n/ff (5 V/div) On/Off Vltage V n/ff (5 V/div) Input Vltage V in (5 V/div)??? V (1 V/div) Time (1 ms/div) Fig. 16 Typical Start-up with Applicatin f V in (V in = 12 V dc, V = 3.3 V dc, I = 5 A) On/Off Vltage V n/ff (5 V/div) V (1 V/div) V (0.5 V/div)?? : 500 mvlt 1 ms On/Off Vltage: 5 Vlt 1 ms Time (1 ms/div) Fig. 17 Typical Start-up using Remte On/Off with Prebias (V in = 12 V dc, V = 1.8 V dc, I = 1 A, V bias = 1 V dc ) V (1 V/div)?? : 1 Vlt 1 ms On/Off Vltage: 5 Vlts 1 ms Time (1 ms/div) Fig. 15 Typical Start-up using Negative Remte On/Off with Lw-ESR External Capacitrs (10x100 µf Plymer) (V in = 12 V dc, V = 3.3 V dc, I = 5.0 A, C = 1000 µf) Output Current I (4 A/div)?? Output Current (4 A/div): 20 mvlt 25 ms Time (5 ms/div) Fig. 18 Output Shrt Circuit Current (V in = 12.0 V dc, V = 0.75 V dc ) 6

7 Characteristic Curves (Cntinued) 7 Output Current (A) LFM 0 LFM 100 LFM Ambient Temperature ( C) Fig. 19 Derating Output Current vs. Lcal Ambient Temp. and Airflw (V in = 12.0 V dc, V = 0.75 V dc ) Output Current (A) LFM 200 LFM 100 LFM Ambient Temperature ( C) Fig. 21 Derating Output Current vs. Lcal Ambient Temp. and Airflw (V in = 12.0 V dc, V = 3.3 V dc ) 85 Output Current (A) LFM 0 LFM 100 LFM Output Current (A) LFM 200 LFM 100 LFM Ambient Temperature ( C) Fig. 20 Derating Output Current vs. Lcal Ambient Temp. and Airflw (V in = 12.0 V dc, V = 1.8 V dc ) Ambient Temperature ( C) Fig. 22 Derating Output Current vs. Lcal Ambient Temp. and Airflw (V in = 12.0 V dc, V = 5.0 V dc ) 85 7

8 Operating Infrmatin Remte On/Off The MX5A-12SA cmes standard with Active LOW with Negative On/Off lgic, i.e., OPEN r LOW (< 0.4 V) will turn ON the device. T turn the device OFF, increase the vltage level abve 2.4 V, placing the part int lw dissipatin sleep mde. The signal level f the On/Off pin input is defined with respect t grund. MX5A-12SA Fig. 23 Circuit Cnfiguratin fr using Negative Lgic On/Off Input Cnsideratins The input must have a stable lw impedance AC surce fr ptimum perfrmance. This can be accmplished with external ceramic capacitrs, tantalum capacitrs and/r plymer capacitrs. Using lw impedance tantalum capacitrs requires abut 20 µf per Amp and an ESR f 250 mω per Amp f utput current. Fr a 5 A cnverter, tantalum capacitrs with a cmbined value f 100 µf and 50 mω wuld be adequate. This can be implemented with (2) 47 µf tantalum capacitrs with an ESR f 100 mω. Ceramic capacitrs are als recmmended t reduce high frequency ripple n the input. Output Cnsideratins T maintain the specified utput ripple and transient respnse, external capacitrs must be used. An external 1 µf ceramic capacitr in parallel with a 10 µf lw ESR tantalum capacitr will usually meet the specified perfrmance. Imprved perfrmance can be achieved by using mre capacitance. Lw ESR plymer capacitrs may als be used. Tw 100 µf, 9 mω r lwer ESR capacitrs are recmmended. Safety Infrmatin In rder t cmply with safety requirements the user must prvide a fuse in the unearthed input line. This is t prevent earth being discnnected in the event f a failure. The cnverter must be installed as per guidelines utlined by the varius safety apprvals if safety agency apprval is required fr the verall system. Overtemperature Prtectin The device will shut dwn if it becmes t ht (typically 135 C at cntrller IC). Once the cnverter cls, it autmatically restarts. This feature des nt guarantee the cnverter wn t be damaged by temperatures abve its rating. Overcurrent Prtectin The device has an internally set utput current limit t prtect it frm verlads, placing the unit in hiccup mde. Once the verlad is remved the cnverter autmatically resumes nrmal peratin. N user adjustments are available. An external fuse in series with the input vltage is als required fr cmplete verlad prtectin. Input Undervltage Lckut The device peratin is disabled if the input vltage drps belw the specified input range. Once the input returns t the specified range peratin autmatically resumes. N user adjustments are available. 8

9 Operating Infrmatin (Cntinued) Setting The utput vltage can be prgrammed t any vltage between 0.75 Vdc and 5.5 Vdc by cnnecting a single resistr between the trim pin and the GND pin f the mdule, as shwn in Fig. 24 belw. If left pen circuit the utput vltage will default t 0.75 Vdc. The crrect Rtrim value fr a specific vltage can be calculated using the fllwing equatin: Rtrim = [10.5/(V )-1] KΩ VIN (+) VO (+) Fr example, t set the MX5A-12SA t 3.3 V the fllwing Rtrim resistr must be used: ON/OFF TRIM LOAD Rtrim = [10.5/( )-1] KΩ Rtrim = kω, The clsest standard 1 % E96 value is 3.09 kω. Table 1 prvides the Rtrim values required fr sme cmmn utput vltage set pints. MX5A-12SA Rtrim Values V (V) Rtrim (kω) 1 % Value 0.75 Open Open Table 1 MX5A-12SA Vtrim Values V (V) Vtrim (V) 0.75 Open GND Rtrim Fig. 24 Circuit Cnfiguratin t Prgram Output Vltage using an External Resistr The utput vltage f the device can als be set by applying a vltage between the TRIM and GND pins. The Vtrim equatin can be written as fllws: Vtrim = ( x{v )) T set V = 3.3 V, the Vtrim required wuld therefre be V. Table 2 belw prvides the Vtrim values required fr sme cmmn utput vltage set pints. Table 2 9

10 Operating Infrmatin (Cntinued) Vltage Margining Output vltage margining can be implemented as fllws: 1) Trim-up: Cnnect a resistr, Rm-up, frm the Trim pin t the grund pin fr adjusting the vltage upwards, and 2) Trim-dwn: Cnnect a resistr, Rm-dwn, frm the Trim pin t the utput pin fr adjusting the vltage dwnwards. Please cnsult yur lcal Burns Field Applicatins Engineer fr mre details and the calculatin f the required resistr values. Vin On/Off V Trim V R margin-dwn Q2 R trim R margin-up Q1 Thermal Cnsideratins COM Fig. 25 Circuit Cnfiguratin fr Margining Sufficient cling must always be cnsidered t ensure reliable peratin, as these devices perate in a variety f thermal envirnments. Factrs such as ambient temperature, airflw, pwer dissipatin and reliability must be taken int cnsideratin. The data presented in Figures 19 t 22 is based n physical test results taken in a wind tunnel test. The test set-up is shwn in Figure 27. The thermal reference pints are (1) T ref1 = temp at dual Msfet, as shwn in Figure 26, and (2) T ref2 = temp at cntrller IC. Fr reliable peratin, neither T ref1 r T ref2 shuld exceed 115 C. Air Flw T ref1 n Air Flw 8.1 (0.32) WIND TUNNEL Airflw and ambient temp sensr prbes lcatin 76.2 (3.0) C2 C3 L1 Q1 UNIT UNDER TEST C1 PCB Fig. 26 T ref1 Temperature Measurement Lcatin 25.4 (1.0) Fig. 27 Thermal Test Set-up 10

11 Prduct Dimensins 4.06 (0.160) 4.83 (0.190) BOTTOM VIEW 20.3 (0.80) 4.06 (0.160) 4.57 (0.180) DIMENSIONS: MM (INCHES) SIDE VIEW 5.84 (0.230) MAX (0.219) REF (0.350) GND TRIM VOUT (0.450) 8.64 (0.340) TOLERANCES: 0.5 DECIMAL.X ± (0.02) DECIMAL.XX ± 0.25 (0.010) VIN ON/OFF L1 INDUCTOR 1.47 (0.058) (0.06) (0.090) 1.3 (0.05) 1.57 (0.062) Fig. 28 Prduct Dimensins Cplanarity The MX5A-12SA device has a maximum cplanarity f 100 µm (apprx ), as defined by JESD22-B108. Pin Plating Cmpsitin Tin (Sn) plating ver nickel (Ni). Recmmended Pad Layut 4.57 (0.180) 4.06 (0.160) (0.690) 4.06 (0.160) 4.83 (0.190) VOUT TRIM GND 8.64 (0.340) ON/OFF 0.25 (0.010) VIN 8.89 (0.350) DIMENSIONS: MM (INCHES) 1.5 (0.06) 1.3 (0.05) RECOMMENDED PAD SIZE: X MIN. (0.120) (0.095) X MAX. (0.135) (0.110) Fig. 29 Recmmended Pad Layut 11

12 Use in Manufacturing Envirnment Pick and Place Infrmatin Burns SMT devices, packaged n tape and reel, are designed (lw mass) fr autmated assembly using standard SMT pick and place equipment. The centrally lcated inductr prvides the flat surface area t be used fr cmpnent pick up. Variables such as nzzle style, nzzle size, handling speed, and placement pressure need t be ptimized fr best results (0.450) 6.22 (0.245) 9.65 (0.380) 20.3 (0.80) DIMENSIONS: MM (INCHES) Fig. 30 Pick and Place Lcatin Packaging Infrmatin Devices cme in 44 mm tape and reel, as per EIA ±0.10 (.016 ±.004) 5.90 (.232) A 4.00 ± 0.10 (.157 ±.004) 2.00 ± 0.10 (.079 ±.004) DIA /-0.00 ( /-0.00) 1.75 ± 0.10 (.069 ±.004) ± 0.10 (.795 ±.004) ± ±.004) Reel Dimensins: (.811) DIA /-0.00 ( /-0.00) B B ± 0.10 (1.591 ±.004) Outside Diameter: Inside Diameter: 44.0 Width: (1.73) (13.00) (7.00) SECTION B-B A ± 0.10 (.630 ±.004) DIMENSIONS: MM (INCHES) (.461) SECTION A-A Fig. 31 Packaging Tape Detail PCB Layut fr SMT Devices Use a slder mask defined pad design. See specific datasheet fr recmmended minimum and maximum pad size. Intercnnectin t internal pwer planes is typically required. Via-in-pad design shuld be avided in the SMT pads. Slder mask shuld be used t eliminate slder wicking int the vias. Lw resistance and lw inductance PCB layut traces shuld be used where pssible, particularly n the utput side. A lw impedance track between the input grund and utput grund is very imprtant t achieve high efficiencies. 12

13 Use in Manufacturing Envirnment (Cntinued) Sldering Requirements Burns recmmends the fllwing temperature prfile fr use n tin lead slder (Sn-Pb Eutectic) and lead free slder. Fr lead free slder, the maximum temperature during the munting prcess shuld nt exceed 245 C. Sufficient time must be allwed t fuse the plating n the cnnectin t ensure a reliable slder jint. Hwever, the time abve 230 C shuld nt exceed 60 secnds. 300 Slder Reflw Prfile Temperature ( C) Preheat Zne <2.5 C/sec. Peak Temp. (Pb-Free Slder) 245 C Saking Zne (2 min. max.) sec typical C/sec. Preheating Zne (2-4 min. max.) Time (Secnds) Reflw Zne (90 sec. max.) sec. typ C/sec. Peak Temp. (Pb Slder) C Cl Dwn Zne Fig. 32 Suggested Reflw Prfile Water Washing A nn-clean slder paste system shuld be used fr slder attach nt applicatin bards. The parts are suitable fr water washing applicatins. Hwever, the user must ensure that the drying prcess is sufficient t remve all water frm the mdule after washing and that the mdule is never pwered up prir t the mdule being fully dried. Inspectin/Rewrk Cnventinal techniques may be emplyed when replacing a unit in the applicatin. Using a precisin dispenser r a suitable ministencil, a suitable vlume f slder paste shuld be applied t the cleaned pads. Reflw can be achieved by standard SMT rewrk techniques such as IR r techniques develped fr BGA cmpnents. ESD Requirements Burns manufactures all mdels in an ESD cntrlled envirnment and all prduct is supplied in cnductive packaging t prevent ESD damage frm ccurring befre r during shipping. All prducts must be unpacked and handled using apprved ESD cntrl prcedures. Failure t d s may affect the lifetime f the cnverter. Strage The X & XT Series have an MSL rating f 1 per IPC/JEDEC J-STD-033A. Asia-Pacific: Tel: Fax: Eurpe: Tel: Fax: The Americas: Tel: Fax: LONGFORM REV. B 08/06 13

14 Muser Electrnics Authrized Distributr Click t View Pricing, Inventry, Delivery & Lifecycle Infrmatin: Burns: MX5A-12SA