A Basis for LDO and It s Thermal Design

Transcription

1 A Basis fr LDO and It s Thermal Design Hawk Chen Intrductin The AIC LDO family device, a 3-terminal regulatr, can be easily used with all prtectin features that are expected in high perfrmance vltage regulatin applicatin. These devices prvide shrt-circuit prtectin, thermal shutdwn prtectin and internal current limit prtectin against any verlad cnditin that wuld create ver heating junctin temperature. (1)Current Limit Prtectin Like ther pwer regulatin IC, the AIC LDO family has safety prtectin area. The current limit prtectin wrks while utputting heavylading current and keeps the utput current within a safe perating scpe. The utput vltage decreases t a lwer vltage level at the same time. The AIC LDO family prtectin functin is designed t set up utput current limit when ver-current happen and the dwnstream devices can be prtected frm being damaged. Upper: utput vltage (1V/DIV) Lwer: utput current (2A/DIV) (2) Prtectin Dides During nrmal peratin, the AIC LDO device needs n prtectin dide. The internal dide between input and utput pins can handle micrsecnd surge current. Even with large utput capacitance, it is very difficult t get thse values f surge current in nrmal peratin. The damage will nt ccur, unless the high value utput capacitrs and the input pin are shrted t grund instantaneusly. A crwbar circuit at the input f the LDO device can generate thse kinds f current and a dide frm utput-t-input is then recmmended. Nrmal pwer supply cycling r even plugging and unplugging in the system will nt generate sufficient large current t damage device (see Figure 2). D1 Functin blck diagram AIC1086 Tplgy + C IN + C OUT Figure 2 AIC1086 prtectin dides diagram (3) Ripple Rejectin Figure 1 AIC1086 current limit test It is recmmended t use the AIC LDO family device in the applicatin required imprving May

2 ripple rejectin. By cnnecting a bypass capacitr frm the ADJ pin t the grund can reduce the utput vltage ripple significantly (see Figure3). The bypass capacitr prevents utput ripple frm being amplified as the utput vltage r lading current increases. The functin is defined by: 1 R1 2π Fr CADJ Here the Fr is the utput ripple frequency and the CADJ is a bypass capacitr (Fr figure 4). The ripple rejectin capability intensifies as utput capacitr increases, the utput ripple will then be reduced. Fr mre infrmatin, please refer t AIC LDO family datasheet. + C IN D1 Functin blck diagram C ADJ R1 + AIC1086 Tplgy C OUT Figure 3 AIC1086 and bypass capacitr (C ADJ ) Ripple Rejectin (db) (AIC1722D - 33) B : C OUT =10F, I L =1Ma C : C OUT =1F, I L =1mA D : C OUT =1F, I L =40mA =5V DC + 1Vp-p Frequency (KHz) Figure 4 AIC 1722D-33 frequency and ripple rejectin (4) Lad Regulatin Being a three-terminal device, the AIC LDO family is unable t prvide true remte lad sensing. The resistance f the wire cnnecting the regulatr t the lad will limit the lad regulatin. Please refer t the datasheet fr the detail measurement. (a) Figure 5: When the fixed type regulatr is used, the lad shuld be cnnected t the utput terminal n the psitive side and the grund terminal n the negative side. The utput vltage is measured as the fllwing equatin: VL Vut I(RS1 RS2) (b) Figure 6: When the adjustable type regulatr is used, the lad shuld be cnnected t the utput terminal n the psitive side and the grund terminal n the negative side. The utput vltage is measured as the fllwing equatin: V L V REF R1 R1 I (RS1 RS2) (c) Lad regulatin is the circuit s ability t maintain the specified utput vltage level under different lad cnditins, which is defined as: V I OUT O Figure 7 shws a PMOS vltage regulatr. The rati f utput vltage variatin t the given lad current variatin ( /I) under cnstant input vltage Vi can be calculated as fllw. Here, Q1 is the series pass element, and is the current gain f Q1. Gm is the transcnductance f the errr amplifier at its perating pint. Assume that there is a small utput current change (I), The change f utput current causes the utput vltage t change was calculated as: V ut I R EQ (R EQ (R1 ) R L R L ) 2

3 Where R EQ is the equivalent utput resistr.the change f sensed vltage multiplied by Gm f the errr amplifier input difference and f the PMOS current gain (Figure7) must be large enugh t achieve the specified change f utput current. Thus, Q1 () I G M - + ERROR AMP. R1 RL I O GMV GM( ) V R1 OUT V Reference Then, the lad regulatr is btained frm abve equatin. VOUT 1 R1 I Gm Since lad regulatin is a steady-state parameter, all frequency cmpnents are neglected. The lad regulatin is limited by the pen lp current gain f the system. As nted frm the abve equatin, increasing dc pen lp current gain imprved lad regulatin. VIN VOUT RS1 RS2 RL Figure 5 AIC LDO Fixed Regulatr VIN VOUT R1 RS1 RL RS2 Figure 6 AIC LDO Adjustable regulatr Figure 7 PMOS vltage regulatr (5) Quiescent Current r Grund Current Quiescent current r grund current is the difference between input and utput current fr AIC LDO family. Minimum quiescent current is necessary t maximize current efficiency. It is defined: I q I I i Quiescent current cnsists f bias current and drive current f the series pass element, which des nt cntribute t utput pwer. The series pass element, functin diagram, ambient temperature, and etc, determine the value f quiescent current. Linear drput vltage usually emply biplar r MOS transistrs as series pass elements. (a) Figure 8 :The cllectr current f biplar transistrs is defined by: I C I B Where I C is the cllectr current f biplar transistr, is the cmmn-emitter current gain f biplar transistr and I B is the base current f biplar transistr. The base current f biplar transistr is prprtinal t the cllectr current. When the utput current increases, the base current increases, t. Since the base current cntributes t quiescent current, biplar transistrs have higher quiescent current than MOS transistrs. At the same time, during the drput regin the quiescent current will increase, because f the additinal parasitic current path between the emitter and the base f biplar transistrs, which is caused by a lwer base vltage than that f the utput vltage. 3

4 (b) Figure 9 the drain surce current f MOS transistrs is defined by: I D I K(V D GS K(V DS T 2 V ) (1 V 2 T V ) DS )( V DS 0) K is a MOS transistr cnductivity parameter Vgs is the gate t surce vltage Vt is the MOS threshld vltage The drain current is a functin f the gate t surce vltage, nt the gate current. Figure 10 and figure 11 shw the grund current with respect t input vltage and temperature. Grund Current (A) Grund Current vs. Input Vltage IC I B3 I B2 I B1 V CC Input Vltage (V) Figure 10 AIC1722 input and grund current characteristics Figure 8 transistrs I-V characteristics f biplar Grund Current vs. Temperature ID K V GS4 V GS3 V GS2 Grund Current (A) I L =300mA I L =150mA I L =0.1mA V GS1 V DS Figure 9 I-V characteristic f MOS transistrs Fr biplar transistrs, the quiescent current increases prprtinally with the utput current because the series pass element is a currentdriven device. Fr MOS transistrs, the quiescent current has a near cnstant value with respect t the lad current since the device is vltage-driven. The nly things that cntribute t the quiescent current fr MOS transistrs are the biasing currents f band-gap, sampling resistr, and errr amplifier. In mst applicatins where pwer cnsumptin is critical r where small bias current is requested in cmparisn with the utput current, an LDO vltage regulatr using MOS transistrs is an essential chice Temperature (C) Figure 11 AIC 1722 temperature and grund current characteristics (6) Thermal Cnsideratins The AIC LDO family has internal pwer and thermal-limiting circuitry, which is designed t prtect the device against verlad cnditins. Fr cntinuus nrmal lad cnditins, hwever, maximum ratings f junctin temperature must nt be exceeded. It is imprtant t pay mre attentin t all surces f thermal resistance frm junctin t ambient. This includes junctin-t-case, case-t-heat sink interface, and heat sink resistance itself

5 We take the fllwing cnditin as an example f AIC (max cntinuus)=5v, =3.3V, I OUT =1A, T A =70ºC HEAT SINK =1ºC/W, CASE-TO-HEATSINK =0.2ºC/W fr TO-220 package with thermal cmpund. dissipatin under these cnditins can be calculated : P D =( - )(I OUT )=1.7W Junctin temperature will be equal t: T J =T A +P D ( HEAT SINK + CASE-TO-HEAT SINK + JC ) Fr the perating junctin temperature range: T J =70ºC+1.7W(1ºC/W+0.2ºC/W+0.7ºC/W) =73.23ºC 73.23ºC<125ºC=T JMAX (Operating Junctin Temperature Range) Fr the strage temperature range: T J =70ºC +1.7W (1ºC / W+0.2ºC / +3ºC /W) =77.14ºC 77.14ºC<150ºC=T JMAX (Strage Temperature Range) In the abve tw cases, the junctin temperature are lwer than the maximum rating, and this ensure a reliable peratin. (7) Efficiency The quiescent r grund current and input/utput vltage are with respect t the efficiency f a LDO regulatr input/utput vltage with fllwing equatin: E I IV 100% I V g In rder t achieve a higher efficiency fr LDO i regulatr, The drput vltage and quiescent current must be reduced. In additin, the drput vltage between input and utput must be minimized since the pwer dissipatin f LDO regulatrs affects t the efficiency significantly. dissipatin = (Vi V) I Fr example f AIC1722: Input vltage is 5V vltage is 3.3V current is 300mA Grund (max) current is 80A E 300mA % 300mA 88µ8 5 66% (8) Layut Nte Accrding t the fllwing parameter, we can achieve the maximum allwable Temperature Rise, (T R ) T R = T J (max)- T A (max) where T J (max) is the maximum allwable junctin temperature (125ºC ), and T A (max) is the maximum ambient temperature suitable in the applicatin. Use the calculated values fr T R and P D, the maximum allwable value f the junctin-t-ambient thermal resistance ( JA ) can be calculated: JA =T R /P D If the maximum allwable value fr JA is achieved t be 133ºC /W fr SOT-223 package r 74ºC /W fr TO-220 package r 102ºC /W fr TO-263 package, n heatsink is needed since the package will dissipate heat t satisfy these requirements. If the calculated value fr JA falls belw these limits, extra heatsink fr LDO device is required. TABLE 1. JA Different Heatsink Area Table 1 shws the values f the JA f SOT-223 and TO-263 fr different heatsink area. The 5

6 cpper patterns that we used t measure these JA are shwn as belw. Layut Cpper Area Tp Side (in 2 )* Bttm Side (in 2 )* Thermal Resistance ( JA C/W) TO-263 ( JA C/W) SOT TABLE 2. AIC LDO Series Temperature table ()Since IC s temperature can rise up, these peratin cnditins are nt recmmended. Test IC TYPE:AIC CZL(TO-92) withut heat sink : dissipatin 0.5W 0.7W() Lad current 298mA 417mA vltage :3.322V DC vltage Package 3.302V 70ºC 3.307V 81ºC Test IC TYPE:AIC CZL(SOT-89)IC stick n PCB dissipatin 0.5W 0.6W() Lad current 290mA 348mA vltage:3.278v DC vltage Package 3.305V 70ºC 3.299V 80ºC 6

7 Test IC TYPE:AIC CE(TO-252)IC stick n PCB dissipatin 0.5W 0.9W 1W() N lad : Lad current 300mA 538mA 598mA vltage:3.328v DC vltage Package 3.321V 40ºC 3.313V 50ºC 3.316V 57ºC Test IC TYPE:AIC CF(TO-251) withut heat sink 0.9W 1W 1.1W() Lad Current 524mA 582mA 641mA Vltage 3.294V 3.295V 3.296V Package 63ºC 66ºC 73ºC vltage:3.284v DC Junctin 80ºC 87ºC 96ºC Test IC TYPE:AIC1084CT(TO-220) withut heat sink 1W 3W() 6W() Lad Current 600mA 1.802A 3.604A Vltage 3.331V 3.311V 3.291V Package 55ºC 99ºC 127ºC vltage:3.335v DC Junctin 66ºC 124ºC 176ºC Test IC TYPE:AIC1084CT(TO-220) with heat sink 1W 3W 6W() Lad Current 600mA 1.802A 3.604A Input vltage: 5V Vltage 3.333V 3.322V 3.219V DC Package 47ºC 61ºC 88ºC vltage:3.335v DC Junctin 54ºC 85ºC 113ºC Test IC TYPE:AIC1084CT(TO-220) IC stick n PCB Ta : 28ºC 1W 3W 6W() Lad Current 600mA 1.802A 3.604A Vltage 3.333V 3.324V 3.197V Package 41ºC 66ºC 93ºC vltage:3.335v DC Junctin 46ºC 75ºC 110ºC 7

8 Test IC TYPE:AIC1084CM(TO-263) IC stick n PCB 1W 3W 6W() 7W() Lad Current 594mA 1.784A 3.567A 4.162A Vltage 3.314V 3.296V 3.242V 3.077V Input vltage : 5V DC Package 40ºC 74ºC 88ºC 100ºC vltage:3.318v DC Junctin 44ºC 90ºC 108ºC 120ºC Test IC TYPE:AIC1085CT(TO-220) withut heat sink 1W 3W() 6W() Lad Current 556mA 1.667A 3.333A Vltage 3.193V 3.173V 3.285V Package 56ºC 90ºC 130ºC vltage:3.200v DC Junctin 76ºC 146ºC 193ºC Test IC TYPE:AIC1085CT(TO-220) with heat sink 1W 3W 6W() Ta : 28ºC Lad Current 556mA 1.667A 3.333A Vltage 3.192V 3.179V 3.176V Package 40ºC 56ºC 95ºC vltage:3.200v DC Junctin 50ºC 80ºC 138ºC Test IC TYPE:AIC1085CT(TO-220) IC stick n PCB 1W 3W 6W() Ta : 28 Lad Current 556mA 1.667A 3.333A Vltage 3.199V 3.192V 3.174V Package 45ºC 65ºC 100ºC vltage:3.200v DC Junctin 54ºC 85ºC 132ºC Test IC TYPE:AIC1085CM(TO-263) IC stick n PCB Ta : 28ºC 1W 3W 6W() Lad Current 595mA 1.788A 3.576A Vltage 3.321V 3.310V 3.192V Package 40ºC 64ºC 80ºC vltage:3.322v DC Junctin 47ºC 88ºC 100ºC 8

9 Test IC TYPE:AIC1117CE(TO-252) IC stick n PCB Ta : 28ºC 1W 1.5W 2W() Lad Current 561mA 841mA 1.122A Input vltage : 5V DC Vltage 3.204V 3.192V 3.184V Package 55ºC 68ºC 80ºC vltage:3.217v DC Junctin 60ºC 70ºC 84ºC (9) Summary Install a 10F (r greater) capacitr is required between the AIC LDO family device s utput and grund pins fr the reasn f stability. Withut this capacitr, the part will scillate. Even thugh mst types f capacitr may wrk, the equivalent series resistance (ESR) shuld be held t 5 r less, if aluminum electrlytic type is used. Many Aluminum electrlytic capacitrs have electrlytes that will freeze under -30C, s slid tantalums are recmmended fr peratin belw -25C. The value f this capacitr may be increased withut limit. A 10F (r greater) capacitr shuld be placed frm the AIC LDO family input t grund if the lead inductance between the input and pwer surce exceeds 500nH (apprximately 10 inches f trace). 9