HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING Description

Transcription

1 HIGH FEQUENCY 2-PHASE, SINGLE O DUAL OUTPUT SYNCHONOUS STEP DOWN CONTOLLE WITH OUTPUT TACKING AND SEQUENCING Descriptin Features Dual Synchrnus Cntrller with 80 Out f Phase Operatin Cnfigurable t 2-Independent Outputs r Current Shared Single Output Output Vltage Tracking Pwer up / dwn Sequencing Current Sharing Using Inductr s DC +/-% Accurate eference Vltage Prgrammable Switching Frequency up 600kHz Prgrammable Over Current Prtectin Hiccup Current Limit Using MOSFET ds(n) sensing Latched Overvltage Prtectin Dual Prgrammable Sft-Starts Prgrammable Enable Input Pre-Bias Start-up Dual Pwer Gd Outputs On Bard egulatr External Frequency Synchrnizatin Thermal Prtectin 32-Lead MLPQ Package Applicatins Embedded Telecm Systems Distributed Pint f Lad Pwer Architectures Cmputing Peripheral Vltage egulatrs Graphics Cards General DC/DC Cnverters Data Sheet N.PD94722 reva The I3622 IC integrates a dual synchrnus Buck cntrller, prviding a high perfrmance and flexible slutin. The I3622 can be cnfigured as 2-independent utputs r as current shared single utput. The current share cnfiguratin is ideal fr high current applicatins. The I3622 enables utput tracking and sequencing f multiple rails in either ratimetric r simultaneus fashin. The I3622 features 80 ut f phase peratin which reduces the required input/utput capacitance and results in lwer number f capacitrs. The switching frequency is prgrammable frm 200kHz t 600kHz per phase using ne external resistr. In additin, I3622 als allws the switching frequency t be synchrnized t an external clck signal. Other key features ffered by this device include tw independent prgrammable sft starts, tw independent pwer gd utputs, precisin enable input, and under vltage lckut functin. The current limit is prvided by sensing the lwer MOSFET's n-resistance fr ptimum cst and perfrmance. The utput vltages are mnitred thrugh dedicated pins t prtect against pen circuit, and enhance faster respnse t an vervltage event. Vin V V t Cmp Cmp2 I3622 HDrv OCSet LDrv PGnd Vut V2 atimetric Pwerup V2 atimetric Pwerdwn Vut SS / SD SS2 / SD Seq Track HDrv2 OCSet2 Vin Vut2 V V2 V V2 LDrv2 Gnd PGnd2 Simultaneus Pwerup Simultaneus Pwerdwn ODEING INFOMATION PKG PACKAGE PIN PATS PATS T& DESIG DESCIPTION COUNT PE BAG PE EEL OIANTAION M I3622MPbF M I3622MTPbF Fig A 03/5/07

2 ABSOLUTE MAXIMUM ATINGS (Vltages referenced t GND) Vcc, VcL Supply Vltage V t 6V VcH,VcH V t 30V PGd, PGd V t 6V HDrv, HDrv2-0.5V t 30V (-2V fr 00ns) LDrv, LDrv2-0.5V t 6V (-2V fr 00ns) Gnd t PGnd.. +/- 0.3V Strage Temperature ange C T 50 C Operating Junctin Temperature ange C T 25 C ESD Classificatin.. JEDEC, JESD22-A4 (KV) Misture Sensitivity Level.. JEDEC, Level 260 C Cautin: Stresses abve thse listed in Abslute Maximum ating may cause permanent damage t the device. These are stress ratings nly and functin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins is nt implied. Expsure t Abslute Maximum ating cnditins fr extended perids may affect device reliability. Package Infrmatin t VSEN2 Fb2 Cmp2 SS2/SD2/Mde Track VOUT3 Vcc Gnd PGd Pad VEF VP2 VP PGd2 Sync VSEN Fb Cmp OCSet2 6 9 SS/SD VcH2 7 8 OCSet HDrv VcH Enable PGnd2 LDrv2 VcL LDrv PGnd Seq HDrv Θ JA 36 C/W* Θ JC C/W *Expsed pad n underside is cnnected t a cpper pad thrugh vias fr 4-layer PCB bard design 2

3 ecmmended Operating Cnditins Symbl Definitin Min Max Units Vcc, VcL Supply Vltage V VcH, VcH2 Supply Vltage Cnverter Vltage + 5V 28 V Fs Operating frequency khz Tj Junctin temperature C Electrical Specificatins Unless therwise specified, these specificatin apply ver VccVcLVcHVcH22V, 0 C<Tj<05 C Parameter SYM Test Cnditin Min TYP MAX Units Output Vltage Accuracy FB,2 Vltage V FB VpVp2Vref0.8V 0.8 V Accuracy 0 C <Tj< 25 C - + % Supply Current V CC Supply Current (Static) V CC Supply Current (Dynamic) V CL Supply Current (Static) V CL Supply Current (Dynamic) V CH,2 Supply Current (Static) V CH,2 Supply Current (Dynamic) -40 C <Tj< 25 C; Nte % I CC (Static) SS0V, N Switching 3 8 ma I CC (Dynamic) Fs300kHz, C LOAD 3.3nF ma I CL (Static) SS0V, N Switching 8 0 ma I CL (Dynamic) Fs300kHz, C LOAD 3.3nF ma I CH (Static) SS0V, N Switching 9 ma I CH (Dynamic Fs300kHz, C LOAD 3.3nF ma Under Vltage Lckut, Enable V CC -Start Threshld V CC _UVLO() Supply ramping up V V CC -Stp Threshld V CC _UVLO(F) Supply ramping dwn V V CC -Hysteresis Supply ramping up and dwn V V CH,2 -Start Threshld V CH _UVLO() Supply ramping up V V CH,2 -Stp Threshld V CH _UVLO(F) Supply ramping dwn V V CH,2 -Hysteresis Supply ramping up and dwn V Enable-Threshld En_UVLO Supply ramping up V Enable-Hysteresis Supply ramping up and dwn V Oscillatr Frequency ange F S khz Accuracy Fs300kHz % amp Amplitude Vramp Nte.25 V Min Duty Cycle Dmin FbV 0 % Min Pulse Width Tn(min) F S 300kHz, Nte 50 ns Max duty Cycle Dmax F S 300kHz, Fb0.6V 84 % Sync Frequency ange Sync(F) 20% abve free running Freq 200 khz Sync Pulse Duratin Sync(Pulse) ns Sync High Level Threshld Sync(H) 2 V Sync Lw Level Threshld Sync(L) 0.6 V 3

4 Electrical Specificatins Parameter SYM Test Cnditin Min TYP MAX Units Errr Amplifier, 2 Fb Vltage Input Bias Current IFB SS3V µa E/A Surce/Sink I(surce/Sink) µa Current Transcnductance gm, µmh Input ffset Vffset Fb t Vref mv Vltage VP Vltage ange VP Nte 0.4 Vcc-2 V Internal egulatr Output Accuracy Vut V Drput Vdrp Vcc(min)9V, Isurce00mA 2 V Current Limit Ishrt 0 ma Sft Start/SD Sft Start Current ISS Surce/Sink µa Shutdwn Threshld Over Current Prtectin SD 0.25 V OCSET Current I OCSET µa Hiccup Duty Cycle Hiccup(duty) Ihiccup / Icset, Nte 5 % Over Vltage Prtectin OVP Trip Threshld OVP(trip).Vref.5Vref.2Vref V OVP Fault Prp Delay Thermal Shutdwn OVP(delay) Output Frced t.25vref 5 µs Thermal shutdwn Nte 40 Thermal shutdwn Nte 20 Hysteresis Pwer Gd Vsen Lwer Trip pint PGd Output Lw Vltage Vsen(trip) Vsen amping Dwn 0.8Vref 0.9Vref 0.95Vref V PG(vltage) I PGd 2mA V Output Drivers LO, Drive ise Time Tr(L) C LOAD 3.3nF, Fs300KHz, 2V t 9V ns C C LO Drive Fall Time Tf(L) C LOAD 3.3nF, Fs300KHz, 9V t 2V ns HI Drive ise Time Tr(Hi) C LOAD 3.3nF, Fs300KHz, 2V t 9V ns HI Drive Fall Time Tf(Hi) C LOAD 3.3nF, Fs300KHz, 9V t 2V ns Dead Band Time Tdead See Figure ns Seq Input Seq Threshld Seq On 2.0 V Off 0.3 Tracking Track vltage range TK Nte 0 Vcc V 4

5 Nte: Guaranteed by design but nt tested in prductin. Nte2: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. High Side Driver (HDrv) Lw Side Driver (LDrv) 9V 2V 9V 2V Tr Tf Tr Tf Deadband H_t_L Deadband L_t_H Fig. : ise / Fall and deadband time fr driver sectin 5

6 Pin# Pin Name Descriptin t Cnnecting a resistr frm this pin t grund sets the switching frequency (see figure 6 n page 7 fr selecting resistr value) 2 VSEN2 Sense pin fr OVP2 and Pwer Gd2, Channel 2 3 Fb2 Inverting input t the errr amplifier2 4 Cmp2 Cmpensatin pin fr the errr amplifier2 5 SS2/SD2/Mde Sft start fr channel 2, can be used as SD pin. Flat this pin fr current share single utput applicatin 6 OCSet2 Current limit set pint fr channel2 7, 7 VcH2, VcH Supply vltage fr the high side utput drivers. These are cnnected t vltage that must be typically 6V higher than their bus vltages. A 0.uF high frequency capacitr must be cnnected frm these pins t PGND t prvide peak drive current capability 8,6 HDrv2, HDrv Output drivers fr the high side pwer MOSFETs 9 Enable Enable pin, recycling this pin will reset OV, SS and Prebias latch 0, 4 PGnd2, PGnd These pins serve as the separate grunds fr MOSFET drivers and shuld be cnnected t the system s grund plane, 3 LDrv2, LDrv Output drivers fr the synchrnus pwer MOSFETs 2 VcL Supply vltage fr the lw side utput drivers 5 Seq Enable pin fr tracking and sequencing. If this pin is nt used cnnect it t V ut3 8 OCSet Current limit set pint fr Channel 9 SS/SD Sft start fr Channel, can be used as SD pin 20 Cmp Cmpensatin pin fr the errr amplifier 2 Fb Inverting input t the errr amplifier 22 VSEN Sense pin fr OVP and Pwer Gd, Channel 23 Sync External synchrnizatin pin 24 PGd2 Pwer Gd pin utput fr channel 2, pen cllectr. This pin needs t be externally pulled high 25 VP Nn inverting input f errr amplifier 26 VP2 Nn inverting input f errr amplifier2 27 VEF eference Vltage 28 Gnd IC s Grund 29 PGd Pwer Gd pin utput fr Channel, pen cllectr. This pin needs t be externally pulled high 30 Vcc Supply vltage fr the internal blcks f the IC. A 0.uF high frequency capacitr must be cnnected frm this pin t Gnd. 3 Vut3 Output f the internal regulatr. A 0.uF high frequency capacitr must be cnnected frm this pin t PGnd. 32 Track Sets the type f pwer up / dwn sequencing (ratimetric r simultaneus). If this pin is nt used cnnect it t V ut3 6

7 Blck Diagram Enable Vcc Seq SS2 / SD SS / SD PO VP 23uA 23uA 64uA 64uA Errr Amp Mde VcH VcH2 PWM Cmp Bias Generatr UVLO PO Thermal Shutdwn 3V 0.8V 0.3V SS SS 3uA PO OVP PBias S Q PBias VcH HDrv VCL LDrv PGnd Fb Cmp t Sync VEF Track 0.8V Errr Amp2 amp amp2 Tw Phase Oscillatr PWM Cmp2 Set Set2 S eset Dm eset Dm S Q Q SS SS2 Mde Hiccup Cntrl 20uA OCSet VcH2 HDrv2 VP2 Fb2 0.3V S Q OVP2 PBias2 LDrv2 PGnd2 Cmp2 VSEN.5Vref PO S Q SS2 OVP HDrv OFF / LDrv ON PO SS2 3uA 20uA OCSet2 PGd VSEN2 0.90Vref.5Vref PO S Q OVP2 HDrv2 OFF / LDrv2 ON SS / SD 23uA Vcc egulatr Tracking VOUT3 Seq PGd2 Gnd 0.90Vref Fig. 2: Simplified blck diagram f the I3622 7

8 TYPICAL OPEATING CHAACTEISTICS (-40 C-25 C) VFb vs Temperature VFb2 vs Temperature VFb (V) VFb2 (V) Temperature (C) Temperature (C) SS Current vs Temperature SS2 Current vs Temperature -9-9 SS Current (ua) Temperature (C) SS2 Current (ua) Temperature (C) Vcc_UVLO vs Temperature Vut3 vs Temperature Vcc_UVLO (V) Temperature (C) VOut3 (V) Temperature (C) 8

9 TYPICAL OPEATING CHAACTEISTICS (-40 C-25 C) IOCSET vs Temperature IOCSET2 vs Temperature IOCSET (ua) Temperature (C) IOCSET2 (ua) Temperature (C) GM vs Temperature GM2 vs Temperature GM (umh) GM2 (umh) Temperature (C) Temperature (C) Freq 300KHz vs Temperature Max Duty Cycle vs Temperature Freq (KHz) Temperature (C) Max Duty Cycle (%) Temperature 9

10 Circuit Descriptin THEOY OF OPEATION Intrductin The I3622 is a versatile device fr high perfrmance buck cnverters. It cnsists f tw synchrnus buck cntrllers which can be perated either in tw independent utputs mde r in current share single utput mde fr high current applicatins. The timing f the IC is prvided by an internal scillatr circuit which generates tw 80 -ut-fphase clck signals that can be externally prgrammed up t 600kHz per phase. Prgrammable Enable Input The enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by under-vltage lckut circuit. It s threshld can be externally prgrammed t desired level by using tw external resistrs, s the cnverter desn t start up until the input vltage is sufficiently high (see figure 3). Under-Vltage Lckut The under-vltage lckut circuit mnitrs fur signals (Vcc, VcH, VcH2 and Enable). This ensures the crrect peratin f the cnverter during pwer up and pwer dwn sequence. The driver utputs remain in the ff state whenever ne f these signals drp belw set threshlds. Nrmal peratin resumes nce these signals rise abve the set values. Figure 3 shws a typical start up sequence. V 2V 2V 7.2V 7.2V Vbus Vcc Vut3 Seq Enable 3V Enable OK (IC's PO) SS Fig. 3: Nrmal Start up, Enable threshld is externally set t V Seq pin is pulled t Vut3 prir t start up 0

11 Internal egulatr The I3622 features an n-bard 7.2V regulatr with shrt circuit prtectin. The regulatr is capable f surcing current up t 00mA. This integrated regulatr can be used t generate the necessary bias vltage fr drivers, an example f hw this can be used is shwn in figure 23, page26. Out-f-Phase Operatin The I3622 drives its tw utput stages 80 utf-phase. In current share mde single utput, the tw inductr ripple currents cancel each ther and result in a reductin f the utput current ripple and yield a smaller utput capacitr fr the same vltage ripple requirement. Figure 4 shws tw channels inductr current and the resulting vltage ripple at the utput. HDV MS Current Nrmalized (I MS /I ut ) In additin, the 80 ut f phase cntributes t input current cancellatin. This results in much smaller input capacitr s MS current and reduces the number f required input capacitrs. Figure 5 shws the equivalent MS current. Single Phase 2 Phase Duty Cycle (V/Vin) Fig. 5: Input MS value vs. Duty Cycle HDV2 IL 0 DT T IL2 Mde Selectin The I3622 can perate as a dual utput independently regulated buck cnverter, r as a 2 phase single utput buck cnverter (current share mde). The SS2 pin is used fr mde selectin. In current share mde this pin shuld be flating. In the dual utput mde, a sft start capacitr must be cnnected frm this pin t the grund t prgram the start time fr the secnd utput. Ic Fig. 4: Current ripple cancellatin fr utput I Independent Mde In this mde the I3622 prvides cntrl t tw independent utput pwer supplies with either cmmn r different input vltages. The utput vltage f each individual channel is set and cntrlled by the utput f the errr amplifier, which is the amplified errr signal frm the sensed utput vltage and the reference vltage. The errr amplifier utput vltage is cmpared t the ramp signal thus generating fixed frequency pulses f variable duty-cycle, (PWM) which are applied t the internal MOSEFT drivers. Figure 24 shws a typical schematic fr such applicatin.

12 Current Share Mde This feature allws t cnnect bth utputs tgether t increase current handling capability f the cnverter t supprt a cmmn lad. In the current sharing mde, errr amplifier becmes the master which regulates the cmmn utput vltage and the errr amplifier 2 perfrms the current sharing functin, figure 6 shws the cnfiguratin f errr amplifier 2. In this mde, I3622 makes sure the master channel starts first fllwed by slave channel t prevent any glitch during start up. This is dne by clamping the utput f slave s errr amplifier until the master channel generates the first PWM signal. At n lad cnditin the slave channel may be kept ff depending n the ffset f the errr amplifier. Lssless Inductr Current Sensing The I3622 uses a lssless current sensing fr current share purpses. The inductr current is sensed by cnnecting a series resistr and a capacitr netwrk in parallel with the inductr and by measuring the vltage acrss the capacitr. The measured vltage is prprtinal t the inductr current. This is shwn figure 6. The vltage acrss the inductr s DC can be expressed by: L VL ( s ) ( Vin Vut ) * ( ) + sl Cmbining equatins (),(2) and (3) result in the fllwing expressin fr V C : Usually the resistr and C are chsen s that the time cnstant f and C equals the time cnstant f the inductr which is the inductance L ver the inductr s DC ( L ). If the tw time cnstants match, the vltage acrss C is prprtinal t the current thrugh L, and L V ( s ) I * L L L ( 2 ) The vltage acrss the C can expressed by: sc V ( s ) ( V V ) * ( 3 ) C in ut + sc V C ( s ) I L L + sl * + s * C ( 4 ) Vin Vin Q2 Q3 Q4 Master Phase IL L L + VL (s) - C 2 L2 VP2 FB2 + VC(s) - L2 Fig. 6: Lss Less inductr current sensing and current sharing C2 Slave Phase VOUT the sense circuit can be treated as if nly a sense resistr with the value L was used. If : C V ( s ) I L * C L * The mismatch f the time cnstant des nt affect the measurements f inductr DC current, but affects the AC cmpnent f the inductr current. Sft-Start The I3622 has prgrammable sft-start t cntrl the utput vltage rise and limit the inrush current during start-up. It prvides a separate sft-start functin fr each utput. This will enable t sequence the utputs by cntrlling the rise time f each utput thrugh selectin f different value sft-start capacitrs. T ensure crrect start-up, the sft-start sequence initiates when the Vcc, VcH, VcH2 and Enable rise abve their threshld and generate the Pwer On eset (PO) signal. Sft-start functin perates by surcing an internal current t charge an external capacitr t abut 3V. Initially, the sft-start functin clamps the errr amplifier s utput f the PWM cnverter. L L 2

13 Sft-Start (cnt.) During pwer up, the cnverter utput starts at zer and thus the vltage at Fb is abut 0V. An internal vltage-cntrlled current surce (64uA) injects current int the Fb pin and generates a vltage abut.6v (64ux25K) acrss the negative input f errr amplifier, see figure 7. This keeps the utput f the errr amplifier lw. The magnitude f this current is inversely prprtinal t the vltage at the sft-start pin. The 23uA current surce starts t charge up the external capacitr. In the mean time, the sftstart vltage ramps up, the current flwing int Fb pin starts t decrease linearly and s des the vltage at the negative input f errr amplifier. When the sft-start vltage reaches abut V, the vltage at the negative input f the errr amplifier is apprximately 0.8V. As the sft-start capacitr vltage charges up, the current flwing int the Fb pin keeps decreasing. The feedback vltage increases linearly as the injecting current ges dwn. The injecting current drps t zer when sft-start vltage is arund.8v and the utput vltage ges int steady state. Figure 8 shws the theretical peratinal wavefrms during sft-start. The utput start-up time is the time perid when sft-start capacitr vltage increases frm V t.8v. The start-up time will be dependent n the size f the external sft-start capacitr. The startup time can be estimated by: Tstart 23µA. 8V V C ss SS/SD Seq Fb VP SS2/SD2 PO 64uA PO E/A 64uA 3V 3V E/A2 Fb2 VP2 Track ISS 23uA Ihiccup 3uA ISS2 23uA Ihiccup2 3uA Fig. 7: Sft-Start circuit fr I3622 OCP2 Output f PO 3V OCP Fr a given start up time, the sft-start capacitr (nf) can be estimated as: C SS 23 (µ A ) * Tstart ( ms ) 0. 8( V ) ( 5 ) Fr nrmal start up the Seq pin shuld be pulled high (usually can be cnnected t Vut3). Sft-Start Vltage 64uA Current flwing int Fb pin Vltage at negative input f Errr Amp 0V.6V.8V V 0uA 0.8V 0.8V Vltage at Fb pin 0V Fig. 8: Theretical peratin wavefrms during sft-start 3

14 Output Vltage Tracking and Sequencing The I3622 can accmmdate a full spectrum f user prgrammable tracking and sequencing ptins using Track, Seq, Enable and Pwer Gd pins. Thrugh these pins bth simple vltage tracking such as that required by the DD memry applicatin r mre sphisticated sequencing such as ratimetric r simultaneus can be implemented. The Seq pin cntrls the internal current surces t set the pwer up r dwn sequencing. Tggle this pin high fr pwer up, and tggle this pin lw fr pwer dwn. The Track pin is used t determine the secnd channel utput fr either ratimetric r simultaneus by using tw external resistrs. Figure 9 shws hw these pins are cnfigured fr different sequencing mde. In general the A and B set the utput vltage fr the first utput and C and D set the utput vltage fr the secnd utput. Fr simultaneus vs. ratimetric, E and F can be selected accrding t the table belw: Simultaneusly atimetric Track Pin E C, F D E A, F B 3V 64uA ISS 23uA SS/SD OCP CSS PO Ihiccup 3uA Seq V A Fb E/A Fig. 0: atimetric Pwer Up / dwn B VP VEF 3V SS2/SD2 Flating 64uA ISS2 23uA OCP2 V2 PO Ihiccup2 3uA C D Fb2 E/A2 V E Track F VP2 VEF Fig. 9: Using Seq and Track pin fr different sequencing Fig. : Simultaneusly Pwer up /dwn 4

15 Fault Prtectin The I3622 mnitrs the utput vltage fr ver vltage prtectin and pwer gd indicatin. It senses the ds(n) f lw side MOSFET fr ver current prtectin. It als prtects the utput fr prebias cnditins. Figure 2 shws the IC s perating wavefrms under different fault cnditins. PO 3V.8V.0V SS V 90%Vfb Set Vltage Pre_Bias Vltage PGd OCP Threshld Iut OV t0 t t2 t3 t4 t5 t6 t7 t8 t9 t0 t Fig. 2: Fault Cnditins t 0 t : Vcc, VcH,VcH2 and Enable signals passed their respective UVLO threshld. Sft start sequence starts. t t 2 : Pwer Gd signal flags high. t t 3 : Output vltage ramps up and reaches the set vltage. t 4 t 5 : OC event, SS ramps dwn. IC in Hiccup mde. t 5 t 6 : OC is remved, recvery sequence, fresh SS. t 6 t 7 : Output vltage reaches the set vltage. t 8 : OVP event. HDrv turns ff and LDrv turns n. The IC latches ff. t 9 t 0 : Manually recycled the Vcc after latched OVP. PreBias start up. t 0 t : New Sft Start sequence 5

16 Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the ds(n) f the lw side MOSFET (Q2). This methd enhances the cnverter s efficiency and reduce cst by eliminating a current sense resistr. As shwn in figure 3, an external resistr ( SET ) is cnnected between the OCSet pin and the drain f Q2 which sets the current limit set pint. 23uA SS / SD 20 28uA 3uA OCP The internal current surce develps a vltage acrss SET. When the Q2 is turned n, the inductr current flws thrugh the Q2 and results in a vltage drp which is given by: V OCSet Hiccup Cntrl (I OCSet I3622 IOCSET OCSet ) ( OCSet ds(n) I ) SET L (6) Q Q2 L VOUT Fig. 4: 3uA current surce fr discharging sft-start capacitr during hiccup The OCP circuit starts sampling current when the lw gate drive is abut 3V. The OCSet pin is internally clamped t apprximately.4v during deadtime t prevent false trigging. Figure 5 shws the OCSet pin during ne switching cycle. There is abut 50ns delay t mask ut the deadtime, since this nde cntains switching nise, this delay als functins as a filter. Fig. 3: Cnnectin f ver current sensing resistr The critical inductr current can be calculated by setting: Deadtime I V (I ) ( I ) OCSet OCSet OCSet ds(n) L SET I L( critical) OCSet I ds( n) OCSet (7) I cset * cset Blanking time Clamp Vltage An ver current is detected if the OCSet pin ges belw grund. This trips the OCP cmparatr and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by charging and discharging the sft-start capacitr at a certain slpe rate. As shwn in figure 4 the 3uA current surce is used t discharge the sft-start capacitr. The OCP cmparatr resets after every sft start cycles, and the cnverter stays in this mde until the verlad r shrt circuit is remved. The cnverter will autmatically recver. Fig. 5: OCset pin during nrmal cnditin Ch: Inductr pint, Ch2:LDrv, Ch3:OCSet The value f SET shuld be checked in an actual circuit t ensure that the ver current prtectin circuit activates as expected. The I3622 current limit is designed primarily as shrt circuit prtectin, "n blw up" circuit, and desn't perate as a precisin current regulatr. When the SS2 is flating, an ver current cnditin n either phase wuld result in hiccup current prtectin. 6

17 Pre-Bias The I3622 is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSFET ff until the first gate signal fr cntrl MOSFET is generated. Figure belw shws a typical Pre-Bias cnditin at start up. Depending n system cnfiguratin, specific amunt f utput capacitance may be required t prevent discharging the utput vltage. Operating Frequency Selectin The switching frequency is determined by cnnecting an external resistr (t) t grund. Figure 6 prvides a graph f scillatr frequency versus t. The maximum recmmended channel frequency is 600kHz V V Fsw (khz) Pre-Bias Vltage (Output Vltage befre startup) Over Vltage Prtectin Over-vltage is sensed thrugh tw dedicated sense pins V SEN, V SEN2. A separate OVP circuit is prvided fr each channel. The OVP threshld is user prgrammable and can be set by tw external resistrs. Upn vervltage cnditin f either ne f the utputs, the OVP frces a latched shutdwn n the fault utput. In this mde, the upper FET driver turns ff and the lwer FET drivers turn n, thus crwbaring the utput. eset is perfrmed by recycling the Vcc r Enable. Pwer Gd The I3622 prvides tw separate pen cllectr pwer gd signals which reprt the status f the utputs. The utputs are sensed thrugh the tw dedicated V SEN and V SEN2 pins. Once the I3622 is enabled and the utputs reach the set value (90% f the Vut set pint) the pwer gd signals g pen and stay pen as lng as the utputs stay within the set values. These pins need t be externally pulled high. Shutdwn using Sft Start pins The utputs can be shutdwn by pulling the sftstart pins belw 0.3V. This can be easily dne by using an external small signal transistr. During shutdwn bth MOSFET drivers will be turned ff. Nrmal peratin will resume by cycling sft start pin. Time t (Khm) Fig. 6: Switching Frequency vs. External esistr ( t ) Frequency Synchrnizatin The I3622 is capable f accepting an external digital synchrnizatin signal. Synchrnizatin will be enabled by the rising edge at an external clck. Per channel switching frequency is set by external resistr (t). The free running frequency scillatr frequency is twice the perchannel frequency. During synchrnizatin, t is selected such that the free running frequency is 20% belw the synchrnizatin frequency. Synchrnizatin capability is prvided fr bth single utput current share mde and dual utput cnfiguratin. The sync pin is nise immune, when unused it shuld be left flating. Thermal Shutdwn Temperature sensing is prvided inside I3622. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSFETs. Thermal shutdwn is nt latched and autmatic restart is initiated when the sensed temperature drps t the nrmal range. There is a 20 C (typical) hysteresis in the shutdwn threshld. 7

18 Applicatin Infrmatin Design Example: The fllwing is a design f typical single utput current share applicatin fr I3622. The applicatin circuit is shwn n page 26. V V. 8V I in 2V,( ± 0%) 40A V 30mV F 375kHz s Output Vltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. As shwn in figure 7 the Fb pin is the inverting input f the errr amplifier, which is internally referenced t 0.8V. The divider is set t prvide 0.8V at the Fb pin when the utput is at its desired value. The utput vltage is defined by the fllwing equatin: Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. The start-up time f the cnverter can be calculated using the fllwing expressin: C ( nf) ( µ A) T ( ms) (0) SS * Where T start is the desired start-up time (ms) Fr a start-up time f 5ms, the sft-start capacitr will be 0.5uF. Chse a ceramic capacitr at 0.5uF. Input Capacitr Selectin The 80 ut f phase will reduce the MS value f the ripple current seen by input capacitrs. This reduces numbers f input capacitrs. The input capacitrs must be able t handle bth the maximum ripple MS current at the highest ambient temperature, as well as the maximum input vltage. The MS value f current ripple fr a duty cycle under 50% is expressed by: start Fig. 7: Typical applicatin f the I3622 fr prgramming the utput vltage V V EF I Fb (8 ) Equatin (8) can be rewritten as: Fr the calculated values f 5 and 6 feedback cmpensatin sectin. 6 5 Vref 5 6 V V ref (9 ) VOUT 6 5 see 2 2 ( I D ( D ) + I D ( D ) 2I I DD ) () I MS Where: -I MS is the MS value f the input capacitr current -D and D 2 are duty cycle fr each channel -I and I 2 are the utput current fr each channel Fr I40A and D0.6 (.8V/0.8V), the I MS 9.43A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ES and ESL at higher frequency, which enhance circuit efficiency. Use 0x22uF, 6V ceramic capacitr frm TDK (C3225X5C226M). Fr the single utput applicatin when the duty cycle is larger than 50% the fllwing equatin can be used t calculate the ttal MS current fr the input capacitr current: ( 2D ( D) + ( 2 2D) ) D 0.5 I I > MS O 8

19 Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. Lw inductr value results in large ripple current, smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f inductr value can be reduced t desired maximum ripple current in the inductr ( i ). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. Fr the buck cnverter, the inductr value fr desired perating ripple current can be determined using the fllwing relatin: Where: Fr 2-phase single utput applicatin the inductr ripple current is chsen between 20-50% f maximum phase current If V in L t Turn n time L 0.4uH i V V L t D in ; t F V Output Vltage V V i * F ( V V ) (2) F Switching frequency in Maximum input vltage i Inductr ripple current s D Duty cycle i 50%( I ), then the utput inductr will be: The Cilcraft MLC260-40ML (L 0.4uH, 20A, L 0.93mOhm) is a lw prfile inductr suitable fr this applicatin. Use the fllwing equatin t calculate C and fr current sensing: (refer t figure 6 n page 2) This results t C uf and 0.432K in L * C L s s Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs types and values. The criteria is nrmally based n the value f the Equivalent Series esistance (ES). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing factrs. The verall utput vltage ripple can be expressed as: V V where: V V V ( ES) ( ESL) ( C) + V I * ES Vin * ESL L IL 8 * C * F + V (3) V Output vltage ripple I Inductr ripple current L ( ES) L s ( ESL) ( C) Therefre it is recmmended t select utput capacitr with lw enugh ES t meet utput ripple and step lad transient requirements. The utput ripple is highest at maximum input vltage since i increases with input vltage. Special Plymer capacitrs ffers lw ES with large strage capacity per unit vlume. These capacitrs ffer a cst effective utput capacitr slutin and are ideal chice when cmbined with a cntrller having high lp bandwidth. The I3622 can perfrm well with all types f capacitrs. Panasnic EEFSXOD22 (SP, 220F, 2V, 9mOhm) is selected fr this design. Equatin (3) can be used t calculate the required ES fr the specific vltage ripple. Fur SP capacitrs wuld meet the vltage ripple requirement. 9

20 Pwer MOSFET Selectin The I3622 uses tw N-Channel MOSFETs per channel. The selectin criteria t meet pwer transfer requirements are based n maximum drain-surce vltage (V DSS ), gate-surce drive vltage (V gs ), maximum utput current, Onresistance DS(n), and thermal management. The MOSFET must have a maximum perating vltage (V DSS ) exceeding the maximum input vltage (V in ). The gate drive requirement is almst the same fr bth MOSFETs. Lgic-level transistr can be used and cautin shuld be taken with devices at very lw gate threshld vltage (V gs ) t prevent undesired turn-n f the cmplementary MOSFET, which results a sht-thrugh current. The ttal pwer dissipatin fr MOSFETs includes cnductin and switching lsses. Fr the Buck cnverter the average inductr current is equal t the DC lad current. The cnductin lss is defined as: 2 P (upperswitch) I D ϑ cnd lad ds(n) 2 Pcnd (lwerswitch) Ilad ds(n) ( D) ϑ ϑ temperatur e dependency ds(n) The DS(n) temperature dependency shuld be cnsidered fr the wrst case peratin. This is typically given in the MOSFET data sheet. Ensure that the cnductin lsses and switching lsses d nt exceed the package ratings r vilate the verall thermal budget. Fr this design, IF6622 is selected fr cntrl FET and IF6629 is selected fr synchrnus FET. These devices prvide lw n resistance in a cmpact Direct FET package. The MOSFETs have the fllwing data: CntrlFET(IF6622) : V ds 25V,Q 87. 0V ds(n) V The cnductin lsses will be: P cn.w/phase The switching lss is mre difficult t calculate, even thugh the switching transitin is well understd. The reasn is the effect f the parasitic cmpnents and switching times during the switching prcedures such as turn-n / turnff delays and rise and fall times. The cntrl MOSFET cntributes t the majrity f the g gs 0V gs SyncFET(IF6629) : V ds 25V,Q 5nC@ 0V ds(n) g 2. V gs 0V gs switching lsses in synchrnus Buck cnverter. The synchrnus MOSFET turns n under zer vltage cnditins, therefre, the turn n lsses fr synchrnus MOSFET can be neglected. With a linear apprximatin, the ttal switching lss can be expressed as: Vds( ff ) t + t r f Psw * * Ilad (3A) 2 T Where: V ds(ff) Drain t surce vltage at the ff time t r ise time t f Fall time T Switching perid I lad Lad current The switching time wavefrms is shwn in figure8. VDS 90% 0% VGS td(on) tr td(off) Fig. 8: switching time wavefrms Frm IF6622 data sheet: tr 3ns tf 4ns These values are taken under a certain cnditin test. Fr mre details please refer t the IF6622 data sheet. By using equatin (3A), we can calculate the switching lsses. P sw 2.8W The reverse recvery lss is als anther cntributing factr in cntrl FET switching lsses. This is equivalent t extra current requires t remve the minrity charges frm synchrnus FET. The reverse recvery lss can be expressed as: P Q * t * F Q :everseecverycharge t : everseecverytime rr Qrr F : SwitchingFrequency s rr rr rr s tf 20

21 Feedback Cmpensatin The I3622 is a vltage mde cntrller; the cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed lp transfer functin with the highest 0dB crssing frequency and adequate phase margin (greater than 45 ). The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure 9). The resnant frequency f the LC filter expressed as fllws: F LC Figure 9 shws gain and phase f the LC filter. Since we already have 80 phase shift just frm the utput filter, the system risks being unstable. 0dB Gain The I3622 s errr amplifier is a differential-input transcnductance amplifier. The utput is available fr DC gain cntrl and AC phase cmpensatin. The E/A can be cmpensated either in type II r type III cmpensatin. When it is used in type II cmpensatin the transcnductance prperties f the E/A becme evident and can be used t cancel ne f the utput filter ples. This will be accmplished with a series C circuit frm Cmp pin t grund as shwn in figure 20. This methd requires that the utput capacitr has enugh ES t satisfy stability requirements. In general the utput capacitr s ES generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ES zer f the utput capacitr expressed as fllws: 2 π L C FLC Frequency -40dB/decade (4) Phase 0-80 FLC Fig. 9: Gain and Phase f LC filter Frequency F VOUT 6 ES 5 2 π * ES* C VEF H(s) db Fb Gain(dB) E/A FZ (5) The transfer functin (Ve/V) is given by: The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: The gain is determined by the vltage divider and E/A s transcnductance gain. First select the desired zer-crssver frequency (F): F > F and F /5 ~/0 * F Use the fllwing equatin t calculate 4 : Where: V in Maximum Input Vltage V sc Oscillatr amp Vltage F Crssver Frequency F ES Zer Frequency f the Output Capacitr F LC esnant Frequency f the Output Filter g m Errr Amplifier Transcnductance Cmp 4 Frequency C9 Ve CPOLE Fig. 20: TypeII cmpensatin netwrk and its asympttic gain plt + s C H( s) gm * 5 * + 6 sc9 5 gm * * Fz 2π * * C [ H( s) ] V 4 sc ES (8) * F * F * ( + ) ES V * F * * g in LC (6) (7) ( ) s m (9) 2

22 T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: F 75% F z LC Fz * 2π L * C (20) Using equatins (8) and (20) t calculate C9. C9 2π * * F 4 z ZIN 8 C0 VOUT 6 5 Fb 7 E/A C2 C Zf Ve Cmp One mre capacitr is smetimes added in parallel with C 9 and 4. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: F P C9 * CPOLE 2π * 4 * C + C The ple sets t ne half f switching frequency which results in the capacitr C POLE : C Fr a general slutin fr uncnditinal stability fr any type f utput capacitrs in a wide range f ES values, we shuld implement lcal feedback with a cmpensatin netwrk (typeiii). The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 2. In such cnfiguratin, the transfer functin is given by: V g Z e m f V + g Z The errr amplifier gain is independent f the transcnductance under the fllwing cnditin: By replacing Z in and Z f accrding t figure 5, the transfrmer functin can be expressed as: POLE π * * F Fs Fr FP << 2 H( s) s ( C + C s 9 m C 9 IN POLE gm * Zf >> and gm * Zin >> π * * F ( + s7c) * * ) C * C 2 + s 7 C + C 2 4 s (2) [ + sc ( + )] 0 * ( + s8c ) H(s) db Gain(dB) VEF FZ FZ2 FP2 FP3 Fig. 2: Cmpensatin netwrk with lcal feedback and its asympttic gain plt As knwn, transcnductance amplifier has high impedance (current surce) utput, which needs t be cnsidered when lading the E/A utput. If the surce/sink utput current capability is exceeded the amplifier will nt be able t swing its utput vltage ver the necessary range. The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: F F F F F P P 2 P 3 z z2 0 2π * * C C 2π * 7 C 2π * * C 7 2π * C * C + C Crss ver frequency is expressed as: F * C π * * C 7 2 * ( + ) 2π * C V * V in sc 8 * 2π * L * C 0 * 6 Frequency 22

23 Based n the frequency f the zer generated by utput capacitr and its ES versus crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f crssver frequency. Cmpensatr type TypII(PI) F ES vs. F F LC <F ES <F <F s/2 Output capacitr Electrlytic, Tantalum The fllwing design rules will give a crssver frequency apprximately ne-sixth f the switching frequency. The higher the band width, the ptentially faster the lad transient respnse. The DC gain will be large enugh t prvide high DC-regulatin accuracy (typically -5dB t -2dB). The phase margin shuld be greater than 45 fr verall stability. 7 2 g m ; 0. 67KΩ ; 7 Select: 6.04KΩ 7 TypeIII(PID) Methd A F LC <F <F ES <F s/2 Tantalum, ceramic CalculateC,C 2 andc 0 : TypeIII(PID) Methd B F LC <F <F s/2 <F ES Ceramic Table- The cmpensatin type and lcatin f F ES versus F The details f these cmpensatin types are discussed in applicatin nte AN-043 which can be dwnladed frm I Web-Site. Fr this design we have: V in 3.2V V.8V V sc.25v V ref 0.8V g m 3000umh L 0.4uH, DC0.930mOhm C 4x220uF, ES 2.25mOhm F s 375kHz These result in: F LC 2kHz (eplace L t L/2 in frmula#4 fr current share cnfiguratin) F ES 80.38kHz F s/2 85kHz Select crssver frequency: F 60kHz ( /5 ~/0) Fs F < F and F * ES Since: F LC <F <F ES <Fs/2, typeiii methd A is selected t place the ple and zers. F C F C C Select: C Calculate, 8 2π * C 6 2π * C Vref 5 V V Check: Z P * F 2π * F F 2π * F 2π * F * L * C * V 6 s 0.78kΩ > nF 0 0 ref Z P3 8 LC gm * ; C * 7 6 * F * F P2 Z2 * ; 6. 30KΩ, Select: 6. 34KΩ > gm ; C in and ;. 32KΩ, ; 7. 84KΩ, 5 OK! nF, Select: C 70pF, * V 8 8 sc 5 : 6 ; C 0. 03nF, gm Select: C 2 Select: KΩ Select: 7. 87KΩ 0.33 KΩ 2.8nF 56pF If this cnditin is nt met, then iteratin may be required by selecting larger

24 Cmpensatin fr Current Lp (slave channel) The slave errr amplifier is differential transcnductance amplifier, in 2-phase cnfiguratin the main gal fr the slave channel feedback lp is t cntrl the inductr current t match the master channel inductr current as well prvides highest bandwidth and adequate phase margin fr verall stability. The fllwing analysis is valid fr bth using external current sense resistrs and using DC f the inductr. The transfer functin f pwer stage is expressed by: IL2( s) Vin G( s) V sl * V Where: V in Input vltage L 2 Output inductr V sc Oscillatr Peak Vltage e (22) As shwn the G(s) is a functin f inductr current. The transfer functin fr cmpensatin netwrk is given by equatin (23), when using a series C circuit as shwn in figure22. S2 S IL2 Fb2 IL Vp2 L2 L sc E/A2 Cmp2 Fig. 22: The Cmpensatin netwrk fr current lp 2 C2 Ve Select a zer frequency fr current lp (F 2 ).2 times larger than zer crss frequency fr vltage lp (F ). Frm (24), 2 can be expressed as: V in 3.2V V sc.25v g m 3000umh L 2 0.4uH s DC0.930mOhm F 2 72kHz This results t : 2 6.4K Select K The pwer stage f current lp has a dminant ple (Fp) at frequency expressed by: Where ds(n) is the n-resistance f cntrl FET, ds(n2) is the n-resistance f synchrnus FET, L is the DC f utput inductance and D is the duty cycle eq 3.7mOhm F. 25% * F O2 Vin H( FO 2) gm * s * 2 * 2π * F * L * V 2 g * eq m s O2 O 2π * FO2 * L2 * V * V in eq FP 2π * L ds( n) * D + ds( n2) 2 2 sc sc * ( D) (25) L (24) V ( s) + sc e s 2 2 T( s) gm * s2 * s2 sc (23) Set the zer f cmpensatr at 0 times the dminant ple frequency F P, the cmpensatr capacitr, C2 can be expressed as: The lp gain functin is: H( s) [ G( s) * T( s) ] H ( s) * s2 * g m * s s2 s2 + s C V 2 2 in * * sc2 sl2 * V sc C 2.8nF F 0 * F z C2 2π * * F All design shuld be tested fr stability t verify the calculated values. P 2 z 24

25 Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr ( SET ) frm drain f lw side MOSFET t the OCSet pin. The resistr can be calculated by using equatin (7). The ds(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrse case peratin. This resistr must be placed clse t the IC, place a small ceramic capacitr frm this pin t grund fr nise rejectin purpses. I SET ds( n) 2. mω mΩ I I 20A. 5 30A SET ( LIM ) (50% ver nminal utput current) 4KΩ OCSet I L( critical) 3 OCSet I 4 ds( n) OCSet (7) Layut Cnsideratin The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Start t place the pwer cmpnents, make all the cnnectin in the tp layer with wide, cpper filled areas. The inductr, utput capacitr shuld be clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place input capacitr clse t cntrl FETs, t reduce the ES replace the single input capacitr with tw parallel units. The feedback part f the system shuld be kept away frm the inductr and ther nise surces, and be placed clse t the IC. In multilayer PCB use ne layer as pwer grund plane and have a cntrl circuit grund (analg grund), t which all signals are referenced. The gal is t lcalize the high current path t a separate lp that des nt interfere with the mre sensitive analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The expsed pad f IC shuld be cnnected t analg grund. 25

26 Typical Applicatin C2 D 2V C C3 C4 C3 VCL VcH VOUT3 VcH2 C4 PGd 2 Vut C0 C5 C8 C9 Vcc Enable Sync VEF VP t Cmp Cmp2 PGd SS / SD SS2 / SD U I3622 HDrv OCSet LDrv PGnd VP2 VSEN VSEN2 Fb Fb2 HDrv2 OCSet2 LDrv2 PGnd2 Gnd 6 Q2 Q3 Q4 Q5 C7 L3 5 9 L4 C5 C Vut C6 Vut3 Track Seq PGd2 Fig. 23: Applicatin circuit fr 2V 40A 26

27 Typical Applicatin C2 D BAT54S 2V C C3 C4 VCL VcH VOUT3 VcH2 C3 C4 26 C5 Vcc HDrv OCSet Q2 L3 Vut 27 VOUT PGd PGd2 C C5 C8 C9 Enable VP VEF VP2 t Cmp Cmp2 PGd PGd2 SS / SD SS2 / SD U I3622 LDrv PGnd Sync VSEN VSEN VSEN2 VSEN2 Fb Fb2 HDrv2 6 OCSet2 LDrv2 PGnd2 VOUT3 Q3 D2 VSEN BAT54S C30 C7 Q4 L4 Q5 22 VSEN C8 C6 Vut2 Vut A B Seq Track Gnd Fig. 24: Applicatin circuit fr Dual utput applicatin Tracking and sequencing using Track pin Track Pin Simultaneusly atimetric A 9, B 5 A 7, B 8 27

28 PCB Metal and Cmpnents Placement Lead land width shuld be equal t nminal part lead width. The minimum lead t lead spacing shuld be 0.2mm t minimize shrting. Lead land length shuld be equal t maximum part lead length mm utbard extensin mm inbard extensin. The utbard extensin ensures a large and inspectable te fillet, and the inbard extensin will accmmdate any part misalignment and ensure a fillet. Center pad land length and width shuld be equal t maximum part pad length and width. Hwever, the minimum metal t metal spacing shuld be 0.7mm fr 2 z. Cpper ( 0.mm fr z. Cpper and 0.23mm fr 3 z. Cpper). A single 0.30mm diameter via shall be placed in the center f the pad land and cnnected t grund t minimize the nise effect n the IC. 28

29 Slder esist The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.06mm. The slder resist mis-alignment is a maximum f 0.05mm and it is recmmended that the lead lands are all Nn Slder Mask Defined (NSMD). Therefre pulling the S/ 0.06mm will always ensure NSMD pads. The minimum slder resist width is 0.3mm. At the inside crner f the slder resist where the lead land grups meet, it is recmmended t prvide a fillet s a slder resist width f 0.7mm remains. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.06mm t accmmdate slder resist mis-alignment. In 0.5mm pitch cases it is allwable t have the slder resist pening fr the land pad t be smaller than the part pad. Ensure that the slder resist in-between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land. The single via in the land pad shuld be tented r plugged frm bttm bardside with slder resist. 29

30 Stencil Design The stencil apertures fr the lead lands shuld be apprximately 80% f the area f the lead lands. educing the amunt f slder depsited will minimize the ccurrence f lead shrts. Since fr 0.5mm pitch devices the leads are nly 0.25mm wide, the stencil apertures shuld nt be made narrwer; penings in stencils < 0.25mm wide are difficult t maintain repeatable slder release. The stencil lead land apertures shuld therefre be shrtened in length by 80% and centered n the lead land. The land pad aperture shuld be striped with 0.25mm wide penings and spaces t depsit apprximately 50% area f slder n the center pad. If t much slder is depsited n the center pad the part will flat and the lead lands will be pen. The maximum length and width f the land pad stencil aperture shuld be equal t the slder resist pening minus an annular 0.2mm pull back t decrease the incidence f shrting the center land t the lead lands when the part is pushed int the slder paste. 30

31 (I3622M) MLPQ Package; 5x5-32 Lead I3622MPbF Feed Directin Figure A I WOLD HEADQUATES: 233 Kansas St., El Segund, Califrnia 90245, USA Tel: (30) TAC Fax: (30) This prduct has been designed and qualified fr the Industrial market. Visit us at fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 6/5/2007 3