HIGH FREQUENCY 2-PHASE, SINGLE OR DUAL OUTPUT SYNCHRONOUS STEP DOWN CONTROLLER WITH OUTPUT TRACKING AND SEQUENCING Description Features

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1 HIGH FEQUENCY 2-PHASE, SINGLE O DUAL OUTPUT SYNCHONOUS STEP DOWN CONTOLLE WITH OUTPUT TACKING AND SEQUENCING Descriptin Features Dual Synchrnus Cntrller with 80 Out f Phase Operatin Cnfigurable t 2-Independent Outputs r Current Share Single Output Output Vltage Tracking Pwer up /dwn Sequencing Current Sharing Using Inductr s DC +/-% Accurate eference Vltage Prgrammable Switching Frequency up 200kHz Prgrammable Over Current Prtectin Hiccup Current Limit Using MOSFET DS(n) sensing Latched Overvltage Prtectin Dual Prgrammable Sft-Starts Enable Pre-Bias Start-up Dual Pwer Gd Outputs On Bard egulatr External Frequency Synchrnizatin Thermal Prtectin 32-Lead MLPQ Package Applicatins Embedded Telecm Systems Distributed Pint f Lad Pwer Architectures Cmputing Peripheral Vltage egulatr Graphics Card General DC/DC Cnverters Data Sheet N.PD9477 rev.i The I3623 IC is a high perfrmance Synchrnus Buck PWM Cntrller that can be cnfigured fr tw independent utputs r as a current sharing single utput. Since the IC des nt cntain integrated MOSFET drivers it is ideal fr cntrlling ipowi TM integrated pwer stage mdules such as the ip2005 series f prducts. I3623 enables utput tracking and sequencing f multiple rails in either ratimetric r simultaneus fashin. The I3623 features 80 ut f phase peratin which reduces the required input/utput capacitance. The switching frequency is prgrammable frm 200kHz t 200kHz per phase by use f an external resistr r the switching frequency can be synchrnized t an external clck signal. Other key features ffered by the I3623 include; tw independent prgrammable sft starts, tw independent pwer gd utputs, precisin enable input and under vltage lckut. The current limit is prvided by sensing the lw side MOSFET's n-resistance fr ptimum cst and perfrmance. The utput vltages are mnitred thrugh dedicated pins t prtect against pen circuit and t imprve respnse time t an vervltage event. V V V2 V2 atimetric Pwerup atimetric Pwerdwn V V V2 V2 Simultaneus Pwerup Simultaneus Pwerdwn Fig. : Pwer Up /Dwn Sequencing ODEING INFOMATION PKG PACKAGE PIN PATS PATS T& DESIG DESCIPTION COUNT PE TUBE PE EEL OIANTAION M I3623MPbF M I3623MTPbF Fig A January 28, 203

2 ABSOLUTE MAXIMUM ATINGS (Vltages referenced t GND) Vcc Supply Vltage V t 6V PWM, PWM V t 6V PGd V t 6V Gnd t SGnd +/- 0.3V Strage Temperature ange C T 50 C Operating Junctin Temperature ange C T 25 C ESD Classificatin JEDEC, JESD22-A4 Cautin: Stresses abve thse listed in Abslute Maximum ating may cause permanent damage t the device. These are stress ratings nly and functin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins is nt implied. Expsure t Abslute Maximum ating cnditins fr extended perids may affect device reliability. Package Infrmatin PGd 32 5V_sns Enable t Gnd SGnd VEF VP2 VP Seq PGd Sync Track2 VSEN2 OVP_Output Pad Track VSEN OCGnd Fb2 6 9 Fb Cmp2 7 8 Cmp SS2/SD2/Mde SS/SD OCSet2 Ph_En2 PWM2 VCC VOUT3 PWM Ph_En OCSet Θ JA = 36 C/W Θ JC = C/W *Expsed pad n underside is cnnected t a cpper pad thrugh vias fr 4-layer PCB bard design January 28, 203 2

3 ecmmended Operating Cnditins Symbl Definitin Min Max Units Vcc Supply Vltage V Fs Operating frequency khz Tj Junctin temperature C Electrical Specificatins Unless therwise specified, these specificatin apply ver Vcc=2V, 0 C<Tj<05 C Parameter SYM Test Cnditin Min TYP MAX Units Output Vltage Accuracy FB, FB2 Vltage V FB 0.8 V Accuracy - + % Supply Current V CC Supply Current (Static) Under Vltage Lckut -40 C<Tj< 25 C, Nte % I CC (Static) SS=0V, N Switching ma V CC -Threshld V CC _UVLO() Supply ramping up V V CC _UVLO(F) Supply ramping dwn V V CC -Hysteresis Vcc-Hyst Supply ramping up / dwn mv Enable-Threshld En_UVLO() Supply ramping up.2.4 V En_UVLO(F) Supply ramping dwn V Enable-Hysteresis En_Hyst Supply ramping up / dwn 00 mv 5V_sns-Threshld 5V_sns_UVLO() Supply ramping up V 5V_sns_UVLO(F) Supply ramping dwn V 5V_sns_Hysteresis 5V_sns_Hyst Supply ramping up / dwn 00 mv Ph_En, PWM,2 Drive Current I(drive) 0 ma Input Vltage High V ut3 - V Input Vltage Lw 0.8 V Internal egulatr Output Accuracy V ut3 7.6V<Vcc<4.5V V Isurce=0 t 200mA Output Curret I 200 ma Oscillatr Frequency F S t=62k khz Frequency ange Fs(range) See Figure khz amp Amplitude Vramp Nte.25 V Min Duty Cycle Dmin Fb=V 0 % Min Pulse Width Dmin(ctrl) F S =300kHz, Nte 50 ns Max duty Cycle Dmax F S =300kHz, Fb=0.6V 85 % Sync Frequency ange 20% abve free running Freq 2400 khz Sync Pulse Duratin ns Sync High Level Threshld Sync Lw Level Threshld Nte 2 V Nte 0.8 V January 28, 203 3

4 Electrical Specificatins Parameter SYM Test Cnditin Min TYP MAX Units Errr Amplifier Fb Vltage Input Bias Current IFB SS=3V A E/A Surce/Sink I (surce/sink) A Current Transcnductance gm, mh Input ffset Vltage Vffset Fb t Vref mv VP Vltage ange VP Nte 0 V CC -2 V Track Vltage ange Sft Start/SD Track Nte 0 V CC -2 V Sft Start Current ISS Surce / Sink A Shutdwn Output Threshld Over Current Prtectin SD 0.25 V OCSET Current I OCSET A Hiccup Current IHiccup Nte 3 ua Hiccup Duty Cycle Hiccup(duty) I Hiccup /I OCSET, Nte 5 % Over Vltage Prtectin OVP Trip Threshld OVP(trip).Vref.5Vref.2Vref V OVP Fault Prp OVP(delay) Output Frced t 5 s Delay.25Vref OVP_Output Current 0 20 ma Thermal Shutdwn Thermal shutdwn Nte 35 Thermal shutdwn Hysteresis Seq Input Seq Threshld Seq On Off Pwer Gd Vsen Lwer Trip pint PGd Output Lw Vltage Nte: Guaranteed by design but nt test in prductin Vsen(trip) Vsen amping Dwn 0.8Vref 0.9Vref 0.95Vref V PG(vltage) I PGd =2mA V Nte2: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin C C V January 28, 203 4

5 Pin# Pin Name Descriptin I3623MPbF PGd Pwer Gd pin ut put fr channel, pen cllectr. This pin needs t be externally pulled high 2 PGd2 Pwer Gd pin ut put fr channel 2, pen cllectr. This pin needs t be externally pulled high 3 Track2 Sets the type f pwer up / dwn sequencing (ratimetric r simultaneusly). If it is nt used cnnect this pin t Vut3. 4 VSEN2 Sense pin fr OVP2 and Pwer Gd 2, Channel 2. If it is nt used cnnect this pin t Gnd. 5 OVP-Output OVP utput, ges high when OVP cnditin ccurs 6 Fb2 Inverting inputs t the errr amplifier2. If it is nt used cnnect this pin t Gnd 7 Cmp2 Cmpensatin pin fr the errr amplifier2 8 SS2/SD2/Mde Sft start fr channel 2, can be used as SD pin. Flat this pin fr current share single utput applicatin. If it is nt used cnnect this pin t Gnd. 9 OCSet2 Current limit set pint fr channel2 0 Ph_En2 Phase Enable pin fr channel2 PWM2 PWM utput fr channel2 2 Vcc Supply Vltage fr the internal blcks f the IC 3 Vut3 Output f the internal regulatr 4 PWM PWM utput fr channel 5 Ph_En Phase Enable pin fr channel 6 OCSet Current limit set pint fr Channel 7 SS/SD Sft start fr channel, can be used as SD pin 8 Cmp Cmpensatin pin fr the errr amplifier 9 Fb Inverting input t the errr amplifier 20 OCGnd Grund cnnectin fr OCset circuit 2 VSEN Sense pin fr OVP and Pwer Gd, Channel 22 Track Sets the type f pwer up / dwn sequencing (ratimetric r simultaneusly). If it is nt used cnnect this pin t Vut3. 23 Sync External synchrnizatin pin 24 Seq Enable pin fr tracking and sequencing 25 VP Nn inverting input f errr amplifier 26 VP2 Nn inverting input f errr amplifier2. If it is nt used cnnect this pin t Gnd. 27 VEF eference Vltage 28 SGnd Signal Grund 29 Gnd IC s Grund 30 t Cnnecting a resistr frm this pin t grund sets the Switching frequency 3 Enable Enable pin, recycling this pin will rest OV, SS and Prebias latch 32 5V_sns Sensing either external 5V r the Vut3 January 28, 203 5

6 Blck Diagram SS 3uA Enable Vcc SS2 / SD/MODE SS / SD PO 25uA 25uA 64uA Max 64uA Mde SS2 0.8V 5V_Sns Mde Cntrl Bias Generatr UVLO PO Mde 3V SS 0.8V SS2 Mde PO Hiccup Cntrl OC OC2 SS2 3uA 20uA 20uA OCGnd OCSet OCGnd OCSet2 Track VP Errr Amp PO Mde OC,2 SS,2 T.S Fault Ctrl Ctrl Ctrl2 Fb Cmp t Sync amp Thermal Shutdwn 0.3V SS PWM PO OVP S Ctrl Q Ctrl Tri-State VOUT3 VOUT3 Ph_En PWM VEF Track2 0.8V Errr Amp2 Tw Phase Oscillatr amp2 PWM2 OVP2 Ctrl2 Tri_State VOUT3 PWM2 VP2 Fb2 Cmp2 VSEN VSEN2 PGd / OVP OVP OVP2 0.3V SS2 PO Ctrl2 Q S VOUT3 Ph_En2 PGd PGd2 Seq Sequencing SS / SD Vcc SGnd egulatr 5V_sns OVP_Output 5V_sns VOUT3 Gnd Fig. 2: Simplified blck diagram f the I January 28, 203 6

7 TYPICAL OPEATING CHAACTEISTICS VFb vs Temperature VFb2 vs Temperature Vfb (V) Vfb2 (V) Temperature (C) Temperature (C) SS Current vs Tem perature SS2 Current vs Tem perature SS Current (ua) SS2 Current (ua) Temperature (C) Temperature (C) Vcc_UVLO vs Temperature VO3 vs Temperature Vcc_UVLO (V) Temperature (C) VO3 (V) Temperature (C) January 28, 203 7

8 TYPICAL OPEATING CHAACTEISTICS IOCSET vs Tem perature IOCSET2 vs Tem perature IOCSET (ua) IOCSET2 (ua) Temperature (C) Temperature (C) GM vs Tem perature PWM FEQ 600KHz vs Temperature GM (umh) PWM Freq (KHz) Temperature (C) Temperature (C) Max Duty Cycle vs Temperature 600kHz Max Duty Cycle vs Temperature.2MHz Max Duty C y cle ( % ) Temperature (C) Max Duty C y cle ( % ) Temperature (C) January 28, 203 8

9 Circuit Descriptin THEOY OF OPEATION Intrductin The I3623 is a versatile device fr high perfrmance buck cnverters. It cnsists f tw synchrnus buck cntrllers which can be perated either in tw independent utputs mde r in current share single utput mde fr high current applicatins. The timing f the IC is prvided by an internal scillatr circuit which generates tw-80 -ut-fphase clck that can be externally prgrammed up t 200kHz per phase. The I3623 when cmbined with I s ipowi pwer stage mdules ffers a cmpact and efficient slutin where integratin and pwer density are desired. Under-Vltage Lckut The under-vltage lckut circuit mnitrs three signals (Vcc, Enable and 5V_sns). This ensures the crrect peratin f the cnverter during pwer up and pwer dwn sequence. The PWM utputs remain in the ff state whenever ne f these signals drp belw set threshlds. Nrmal peratin resumes nce these signals rise abve the set values. Figure 3 shws a typical start up sequence. V 5V_sns I3623 integrates an internal LDO fr pwering the external mdule withut need fr an external supply. Fr a crrect start up sequence the external mdule needs t be biased first prir t thecntrlleric.thev ut3 ramps up as sn as Vcc is applied but the PO (Pwer On eady) is nt enabled until the V ut3 reached the 5V threshld set by 5V_sns pin. Enable The enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by under-vltage lckut circuit. It s threshld can be externally prgrammed t desired level by using tw external resistrs, s the cnverter desn t start up until the input vltage is sufficiently high. 2V 2V 8.0V 4.7V 5.2V Vbus Vcc Vut3 5V_sns Enable 3V Vut3 OK Vcc OK Enable OK (IC's PO) SS Seq Fig. 3: Nrmal Start up, Enable threshld is externally set t V January 28, 203 9

10 Internal egulatr I3623 features an n-bard regulatr capable f surcing current up t 200mA. This integrated regulatr can be used t generate bias vltage an example f hw this can be used t pwer the ip2005a is shwn in figure 22. The utput f regulatr is prtected fr shrt circuit and thermal shutdwn. Out-f-Phase Operatin The I3623 drives its tw utput stages 80 utf-phase. In current share mde single utput, the tw inductr ripple currents cancel each ther and result in a reductin f the utput current ripple and yield a smaller utput capacitr fr the same ripple vltage requirement. Figure 4 shws tw channels inductr current and the resulting vltage ripple at utput. HDV MS Current Nrmalized (I MS /I ut ) In additin, the 80 ut f phase cntributes t input current cancellatin. This result in much smaller input capacitr s MS current and reduces the input capacitr quantity. Figure 5 shws the equivalent MS current. Single Phase 2 Phase Duty Cycle (V/Vin) Fig. 5: Input MS value vs. Duty Cycle HDV2 IL 0 DT T IL2 Mde Selectin The I3623 can perate as a dual utput independently regulated buck cnverter, r as a 2 phase single utput buck cnverter (current share mde). The SS2 pin is used fr mde selectin. In current share mde this pin shuld be flating and in dual utput mde a sft start capacitr must be cnnected frm this pin t grund t prgram the start time fr the secnd utput. Ic Fig. 4: Current ripple cancellatin fr utput I Independent Mde In this mde the I3623 prvides cntrl t tw independent utput pwer supplies with either cmmn r different input vltages. The utput vltage f each individual channel is set and cntrlled by the utput f the errr amplifier, which is the amplified errr signal frm the sensed utput vltage and the reference vltage. The errr amplifier utput vltage is cmpared t the ramp signal thus generating fixed frequency pulses f variable duty-cycle, (PWM) which are applied t the external MOSEFT drivers. Figure 23 shws a typical schematic fr such applicatin. January 28, 203 0

11 Current Share Mde This feature allws t cnnect bth utputs tgether t increase current handling capability f the cnverter t supprt a cmmn lad. In current sharing mde, errr amplifier becmes the master which regulates the cmmn utput vltage and the errr amplifier 2 perfrms the current sharing functin, figure 6 shws the cnfiguratin f errr amplifiers. In this mde I3623 make sure the master channel starts first fllwed by slave channel t prevent any glitch during start up. This is dne by clamping the utput f slave s errr amplifier until the master channel generates the first PWM signal. At n lad cnditin the slave channel may be kept ff depends n the ffset f errr amplifier. Lssless Inductr Current Sensing The I3623 uses a lssless current sensing fr current share purpses. The inductr current is sensed by cnnecting a series resistr and a capacitr netwrk in parallel with inductr and measuring the vltage acrss the capacitr, this vltage is prprtinal t the inductr current. As shwn in figure 6 the vltage acrss the inductr s DC can be expressed by: V L ( s ) ( V V in ut L ) * * sl ( ) The vltage acrss the C can expressed by: V C Cmbining equatins (),(2) and (3) result t the fllwing expressin fr V C : Usually the resistr and C are chsen s that the time cnstant f and C equals the time cnstant f the inductr which is the inductance L ver the inductr s DC ( L ). If the tw time cnstants match, the vltage acrss C is prprtinal t the current thrugh L, and L V ( s ) I * L L L ( s ) ( V V V C in ( s ) I L ut sc ) * * sc L sl * s * C ( 2 ) ( 3 ) ( 4 ) Vin Vin Q2 Q3 Q4 Master Phase IL L L + VL (s) - C 2 L2 VP2 FB2 + VC(s) - L2 Fig. 6: Lss Less inductr current sensing and current sharing C2 Slave Phase VOUT the sense circuit can be treated as if nly a sense resistr with the value L was used. If : C V ( s ) I L * C L * The mismatch f the time cnstant des nt affect the measurements f inductr DC current, but affects the AC cmpnent f the inductr current. Sft-Start The I3623 has prgrammable sft-start t cntrl the utput vltage rise and limit the inrush current during start-up. It prvides a separate Sft-start functin fr each utputs. This will enable t sequence the utputs by cntrlling the rise time f each utputs thrugh selectin f different value sft-start capacitrs. T ensure crrect start-up, the sft-start sequence initiates when the Vcc, Enable and 5V_sns rise abve their threshld and generate the Pwer On eset (PO) signal. Sft-start functin perates by surcing an internal current t charge an external capacitr t abut 3V. Initially, the sft-start functin clamps the errr amplifier s utput f the PWM cnverter. L L January 28, 203

12 Sft-Start (cnt.) During pwer up, the cnverter utput starts at zer and thus the vltage at Fb is abut 0V. A current (64uA) injects int the Fb pin and generates a vltage abut.6v (64ux25K) acrss the negative input f errr amplifier, see figure 7. The magnitude f this current is inversely prprtinal t the vltage at sft-start pin. The 28uA current surce starts t charge up the external capacitr. In the mean time, the sftstart vltage ramps up, the current flwing int Fb pin starts t decrease linearly and s des the vltage at negative input f errr amplifier. When the sft-start capacitr is arund V, the vltage at the negative input f the errr amplifier is apprximately 0.8V. As the sft-start capacitr vltage charges up, the current flwing int the Fb pin keeps decreasing. The feedback vltage increases linearly as the injecting current ges dwn. The injecting current drps t zer when sft-start vltage is arund.8v and the utput vltage ges int steady state. Figure 8 shws the theretical peratinal wavefrms during sft-start. The utput start-up time is the time perid when sft-start capacitr vltage increases frm V t 2V. The start-up time will be dependent n the size f the external sft-start capacitr. The startup time can be estimated by: SS/SD Seq Fb VP SS2/SD2 PO 64uA PO E/A 64uA 3V 3V E/A2 Fb2 VP2 Track ISS = 28uA Ihiccup = 3uA ISS2 = 28uA Ihiccup2 = 3uA Fig. 7: Sft-Start circuit fr I3623 OCP2 OCP Fr a given start up time, the sft-start capacitr (nf)canbeestimatedas: C SS Tstart 28μA. 8V V C ss 20 (A ) * Tstart ( ms ) 0. 8( V ) ( 5 ) Fr nrmal start up the Seq pin shuld be pulled high (usually can be cnnected t Vut3). Output f PO Sft-Start Vltage 64uA Current flwing int Fb pin Vltage at negative input f Errr Amp 0V.6V 3V.8V V 0uA 0.8V 0.8V Vltage at Fb pin 0V Fig. 8: Theretical peratin wavefrms during sft-start January 28, 203 2

13 Output Vltage Tracking and Sequencing The I3623 can accmmdate a full spectrum f user prgrammable tracking and sequencing ptins using Track, Seq, Enable and Pwer Gd pins. Thrugh these pins bth simple vltage tracking such as that required by the DD memry applicatin r mre sphisticated sequencing such ratimetric r simultaneusly can be implemented. The Seq pin cntrls the internal current surces t set the pwer up r dwn sequencing, tggle this pin high fr pwer up and tggle this pin lw fr pwer dwn. The Track pin is used t determine the secnd channel utput fr either ratimetric r simultaneusly by using tw external resistrs. Figure 9 shws hw these pins are cnfigured fr different sequencing mde. In general the A and B set the utput vltage fr the first utput and C and D set the utput vltage fr the secnd utput. Fr simultaneusly vs. ratimetric, E and F can be selected accrding t the table belw: Track Pin simultaneusly ratimetric E C A F D B 3V 64uA ISS = 28uA SS/SD OCP CSS PO Ihiccup = 3uA Fig. 0: atimetric Pwer up /dwn Seq V A Fb E/A B VP VEF 3V SS2/SD2 64uA ISS2 = 28uA Flating OCP2 V2 PO Ihiccup2 = 3uA Fig. : Simultaneusly Pwer Up / dwn V C D E F Fb2 Track2 VP2 Flating E/A2 The Track pin must be cnnected t Vut3 if it is nt used. Fr current share mde, high utput vltage applicatin (e.g. 5V) this pin needs t be cnnected t Vcc. Fig. 9: Sequencing using Track pin January 28, 203 3

14 Fault Prtectin The I3623 mnitrs the utput vltage fr ver vltage prtectin and pwer gd indicatin. It senses the ds(n) f lw side MOSFET fr ver current prtectin. It als prtects the utput fr prebias cnditins. Figure belw shws the IC s perating wavefrms under different fault cnditins. PO Ph_Enable 3V.8V.0V SS PWM Tri_State V 90%Vfb Set Vltage Pre_Bias Vltage PGd OCP Threshld Iut OV_Output t0 t t2 t3 t4 t5 t6 t7 t8 t9 t0 Fig. 2: Fault Cnditins t 0 t : Vcc, 5V_sns and Enable signals passed their respective UVLO threshld. Ph_Enable ges high and PWM switches high frm tri-state. Sft start sequence starts. t t 2 : Pwer Gd signal flags high. t t 3 : Output vltage ramps up and reaches the set vltage. t 4 t 5 : OC event, SS ramps dwn, Ph-Enable pulls lw and PWM tri-states. IC in Hiccup mde. t 5 t 6 : OC is remved, recvery sequence, fresh SS. t 6 t 7 : Ph_Enable ges high and PWM switches high frm tri-state. Output vltage reaches the set vltage. t 8 : OVP event. Ph_Enable is kept high and PWM is pulled lw. OVP-Output flags high t indicate OV event. t 9 t 0 : Manually recycled the Vcc after latched OVP. PreBias start up. The Ph_Enable ges high after first internal PWM pulse is generated. The PWM utput is kept in tri-state until Ph-Enable ges high. January 28, 203 4

15 Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the DS(n) f lw side MOSFET. This methd enhances the cnverter s efficiency and reduce cst by eliminating a current sense resistr. As shwn in figure 3, an external resistr ( SET ) is cnnected between OCSet pin and the drain f lw side MOSFET (Q2) which sets the current limit set pint. 22uA SS / SD 20 28uA 3uA OCP The internal current surce develps a vltage acrss SET. When the lw side MOSFET is turned n, the inductr current flws thrugh the Q2 and results a vltage which is given by: V OCSet (I OCSet OCSet ) ( DS(n) I ) L (6) Fig. 4: 3uA current surce fr discharging sft-start capacitr during hiccup The OCP circuit starts sampling current 200ns (typical) after PWM signal ges high. The OCSet pin is internally clamped t prevent false trigging, figure 5 shws the OCSet pin during ne switching cycle. Hiccup Cntrl I3623 IOCSET OCSet OCGnd SET IP200x Q Q2 L VOUT Fig. 3: Cnnectin f ver current sensing resistr The critical inductr current can be calculated by setting: I OCset * OCset V OCSet (I OCSet OCSet ) ( DS(n) I ) 0 L I SET I L( critical) OCSet I DS( n) OCSet (7) Fig. 5: OCset pin during nrmal cnditin Ch: Inductr pint, Ch2:Ldrv, Ch3:OCSet An ver current is detected if the OCSet pin ges belw grund. This trips the OCP cmparatr and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by charging and discharging the sft-start capacitr in certain slpe rate. As shwn in figure 4 a 3uA current surce is used t discharge the sft-start capacitr. The OCP cmparatr resets after every sft start cycles, the cnverter stays in this mde until the verlad r shrt circuit is remved. The cnverter will autmatically recver. During this fault cnditin the Ph_En signal is lw and PWM utput is n Tri-state, see figure 2. The value f SET shuld be checked in an actual circuit t ensure that the ver current prtectin circuit activates as expected. The I3623 current limit is designed primarily as disaster preventing, "n blw up" circuit, and desn't perate as a precisin current regulatr. When the SS2 is flating ver current n either phase wuld result t hiccup f utput vltage. January 28, 203 5

16 Ph_En and Pre-Bias Fr a crrect start up the driver sectin needs t be pwered up befre the PWM signal is applied. I3623 features a dedicated pin (Ph_En) which can be used fr this purpses. Figure 22 shws hw this pin is used t enable pwer stage mdules. During nrmal start up the PWM is in Tri-state mde until the Ph_En ges high, each channel has it s wn Ph_En pins. During the Pre-Bias start up the Ph_En is kept lw and the PWM utput is in Tri-state mde. The Ph_En will be enabled as sn as the internal PWM signal is generated. Over Vltage Prtectin Over-vltage is sensed thrugh tw dedicated sense pins V SEN,V SEN2. A separate OVP circuit is prvided fr each channel. The OVP threshld is user prgrammable and can be set by tw external resistrs. Upn vervltage cnditin f either ne f the utputs, the OVP frces a latched shutdwn n the fault utput and pulls lw the PWM signal. I3623 features an OVP utput signal, high status f this pin indicates the OVP event fr either f the channels. This pin has 0mA current capability which can be used t drive an external switch. eset is perfrmed by recycling the Vcc r Enable. Pwer Gd The I3623 prvides tw separate pen cllectr pwer gd signals which reprt the status f the utputs. The utputs are sensed thrugh the tw dedicated V SEN and V SEN2 pins. Once the I3623 is enabled and the utputs reach the set value (90% f set value) the pwer gd signals g pen and stay pen as lng as the utputs stay within the set values. These pins need t be externally pulled high. Shutdwn using Sft Start pins The utputs can be shutdwn by pulling the sftstart pin belw 0.3V. This can be easily dne by using an external small signal transistr. During shutdwn bth MOSFET drivers will be turned ff. Nrmal peratin will resume by cycling sft start pin. Operating Frequency Selectin The switching frequency is determined by cnnecting an external resistr (t) t grund. Figure 6 prvides a graph f scillatr frequency versus t. The maximum recmmended channel frequency is.2mhz. Fig. 6: Switching Frequency vs. External esistr ( t ) Frequency Synchrnizatin The I3623 is capable f accepting an external digital synchrnizatin signal. Synchrnizatin will be enabled by the rising edge at an external clck. Per channel switching frequency is set by external resistr (t). The free running frequency scillatr frequency is twice the perchannel frequency. During synchrnizatin, t is selected such that the free running frequency is 20% belw the synchrnizatin frequency. Synchrnizatin capability is prvided fr bth single utput current share mde and dual utput cnfiguratin. When unused, the sync pin will remain flating and is nise immune. Applying the external signal t the Sync input changes the effective value f the ramp signal (Vramp/Vsc). Vcs.25 ffree _ un fsync ( 8) ( eff ) Equatin (8) shws that the effective amplitude f the ramp (V sc(eff) ) is reduced after the external Sync signal is applied. Mre difference between the frequency f the Sync (f Sync ) and the free-running frequency (f Free_un ) results in mre change in the effective amplitude f the ramp signal. January 28, 203 6

17 Therefre, since the ramp amplitude takes part in calculating the lp-gain and bandwidth f the regulatr, it is recmmended nt t use a Sync frequency which is much higher than the freerunning frequency. In additin, the effective value f the ramp signal, given by equatin (8), shuld be used when the cmpensatr is designed fr the regulatr. Thermal Shutdwn Temperature sensing is prvided inside I3623. The trip threshld is typically set t 35 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSFETs. Thermal shutdwn is nt latched and autmatic restart is initiated when the sensed temperature drps t nrmal range. There is a 20 C hysteresis in the shutdwn threshld. January 28, 203 7

18 Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr I3623. The applicatin circuit is shwn in page25. V V. 8V I in 2V,( 3. 2V,max) 40A V 30mV F 600kHz s Output Vltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The Fb pin is the inverting input f the errr amplifier, which is internally referenced t 0.8V. The divider is ratied t prvide 0.8V at the Fb pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: 6 V VEF ( 9) 5 When an external resistr divider is cnnected t the utput as shwn in figure 7. I3623 Fb Fig. 7: Typical applicatin f the I3623 fr prgramming the utput vltage Equatin(9)canberewrittenas: VOUT Vref ( 0) V V ref Fr the calculated values f 5 and 6 see feedback cmpensatin sectin. 6 5 Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. The start-up time f the cnverter can be calculated by using: C 20A * T ( ) SS start Where T start is the desired start-up time (ms) Fr a start-up time f 5ms, the sft-start capacitr will be 0.uF. Chse a ceramic capacitr at 0.uF. Input Capacitr Selectin The 80 ut f phase will reduce the MS value f the ripple current seen by input capacitrs. This reduces numbers f input capacitrs. The input capacitrs must be selected that can handle bth the maximum ripple MS at highest ambient temperature as well as the maximum input vltage. The MS value f current ripple fr duty cycle under 50% is expressed by: 2 2 I D D I D D 2I I D D - -( ) I MS Where: -I MS is the MS value f the input capacitr current -D and D 2 are the duty cycle fr each channel -I and I 2 are the utput current fr each channel Fr I=40A and D=0.3, the I MS = 7.8A. Ceramic capacitrs are recmmended due t their peak current capabilities, they als feature lw ES and ESL at higher frequency which enhance better efficiency, Use 5x22uF, 6V ceramic capacitr frm TDK (C3225X5C226M). Fr the single utput applicatin when the duty cycle is larger than 50% the fllwing equatin can be used t calculate the ttal MS value input capacitr current: I MS I O 2D D 2 2D D January 28, 203 8

19 Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. Lw inductr value causes large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f inductr value can be reduced t desired maximum ripple current in the inductr ( i ). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. Fr the buck cnverter, the inductr value fr desired perating ripple current can be determined using the fllwing relatin: Output Capacitr Selectin The vltage ripple and transient requirements determines the utput capacitrs types and values. The criteria is nrmally based n the value f the Effective Series esistance (ES). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents, these cmpnents can be described as: V V V ( ES) ( ES) I L V * ES ( ESL) V ( C) (4) i V V L in ; t t D F s V ( ESL) Vin * ESL L Where: Fr 2-phase single utput applicatin the inductr ripple current is chsen between 0-40% f maximum phase current If V in L = 0.37uH L V Output Vltage i Inductr ripple current F Switching frequency s t Turn n time D Duty cycle V V i * F V V ( ) in 3 in s Maximum input vltage i 35%( I ), then the utput inductr will be: The Panasnic ETQP4L36WFC (L =0.34uH, 24A, L =.mohm) prvides a lw prfile inductr suitable fr this applicatin. Use the fllwing equatin t calculate C 2 and 2 fr current sensing: 2 * C 2 L This results t C 2 =0.33uF and 2 =.K L V V ( C) IL 8* C * F Output vltage ripple I Inductrripple current L s Since the utput capacitr has majr rle in verall perfrmance f cnverter and determine the result f transient respnse, selectin f capacitr is critical. The I3623 can perfrm well with all types f capacitrs. As a rule the capacitr must have lw enugh ES t meet utput ripple and lad transient requirements, yet have high enugh ES t satisfy stability requirements. The gal fr this design is t meet the vltage ripple requirement in smallest pssible capacitr size. Therefre ceramic capacitr is selected due t lw ES and small size. Panasnic ECJ2FB0J226M (22uF, 6.3V, X5 and EIA 0805 case size) is a gd chice. In the case f tantalum r lw ES electrlytic capacitrs, the ES dminates the utput vltage ripple, equatin (4) can be used t calculate the required ES fr the specific vltage ripple. January 28, 203 9

20 Feedback Cmpensatin The I3623 is a vltage mde cntrller; the cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed lp transfer functin with the highest 0dB crssing frequency and adequate phase margin (greater than 45 ). The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure 8). The resnant frequency f the LC filter expressed as fllws: FLC (5) 2 L C figure 6 shws gain and phase f the LC filter. Since we already have 80 phase shift just frm the utput filter, the system risks being unstable. Fig. 8: Gain and Phase f LC filter The I3623 s errr amplifier is a differential-input transcnductance amplifier. The utput is available fr DC gain cntrl r AC phase cmpensatin. The E/A can be cmpensated either in type II r typeiii cmpensatin. When it is used in typeii cmpensatin the transcnductance prperties f the E/A becme evident and can be used t cancel ne f the utput filter ples. This will be accmplished with a series C circuit frm Cmp pin t grund as shwn in figure 9. This methd requires that the utput capacitr shuld have enugh ES t satisfy stability requirements. In general the utput capacitr s ES generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ES zer f the utput capacitr expressed as fllws: FES (6) 2 * ES* C VOUT 6 5 VEF H(s) db Fb Gain(dB) E/A Cmp Ve The transfer functin (Ve/V) is given by: The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: The gain is determined by the vltage divider and E/A s transcnductance gain. First select the desired zer-crssver frequency (F): 4 Frequency C9 FZ Fig. 9: TypeII cmpensatin netwrk and its asympttic gain plt H( s) g m 5 * 5 s4c * sc9 Use the fllwing equatin t calculate 4 : Vsc * F * FES *( 5 6) 4 2 Vin * FLC * 5 * gm Where: V in = Maximum Input Vltage V sc = Oscillatr amp Vltage F = Crssver Frequency F ES = Zer Frequency f the Output Capacitr F LC = esnant Frequency f the Output Filter g m = Errr Amplifier Transcnductance 6 5 Hs gm * * Fz (9) 2 * * C ES /5 ~/0 Fs F F and F * CPOLE (7) (8) (20) January 28,

21 T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: F 75% F z LC Fz 0.75* 2 L * C (2) Using equatins (9) and (2) t calculate C9. C9 2 * * F 4 z ZIN 8 C0 VOUT 6 5 Fb 7 E/A C2 C Zf Ve Cmp One mre capacitr is smetimes added in parallel with C 9 and 4. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: FP C * C 9 POLE 2 * * 4 C C POLE The ple sets t ne half f switching frequency which results in the capacitr C POLE : C POLE * * F Fs Fr FP 2 4 Fr a general slutin fr uncnditinally stability fr any type f utput capacitrs, in a wide range f ES values we shuld implement lcal feedback with a cmpensatin netwrk (typeiii). The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 20. In such cnfiguratin, the transfer functin is given by: V g Z e m f V g Z The errr amplifier gain is independent f the transcnductance under the fllwing cnditin: g m * Z By replacing Z in and Z f accrding t figure 5, the transfrmer functin can be expressed as: H( s) s ( C C 6 f and 2 s g m 9 m C 9 * Z IN in * * F ( s7c) * sc0 6 8 * ) C * C 2 s * ( s C 7 8 C C 2 4 s (22) 0 ) H(s) db Gain(dB) VEF FZ FZ2 FP2 FP3 Fig. 20: Cmpensatin netwrk with lcal feedback and its asympttic gain plt As knwn, transcnductance amplifier has high impedance (current surce) utput, therefre, cnsider shuld be taken when lading the E/A utput. It may exceed its surce/sink utput current capability, s that the amplifier will nt be able t swing its utput vltage ver the necessary range. The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: F F F F F P P 2 P 3 z z2 0 2 * * C C 2 * 7 C 2 * * C 7 2 * C * C C Crss ver frequency is expressed as: F * C * * C 7 2 * ( ) 2 * C V * V in sc 8 * 2 * L * C 0 * 6 Frequency January 28, 203 2

22 Based n the frequency f the zer generated by utput capacitr and its ES versus crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f crssver frequency. Cmpensatr type F ES vs. F Output capacitr TypII(PI) F LC <F ES <F <F s/2 Electrlytic, Tantalum TypeIII(PID) Methd A TypeIII(PID) Methd B F LC <F <F ES <F s/2 F LC <F <F s/2 <F ES Tantalum, ceramic Ceramic Table- The cmpensatin type and lcatin f F ES versus F The details f these cmpensatin types are discussed in applicatin nte AN-043 which can be dwnladed frm I Web-Site. Fr this design we have: V in =3.2V V =.8V V sc =.25V V ref =0.8V g m =2800umh L =0.34uH, DC=.mOhm C =5x22uF, ES= 0.33mOhm F s =600kHz These result t: F LC =5kHz F ES =.46MHz F s/2 =300kHz Select crssver frequency: F =00kHz /5 ~/0 Fs F F and F * ES Since: F LC <F <F s/2 <F ES, typeiii methd B is selected t place the ple and zers. The fllwing design rules will give a crssver frequency apprximately ne-sixth f the switching frequency. The higher the band width, the ptentially faster the lad transient respnse. The DC gain will be large enugh t prvide high DC-regulatin accuracy (typically -5dB t -2dB). The phase margin shuld be greater than 45 fr verall stability. Desired Phase Margin: F F F F C C C Z2 Z2 P2 P2 Sin F * Sin kHz Sin F * Sin kHz Select: F 7 2 g CalculateC 2 0 m 2 * F 2 * F 2 * F * L * C * V Select: C Z Calculate, 8 2 * C 6 2 * C 0. 5 * F ; 0. 72K ; 0 7 Z P3,C * ; C * 0. 68nF * F * F 7 7 P2 Z2 andc ; C in Z2 2 * V and and Select: 0K.9nF, Select: C 53pF, ; C ; 0. 63K, 8 : F 0.5* F Select: C 0. 67nF, ; 8. 05K, 8 sc 5 0 : 6 0 max P3 7 3 s 2.2nF 47pF Select: 0. 68K 8 Select: 8. 06K 6 January 28, 203 Vref 5 V V ref * ; 6. 45K, 6 5 Select: 6. 49K 5 22

23 Cmpensatin fr Current Lp (slave channel) The slave errr amplifier is differential transcnductance amplifier, in 2-phase cnfiguratin the main gal fr the slave channel feedback lp is t cntrl the inductr current t match the master channel inductr current as well prvides highest bandwidth and adequate phase margin fr verall stability. The fllwing analysis is valid fr bth using external current sense resistrs and using DC f inductr. The transfer functin f pwer stage is expressed by: IL2( s) Vin G( s) ( 23) V sl * V Where: V in =Input vltage L 2 =Output inductr V sc =Oscillatr Peak Vltage e sc As shwn the G(s) is a functin f inductr current. The transfer functin fr cmpensatin netwrk is given by equatin (24), when using a series C circuit as shwn in figure2. IL2 2 Select a zer frequency fr current lp (F 2 ).25 times larger than zer crss frequency fr vltage lp (F ). O2 Frm (25), 2 can be expressed as: V in =3.2V V sc =.25V g m =2800umh L 2 =0.34uH s =DC=.mOhm F 2 =25kHz F. 25% * F Vin H( FO 2) gm * s * 2 * ( 25) 2 * F * L * V 2 g m * s This results t : 2 =8.2K O2 The pwer stage f current lp has a dminant ple (Fp) at frequency expressed by: O 2 2 * FO 2 * L * V 2 in sc * V sc ( 26) L2 Fb2 S2 Vp2 S L E/A2 Cmp2 Ve 2 C2 eq FP 2 * L Where eq is the ttal resistance f the pwer stage which includes the ds(n) f MOSFET switches, the DC f inductr and shunt resistance (if it used). 2 IL Fig. 2: The Cmpensatin netwrk fr current lp Ve ( s) s sc2 2 D( s) gm * * ( 24) s2 s2 sc 2 The lp gain functin is: H( s) H ( s) G( s) * D( s) * s2 * g m * s s2 s2 s 2C2 Vin * * sc2 sl2 * V sc eq =9.4mOhm Set the zer f cmpensatr at 0 times the dminant ple frequency F P, the cmpensatr capacitr, C2 can be expressed as: C 2 =0.47nF eq ds( n) F 0 * F z C2 2 * * F All design shuld be tested fr stability t verify the calculated values. P 2 L z s January 28,

24 Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr ( SET ) frm drain f lw side MOSFET t the OCSet pin. The resistr can be calculated by using equatin (7). The DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrse case peratin. This resistr must be placed clse t the IC, place a small ceramic capacitr frm this pin t grund fr nise rejectin purpses. I SET I L( critical) DS( n) 2.3m m ISET I( LIM ) 20A.5 30A (50%ver nminal utput current) 5.K OCSet I OCSet 3 4 DS( n) OCSet (7) Layut Cnsideratin The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Start t place the pwer cmpnents, make all the cnnectin in the tp layer with wide, cpper filled areas. The inductr, utput capacitr shuld be clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place input capacitrs as clse as pssible t the pwer mdule s input pin. Add capacitrs as necessary t reduce the ES t desired levels. The feedback part f the system shuld be kept away frm the inductr and ther nise surces, and be placed clse t the IC. In multilayer PCB use ne layer as pwer grund plane and have a cntrl circuit grund (analg grund), t which all signals are referenced. The gal is t lcalize the high current path t a separate lp that des nt interfere with the mre sensitive analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The expsed pad f IC shuld be cnnected t analg grund. Layut guidelines fr IP2005A can be fund in the prduct data sheet. January 28,

25 Typical Applicatin Fig. 22: Applicatin circuit fr Single Output January 28,

26 Typical Applicatin Fig. 23: Applicatin circuit fr Dual Output January 28,

27 (I3623M) MLPQ Package; 5x5-32 Lead I3623MPbF Pin Lcatin Lg 3623M LYWWP Part Number Date Cde (L = Assem. Lcatin, Y = Year, WW = Wrk Week, P = PbF) Part MarkingI WOLD HEADQUATES: 233 Kansas St., El Segund, Califrnia 90245, USA Tel: (30) TAC Fax: (30) This prduct has been designed and qualified fr the Industrial market. Visit us at fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 9/29/ January 28,