Pole-Zero-Cancellation Technique for DC-DC Converter

Transcription

1 1 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter Seiya Abe, Tshiyuki Zaitsu, Satshi Obata, Masahit Shyama and Tamtsu Ninmiya Internatinal Centre fr the Study f East Asian Develpment, Texas Instruments Japan Ltd., Kyushu University, Nagasaki University, Japan 1. Intrductin Many types f electric equipments are digitized in recent years. Hwever, the cnfiguratin f switch mde pwer supply is still nly analg circuit because the analg circuit is held dwn t lw cst. The digitized system is perated n the basis f a prcessr. When the switch mde pwer supply is treated as a part f the system, it is difficult that switch mde pwer supply inhabit alne in the system as the analg-circuit. Therefre, the digitizatin f the switch mde pwer supply is necessary t harmnize with ther electrnic circuits in the system. S far, varius examinatins have been discussed abut digitally cntrlled switch mde pwer supplies[1-5]. Hwever, imprtant parameters such as the switching frequency were impractical because the perfrmance f prcessr was nt s gd. Recently, due t the develpment f the semicnductr manufacture technlgy, the perfrmance f prcessr such as DSP and FPGA is develped remarkably. Hence, the expectatin f the practical realizatin in the digitally cntrlled switch mde pwer supply becmes higher. S far, in many case n digitally cntrlled switch mde pwer supply, the cntrl system is cnstructed by very cmplicated, difficult mdern cntrl thery (nnlinear cntrl thery) such as adaptive cntrl r predictive cntrl. Mrever, als in the mst ppular and easiest cntrl methd such as PID cntrl, the design methd is nt s clear, and the ptimal design is difficult[6, 7]. On the ther hand, there are tw methds f cntrller design. One is the digital direct design. The ther is the digital redesign. The digital redesign methd cnverts the analg cmpensatr which is designed n s-regin int digital cmpensatr. The digital redesign methd has sme advantages. Fr example, the cntrl system is designed frm classical cntrl thery (linear cntrl thery). Therefre, many experiences and design techniques f the cnventinal analg cmpensatr can be utilized. Mrever, frm the practical stance, the digital redesign methd is mre realistic than digital direct design. This paper investigates the digitally cntrlled switch mde pwer supply by means f classical cntrl thery. Especially, the interesting cntrl technique which is cancelled the transfer functin f the cnverter by using ple-zer-cancellatin technique is intrduced. This technique is very simple and stability design f cnverter system is very easy.

2 19 Advances in PID Cntrl Furthermre, the arbitrary frequency characteristics can be created by intrducing a new frequency characteristic. Here, the design methd and system stability f the prpsed cntrl technique is examined by using buck cnverter as a simple example.. Cnverter analysis Fr the design f the cntrl system, it is necessary t grasp crrectly the characteristics f the cnverter in detail. The buck cnverter as a cntrlled bject is shwn in Fig. 1. The dynamic characteristics f buck cnverter can be derived by applying the state space averaging methd[8,9]. The transfer functin f duty t utput vltage f buck cnverter is derived fllwing equatin; G dv V () s Gdv() s () s Ds () Ps () (1) where; s Ps () s 1 () s R Gdv() s 1 Vi esr R rl (3) R rl LC R r c (4) Fig. 1. Synchrnus buck cnverter. c L c LC Rr r Rr LC R r R r c L (5) 1 esr (6) Cr c Figure shws the blck diagram f analg system. Frm, Fig., the lp gain f analg cntrlled cnverter can be derived fllwing equatin;

3 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 191 V () s Gdv() s Ts () Gc() skkspwm V () s Ps () * where; Gc(s) : Transfer functin f phase cmpensatr K : DC gain f errr amp. Ks : Sense gain f utput vltage PWM : transfer gain f vltage t duty (7) Fig.. Blck diagram f analg system. In rder t evaluate the validity f the analytical result, the experimental circuit is implemented by means f the specificatins and parameters shwn in Table 1. Symbl Descriptin Value V i Input Vltage 1V V /I Lad Cnditin.5V/5A L Filter Inductr H C Filter Capacitr 47F r L DC Resistance f L 1m r c ESR f C 1m R Lad Resistance 1 K s Sense Gain.3 K Feedback DC Gain 5 PWM PWM Gain.5 fs Switching Frequency 1kHz Table 1. Circuit parameters and specificatins. Figure 3 shws the lp gain f the buck cnverter with p-cntrl in analg cntrl. As shwn in Fig. 3, the analytical and experimental results are agreed well. Hwever, as shwn in Fig. 4, the big difference is shwn in phase characteristics at high frequency side between analg cntrl and digital cntrl.

4 19 Advances in PID Cntrl Gain (Experiment) Gain (Analysis ) Phase (Experiment) Phase (Analysis) 1.E+ 1.E+3 1.E+4 1.E+5 Fig. 3. Frequency respnse f lp gain (analg cntrl) Gain (Analg) Gain (Digital) Phase (Analg) Phase (Digital) E+ 1.E+3 1.E+4 1.E+5 Fig. 4. Frequency respnse cmparisn f analg cntrl and digital cntrl (Experiment). In digital cntrl system, the utput vltage as a detected signal is cnverted t digital signal by AD cnverter, after that the cnverted signal is calculated by DSP. Next, the calculated signal decides the duty rati f next switching perid. Hence, the infrmatin f the utput vltage as the detected signal at certain switching perid is reflected int the duty rati f the next switching perid. Therefre, the dead time element He(s) is included int the cntrl lp as shwn in Fig. 5. Frm Fig. 5, the lp gain f digital cntrlled system can be derived fllwing equatin; where; V () s Gdv() s Ts () Gc() she() skkspwm V () s Ps () * (8) st sample H () s e (9) e

5 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 193 Gc(s) : Transfer functin f phase cmpensatr K : DC gain f errr amp. Ks : Sense gain f utput vltage PWM : transfer gain f vltage t duty He(s) : Dead time cmpnent f digital cntrller : Sampling perid Figure 6 shws the frequency respnse f dead time element He(s). As shwn in Fig. 6, the gain characteristic des nt depend n frequency and it is cnstant. Fig. 5. Blck diagram f digital system Gain - Phase -3 1.E+ 1.E+3 1.E+4 1.E Fig. 6. Frequency respnse f dead time element He(s). On the ther hand, phase characteristic depends n frequency. The phase is rtated arund 18 degrees at Nyquist frequency (=f/), and it is rtated arund 36 degrees at switching

6 194 Advances in PID Cntrl frequency (sampling frequency). Frm these results, the phase is drastically rtated at high frequency side by the influence f dead time element He(s). In rder t evaluate these discussins, the experimental circuit is implemented by means f the specificatins and parameters shwn in Table 1. Mrever, the experimental result is cmpared with analytical result. Figure 7 shws the lp gain f the buck cnverter with p-cntrl in digital cntrl. As shwn in Fig. 7, the analytical and experimental results are agreed well. In analg cntrl system, the phase characteristic f frequency respnse is imprved at higher frequency side by the influence f ESR-Zer as shwn in Fig. 4, and the system has stable peratin. On the ther hand, in digital cntrl system, the phase characteristic f frequency respnse is drastically rtated by the influence f the dead time element He(s) as shwn in Fig. 7. As a result, the phase margin disappears, and the system becmes unstable. In digital cntrl system, the phase rtatin is larger than analg cntrl system by the influence f the dead time element He(s), s the phase cmpensatin is necessary t keep the system stability Gain (Experiment) Gain (Analysis) Phase (Experiment) Phase (Analysis) 1.E+ 1.E+3 1.E+4 1.E+5 Fig. 7. Frequency respnse f lp gain (digital cntrl) Cnventinal phase cmpensatin (Phase lead-lag cmpensatin) The phase cmpensatin is usually used t imprve the system stability. There is varius phase cmpensatin. Here, the phase lead-lag cmpensatin is used as the mst ppular cmpensatin. The digital filter is designed by digital redesign methd. The transfer functin f phase lead-lag cmpensatin is given by fllwing equatin; s s Kc 1 1 ve z1 z Gc() s * v s s 1 1 p1 p (1)

7 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 195 The digital filter can be realized by means f the bilinear transfrmatin. 1 z s T 1 z sample 1 1 (11) 1 1 c () ve z B z B B k * 1 v z A z A1A G z (1) where; p1 p k K c (13) z1 z 4 p1 p p1p A (14) 8 A (15) 1 p 1 p 4 p1 p p1p A (16) 4 z1 z z1z B (17) 8 B (18) 1 z 1 z 4 z1 z z1z B (19) The determinatin f the cmpensatr parameter is varius. Here, these parameter decide frm phase margin. Figure 8 shws the analytical result f lp gain frequency respnse with phase lead-lag cmpensatin. Where, Kc=1, fp1=.3hz, fz1=1.3khz, fp=khz, fz=1.5khz. As shwn in Fig. 8, this system has the stable peratin, and then the bandwidth is arund 5.5kHz, the phase margin is arund 45 degrees. Figure 9 shws the experimental result f lp gain frequency respnse with phase lead-lag cmpensatin. In this case, the bandwidth is arund 5kHz, and the phase margin is arund 45 degrees. Mrever, the analytical and experimental results are agreed well. Thus, the bservatin f cntrl bject frequency respnse is needed in classical cntrl thery (linear cntrl thery).

8 196 Advances in PID Cntrl Gain Phase 1.E+ 1.E+3 1.E+4 1.E Fig. 8. Frequency respnse f lp gain with phase lead-lag cmpensatin (analytical result) Gain Phase 1.E+ 1.E+3 1.E+4 1.E Fig. 9. Frequency respnse f lp gain with phase lead-lag cmpensatin (experimental result). Mrever, much experience and knwledge are needed fr cntrller design, because many parameters in cmpensatr shuld be decided. Therefre, the design methd is nt s clear and depends n knwledge and experience, and the ptimal design is difficult. The cntrller design becmes very simple if the cntrller design is enabled withut cnsidering the frequency respnse f the cnverter as the cntrl bject.

9 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter Principle f PZC technique Reductin f the phase rtatin is very imprtant fr system stability. Especially in the secnd rder system, the phase is drastically rtated arund 18 degrees at resnance peak. The stability f the system is imprved remarkably if the phase rtatin can be reduced. This paper prpses the cntrl technique which is cancelled the transfer functin f the cnverter pwer stage by means f ple-zer-cancellatin methd. The phase rtatin and gain change can be suppressed by cancelling the cnverter pwer stage characteristics. Furthermre, new characteristic can be designed in the system as the arbitrary transfer functin. Figure 1 shws the blck diagram f cnverter system including the ple-zercancellatin technique. Fig. 1. Blck diagram f digital system with PZC cntrl. Frm Fig. 1, the transfer functin f cmpensatr part is given fllwing equatin; G () s G () s G () s () c new pzc The Gnew(s) is the arbitrary transfer functin. This transfer functin decides the frequency respnse f cnverter system. Here, the Gnew(s) is defined as first-rder lw pass filter. G new () s Kc s 1 In buck cnverter case, the resnance peak and ESR-Zer are cancelled. The phase rtatin f 18 degree is reduced by cancelling resnance peak. The transfer functin f the plezer-cancellatin Gpzc(s) is given fllwing equatin; c (1)

10 198 Advances in PID Cntrl G pzc s s 1 () s s 1 Mrever, the transfer functin f the cmpensatr is given fllwing equatin; esr () G () s K c c s s 1 s s 1 1 esr c The digital filter can be realized by means f the bilinear transfrmatin (Eq. 11) as fllwing equatin; (3) where; 1 1 * 1 1 c ( ) ve z B z B B G z k v z A z A A (4) esr c k K c (5) 4/ 1/ esr 1/ c A 1 (6) T esr c esr c 1 sample 8/ A (7) 4/ 1/ esr 1/ c A 1 (8) T sample sample 4/ 4 / B 1 (9) T 8/ 1 B (3) 4/ 4 / B 1 (31) T Figure 11 shws the frequency respnse f PZC part Gpzc(s). As shwn in Fig. 11, the ant resnance peak is appeared at the same frequency f pwer stage frequency respnse. Figure 1 shws the analytical result f the lp gain frequency respnse with PZC technique. Where, Kc=5, fc=.1hz. As shwn in Fig. 1, this system has the stable peratin, and then the bandwidth is arund 4Hz, the phase margin is arund 88 degrees. sample

11 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 199 Mrever, the resnance peak and ESR-Zer are cmpletely cancelled, and this system becmes 1st rder respnse. Frm these results, the cnverter frequency respnse is cmpletely cancelled by the influence f PZC part, and the new characteristic is created (1st rder characteristic). Figure 13 shws the experimental result f lp gain frequency respnse with PZC technique. In this case, the bandwidth is arund 4Hz, and the phase margin is arund 89 degrees. Mrever, the analytical and experimental results are agreed well Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 11. Frequency respnse f PZC part (analytical result) Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 1. Frequency respnse f lp gain with PZC technique (analytical result).

12 Advances in PID Cntrl Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 13. Frequency respnse f lp gain with PZC technique (experimental result). 5. Optimal design f the new transfer functin The first rder lw pass filter as Gnew(s) is designed fr system stability at previus sectin. Here, the ptimizatin f the Gnew(s) is cnsidered. At first, the stability margin is investigated. In this case, the integratr is included, s the phase starts -9deg. In additin, the phase is shifted by the influence f dead time element He(s) as shwn in Fig. 14. Therefre, when the crssver frequency sets t f BW, the phase margin can be derived as fllws; 36 Pm 9 fbw (3) fs When f=fs/4, the phase margin becmes zer. Next, the gain margin is investigated. In this case, this system has 1st rder respnse, s the slpe f gain curve becmes -db/dec. Therefre, the gain margin can be derived fllwing equatin by using the crssver frequency f BW and fs/4. fs Gm lg 1 (3) 4 fbw Frm eq. (31), (3), it is clarified that the phase margin and gain margin is autmatically decided by the determinatin f crssver frequency f BW. The Gnew(s) is ptimized by means f crssver frequency f BW. The Gnew(s) has tw cefficients, c and Kc. The cefficient f c is decided frm Kc and f BW. The steady state errr depends n the utput impedance, especially the lw frequency cmpnent f the clsed lp utput impedance Zc. The pen lp utput impedance can be derived by applying the state space averaging methd as fllwing equatin; slcrslcrr r Z() s slcscr r 1 c L c L L c (33)

13 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 1 Mrever, the clsed lp utput impedance given frm eq. (7) and (33). Z() s Zc() s (34) 1 Ts ( ) Therefre, the lw frequency cmpnent f the clsed lp utput impedance Zc can be derived apprximately as fllwing equatin. 6 K45 DC fc -db/dec f BW f s /4 GM Gain Phase PM E+ 1.E+1 1.E+ Frequency 1.E+3 (Hz) 1.E+4 1.E+5 Fig. 14. Frequency respnse f lp gain with PZC technique fr ptimal filter design. rl Zc (35) K KsKc PWMVin The steady state errr f the utput vltage V is given by Zc prduct utput current variatin I. Therefre, the cefficient Kc can be derived by determining the tlerance f the utput vltage variatin. Frm eq. (35), the cefficient f Kc can be derived apprximately as fllwing equatin rl Kc Z KK PWMV c s in Mrever, the ttal DC gain K DC f lp gain T(s) becmes fllwing equatin. (36) rl KDC lg1 KKs Kc PWMVin lg1 (37) Zc The bandwidth f BW and the cefficient f Kc are decided, and the slpe f lp gain is - db/dec. Frm these parameters, the ttal DC gain K DC can be expressed by using f BW and fc as fllwing equatin. K DC fbw lg1 fc (38)

14 Advances in PID Cntrl Frm eq. (37), (38), the cefficient f fc is given as fllwing equatin. Zc fc fbw (39) rl Frm mentined abve discussin, the cefficients fc and Kc is ptimized. Here, the crssver frequency f BW is set t 1kHz. In this case, the phase margin is arund 54 degrees and the gain margin is rund 8dB. Mrever, the each cefficient is Kc=4, fc=5hz. Where, the utput impedance is set t arund.5m. Figure 15 shws the analytical results f the lp gain frequency respnse with ptimal filter design. As shwn in Fig. 15, the bandwidth is arund 1kHz, the phase margin is arund 5 degrees. Figure 16 shws the experimental results f the lp gain frequency respnse with ptimal filter design. In this case, the bandwidth is arund 1kHz, the phase margin is arund 5 degrees. Mrever, the analytical and experimental results are agreed well Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 15. Optimal design f lp gain (analytical result) Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 16. Optimal design f lp gain (experimental result).

15 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter 3 Next, the transient respnse f the cnventinal phase lead-lag cmpensatin and the PZC technique are measured using experimental circuit f.5v/5a during the step lad transitin frm 1A t 4A (1A/s). Figure 17, 18 shws the transient respnse f the cnventinal phase lead-lag cmpensatin and PZC technique, respectively. In phase leadlag cmensatin case, the utput vltage drp is arund 3mV and the transient time t the steady state is arund 4s. On the ther hand, in the case with PZC technique, the utput vltage drp is arund 16mV and the transient time t the steady state is arund s as shwn in Fig. 15, and the transient respnse is imprved. Fig. 17. Transient respnse (Phase lead-lag cmpensatin). Fig. 18. Transient respnse (PZC technique). 6. Parameter tlerance Here, the actual system implementatin is discussed. S far, Cnductive Plymer Aluminum Slid Capacitr (CPASC) is usually used as the utput capacitr f lw utput vltage cnverter. Hwever, the Ceramic chip capacitr is recently used by the demand f

16 4 Advances in PID Cntrl diminutin and thinness. The issue f Ceramic chip capacitr is that the capacitance is changed by the applied vltage. Cnventinally, the cntrller is designed by means f pwer stage frequency respnse, and it is designed t have sme stability margin. Hwever, when the capacitance is changed by the utput vltage, the pwer stage frequency respnse is changed. Then, the whle system frequency respnse is changed. Hence, the stability margin is changed, and then the system may becme unstable. Mrever, the transient respnse becmes wrse. As a result, prspective perfrmance is nt prvided. In rder t keep the system stability, it is necessary t understand crrectly the characteristics f capacitance variatin in detail. Figure 19 shws the experimental measurements f capacitance vs. applied vltage. The capacitrs are used as fllws; Sample 1: CPASC Nminal value : 47F Rated vltage : 1V Sample : Ceramic chip capacitr Nminal value : 1F (5 parallel, Ttal : 5F ) Rated vltage : 6.3V As shwn in Fig. 19, the capacitance is almst flat in CPASC. On the ther hand, the capacitance is drastically changed in Ceramic chip capacitr. In this case, the capacitance variatin is arund 6%. When the applied vltage is V, the capacitance is 41F, and when the applied vltage is 3.5V, the capacitance is F. As mentined abve, when the capacitance is changed, the system stability is als changed. 55 Capacitance (uf) CPASC Ceramic Cap Applied Vltage(V) Fig. 19. Applied vltage vs. capacitance. Figure shws the analytical result f stability margin vs. applied vltage. Initially, the stability margin is set 9dB GM and 5deg PM at CPASC. As shwn in Fig., the stability margin is flat fr all vltage range at CPASC. On the ther hand, the stability margin is reduced when the applied vltage becmes higher. At applied vltage.5v, the stability margin is changed frm 9dB GM and 5deg PM t 3dB GM and 5deg PM. Finally, when the applied vltage is 3.5V, the stability margin becmes limited.

17 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter Gain Margin(dB) CPASC CPASC Ceramic Cap. Ceramic Cap Applied Vltage(V) Fig.. Applied vltage vs. stability margin. Figure 1 shws the analytical result f lp gain when the utput vltage is 3.5V. Figure 19 has big difference cmpared with Fig. 15 as an initial cnditin. As shwn in Fig. 19, the anti-resnance peak is appeared at arund 1.8kHz. This anti-resnance peak is the influence f Gpzc(s) Phase Margin(deg) Gain Phase E+ 1.E+3 1.E+4 1.E+5 Fig. 1. Lp gain with PZC cntrl when capacitance changes (analytical result). This anti-resnance peak is cancelled by resnance peak f the pwer stage, essentially. Hwever, the anti-resnance peak is appeared n frequency respnse because f the pwer stage resnance peak is shifted by the influence f parameter variatin. Mrever, the resnance peak is appeared at arund.5khz. This resnance peak is pwer stage resnance peak. In this case, the bandwidth is changed frm 1kHz t khz, and the stability margin becmes very few. The perfrmance f the system is greatly affected by the parameter variatin in this way. Therefre, the parameter tracking is needed t keep the system perfrmance.

18 6 Advances in PID Cntrl There are tw methds f parameter tracking. One is perfect tracking methd. Anther is simplified tracking. The influence f parameter variatin is cmpletely cancelled by the perfect tracking methd. Hwever, the accurate detectin f the several mv high frequency vltage is very difficult. S, the perfect tracking is nt available slutin. Here, the simplified tracking methd is examined. The data table is used in the simplified tracking methd. Figure shws the experimental measurements f capacitance vs. stability margin. 1 6 Gain Margin(dB Gain Margin Phase Margin Phase Margin(deg) Capacitance(uF) Fig.. Capacitance vs. stability margin. Frm Fig. 19 and Fig., The designed parameters are listed in Table. The aut parameter tracking can be realized by implementatin f data table t DSP. Table. Parameter list. N. Vltage Range (V) Capacitance (F) Figure 3 shws the experimental result f lp gain when the utput vltage is 3.5V. As shwn in Fig. 3, the anti-resnance peak at arund 1.8kHz is reduced. Mrever, the resnance peak at arund.5khz is als reduced. In this case, the bandwidth is arund 1kHz, and the stability margin is imprved. Frm these results, fr parameter tracking, the system characteristics are kept initial cnditins.

19 Ple-Zer-Cancellatin Technique fr DC-DC Cnverter Gain(Experiment) Gain(Analysis) Phase(Experiment) Phase(Analysis) 1.E+ 1.E+3 1.E+4 1.E+5 Fig. 3. Lp gain with parameter tracking Cnclusins This paper prpses the interesting cntrl technique which is cancelled the transfer functin f the cnverter by means f ple-zer-cancellatin technique. This technique is very simple, and easy t stability design f cnverter system. Furthermre, the arbitrary frequency characteristics can be created by intrducing a new frequency characteristic. Especially, ptimal design f first-rder lw pass filter is cnsidered and, the design methd and system stability f the prpsed cntrl technique is examined analytically and experimentally by using buck cnverter. Furthermre, the parameter tracking is als examined. As a result, the effectiveness f prpsed cntrl technique is cnfirmed. Mrever, it is cnfirmed that the characteristic cancellatin f the cnverter can be realized very easy and can be set the arbitrary characteristic. Furthermre, the effective f parameter tracking is als cnfirmed. 8. References [1] Philip T. Krein, "Digital Cntrl Generatins -- Digital Cntrls fr Pwer Electrnics thrugh the Third Generatin," IEEE PEDS'7, pp P-1-P5, 7 [] A. Kelly and K. Rinne, "Cntrl f DC-DC Cnverters by Direct Ple Placement and Adaptive Feedfrward Gain Adjustment," IEEE APEC'5, pp -, 5. [3] A. Kelly, K. Rinne,"A Self-Cmpensating Adaptive Digital Regulatr fr Switching Cnverters Based n Linear Predictin," IEEE APEC'6, pp , 6. [4] Y. Wen, S. Xia, Y. Jin, I. Batarseh, "Adaptive Nnlinear Cmpensatin fr Asymmetrical Half Bridge DC-DC Cnverters," IEEE APEC'6, pp , 6. [5] L. Gu, J. Y. Hung, and R. M. Nelms, Digital cntrller design fr buck and bst cnverters using rt lcus, IEEE IECON 3, pp , 3. [6] H. Gu, Y. Shirishi, and O. Ichinkura, Digital PI cntrller fr high frequency switching DC/DC cnverter based n FPGA, IEEE INTELEC 3, pp , 3.

20 8 Advances in PID Cntrl [7] M. He, J. Xu, "Nnlinear PID in Digital Cntrlled Buck Cnverters," IEEE APEC'7, pp , 7. [8] R.D. Middlebrk, S. Cuk, A General Unified Apprach t Mdeling Switching- Cnverter Pwer Stages, IEEE Pwer Electrnics Specialists Cnference (PESC) 1976, pp [9] T. Ninmiya, M. Nakahara, T. Higashi, K. Harada, A Unified Analysis f Resnant Cnverters, IEEE Transactins n Pwer Electrnics Vl. 6. N.. April 1991, pp. 6-7.