An enhanced model for small signal analysis of the phase shifted full bridge converter

Transcription

1 An enhanced mdel fr small signal analysis f the phase shifted full bridge cnverter Article Accepted Versin Di Capua, G., Shirsavar, S. A., Hallwrth, M. A. and Femia, N. (14) An enhanced mdel fr small signal analysis f the phase shifted full bridge cnverter. IEEE Transactins n Pwer Electrnics, PP (99). ISSN di: Available at It is advisable t refer t the publisher s versin if yu intend t cite frm the wrk. Published versin at: %3D %6srtType%3Dasc_p_Sequence%6filter%3DAND%8p_IS_Number%3A43594%9 T link t this article DOI: Publisher: IEEE All utputs in CentAUR are prtected by Intellectual Prperty Rights law, including cpyright law. Cpyright and IPR is retained by the creatrs r ther cpyright hlders. Terms and cnditins fr use f this material are defined in the End User Agreement.

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3 An Enhanced Mdel fr Small-Signal Analysis f the Phase- Shifted Full-Bridge Cnverter Giulia Di Capua, Member, IEEE, Seyed A. Shirsavar, Michael A. Hallwrth, Member, IEEE, Nicla Femia, Senir Member, IEEE Abstract - This paper presents an in-depth critical discussin and derivatin f a detailed small-signal analysis f the Phase-Shifted Full-Bridge (PSFB) cnverter. Circuit parasitics, resnant inductance and transfrmer turns rati have all been taken int accunt in the evaluatin f this tplgy s pen-lp cntrl-t-utput, line-t-utput and lad-t-utput transfer functins. Accrdingly, the significant impact f lsses and resnant inductance n the cnverter s transfer functins is highlighted. The enhanced dynamic mdel prpsed in this paper enables the crrect design f the cnverter cmpensatr, including the effect f parasitics n the dynamic behavir f the PSFB cnverter. Detailed experimental results fr a real-life 36V-t-14V/1A PSFB industrial applicatin shw excellent agreement with the predictins frm the mdel prpsed herein. 1 Index Terms - Phase-Shifted Full-Bridge, Small-Signal Analysis, Lsses-based dynamic mdeling. I. INTRODUCTION High-efficiency and high-pwer-density in pwer cnverters can be achieved by reducing switching lsses, minimizing reverse recvery effects in rectifiers, reducing spikes created by parasitic elements, recvering as much energy as pssible and returning it t the pwer flw f the pwer supply. In rder t achieve these bjectives, numerus sft-switching circuit techniques [1]-[3], like Zer Vltage Switching (ZVS) and Zer Current Switching (ZCS), and many different and new resnant tplgies, including quasi-resnant and multi-resnant cnverters [4]-[6], have been prpsed and discussed in the literature. In particular, resnant cnverters have the benefits f high efficiency and high pwer density, with a lw level f Electr-Magnetic Interference (EMI) [7]. Hwever, there are cnsiderable drawbacks t using variable frequency-cntrlled resnant cnverters, sme f which include the difficulty in maintaining resnance peratin and ensuring high efficiency ver a wide dynamic range [8], in sizing apprpriate magnetic cmpnents [9], in designing the input and utput filter due t variable frequency f the cnverter [1]. On the cntrary, pulse-width mdulatin (PWM) cnverters have a cnstant frequency f peratin, hwever they usually wrk under hard switching cnditins, with semicnductr device vltages and currents changing abruptly frm high values t zer and vice-versa at turnn and turn-ff resulting in switching lsses and cnsiderable EMI. In rder t reduce these switching lsses and imprve PWM cnverter efficiency, imprved M. A. Hallwrth and S. A. Shirsavar are with the Schl f Systems Eng., University f Reading, Reading, Berkshire, RG6 6AY, U.K. E- mail: mhallwrth@theiet.rg; s.a.shirsavar@reading.ac.uk. G. Di Capua and N. Femia are with Department f Infrmatin Eng., Electrical Eng. and Applied Mathematics, University f Salern, Fiscian (SA), Italy, gdicapua@unisa.it; femia@unisa.it. semicnductr devices and magnetic materials have been develped ver the past few decades [11]-[13] and numerus sft-switching circuit techniques have been prpsed in the literature fr reducing the vltage-current prduct during the switching transitins [14]. As a result, the trend in pwer technlgy is mving twards cmbining the simplicity f PWM cnverters with the Sft-Switching (SS) characteristics f resnant cnverters, resulting in the advent f PWM-SS cnverters. Amng the PWM-SS tplgies, the ZVS PWM Phase-Shifted Full-Bridge (PSFB) cnverter, described in detail in [15], has becme a very ppular cnverter tplgy in islated high pwer applicatins. In particular, because f the ZVS f the MOSFETs, the PSFB cnverter can perate at higher frequencies and imprved efficiency when cmpared t the equivalent hard switched tplgy, reducing the size and cst f the pwer supply and resulting in higher pwer densities. ZVS at the primary side als reduces the stress n the semicnductr switches and imprves the cnverter reliability [16]. Since its inventin in the 8s, the PSFB cnverter has been used frequently as a secnd stage dwn frm a Frnt-End cnverter(i.e. fllwing a PFC stage), in rder t cnvert input vltages in the range f 36V t 6V dwn t a tightly regulated 48V DC bus [17]. Hwever, in recent years the interest in the PSFB cnverter has grwn due t the push fr efficiency in high pwer applicatins and the PSFB cnverter has been successfully used even fr lw pwer applicatins such as telecms equipment. Thus, a lt f innvative research has been prduced n tplgy variatins and cntrl techniques [18][19] fr the PSFB, vercming sme intrinsic limitatins f the cnverter, including the pssibility f hard switching and high vltage stresses n the secndary side []. Several literature references have shwn hw circulating currents during nrmal peratin can be reduced at the cnverter primary r secndary side [][1] and pr light-lad efficiency, ccurring when ZVS is lst, can be avided given a crrectly sized resnant inductance []. Nevertheless, nly a few published wrks (discussed in detail in Sectin II) deal with the dynamic mdeling f the PSFB cnverter and, mre imprtantly, at the time f writing n references can be fund in literature regarding the impact f the parasitics n the small-signal analysis f the cnverter. A methd cmmnly used fr PWM cnverter dynamic mdel small-signal mdeling is the State Space Averaging (SSA) technique [3]. Hwever n useful SSA-based dynamic mdeling can be fund fr the PSFB because, when applied t the PSFB cnverter, the resulting matrices are very cmplex after cnsidering the all f the peratin intervals and resnant transitins. The

4 first PWM-switch-based [4] small signal analysis fr the PSFB is presented in [6], where the cnverter ac mdel is btained as a mdified versin f the buck cnverter PWM switch mdel. This apprach is based n a simplified analysis f the effects resulting in the dutycycle mdulatin due t the change in input vltage and filter inductr current. Hwever, this mdel des nt cnsider the impact f the cnverter lsses and, as a cnsequence, it des nt take in accunt the cnverter efficiency. The result is a relatively simple small signal mdel fr the PSFB cnverter, based n several idealistic assumptins, including zer Equivalent Series Resistance (ESR) fr the utput capacitr and unity transfrmer turns rati equal t ne. The limitatins f this mdel will be discussed in detail in Sectin II. A further small signal analysis f the PSFB cnverter has been suggested in [7]. The prpsed small-signal analysis uses an uncnventinal averaging technique based n discrete sampled data equatins. Hwever, the resulting dynamic mdel is cmplex and nt versatile; n additinal benefits f the mdel are discussed using this prpsed methd with respect the previus simpler mdel. Finally, bth the lsses and the impact f parasitics are neglected. In rder t explit the benefits f the PSFB tplgy, cnsidering the evlutin f bth the industrial applicatins and semicnductr technlgical prgresses f the past decade, it is fundamentally imprtant t revise and imprve the PSFB cnverter dynamic mdel and investigate the crrelatins existing between the efficiency and dynamic respnse. Due t the lack f new enhanced PSFB small-signal mdels, many recent papers refer t the simplified mdel which is n lnger adequate fr mdern applicatins f the cnverter. In this paper, a new critical and detailed discussin f the small-signal analysis f the PSFB cnverter is presented and an enhanced small signal mdel is derived. The prpsed small-signal mdel includes thus far neglected and yet significant factrs (such as parasitics, resnant inductance and transfrmer turns rati) as well as parameters necessary fr real life practical design, such as the mdulatr gain. Therefre, a mre realistic and accurate dynamic analysis f PSFB cnverter with respect t previus mdels has been carried ut. Secndly, this new mdel als allws the jint investigatin f the influence f the transfrmer characteristics (turns rati and leakage inductance) and the efficiency (assumed t be an independent lumped variable) n the dynamic behavir f the cnverter. In particular, n ne hand achieving sft-switching depends n the value f the resnant inductance. On the ther hand, the maximum achievable efficiency will depend n all f the pwer cmpnents (including the resnant inductance) and n the line/lad perating cnditins. In this paper it is shwn hw the resnant inductance value and the cnverter efficiency influence the dynamic prperties f the PSFB cnverter. In Sectin II an verview f the intrinsic limitatins and drawbacks f previus PSFB small signal mdel is given. In Sectin III the enhanced dynamic mdel f the PSFB cnverter prpsed in this paper is discussed. Realwrld experimental measurements frm a hardware PSFB cnverter are presented, which shw excellent agreement with the prpsed mdel predictins. Using the prpsed mdel, in Sectin IV, the influence f the parasitics n the cnverter cmpensatr design is als discussed and cmpared with apprximated and simplified dynamic mdels. II. SIMPLIFIED PSFB SMALL SIGNAL MODELS In recent years great attentin has been paid t the PSFB cnverter and numerus papers have been published presenting riginal research results abut this cnverter. Several Authrs prpse new lssless dideclamp rectifiers and ther auxiliary circuits, enabling EMI reductins, circulating lsses minimizatin and higher efficiency achievement fr the PSFB [8][9]. Other authrs present slutins fr ensuring the ZVS peratin ver wide lad range, making use f innvative magnetic cmpnents with integrated additinal resnant inductrs [9][3] r additinal silicn devices [8][31]. As a result, new dedicated silicn devices, with fast recvery bdy dides and reduced turn-n and turn-ff delay times [3][33] alng with highly integrated PWM cntrllers have recently been develped in respnse t PSFB requirements [34]. Nevertheless, all the develped innvative research n this tpic is in cntrast with the lack f a detailed dynamic mdel fr this PWM-SS cnverter. In fact, many recent papers either d nt present a suitable small-signal analysis r are nly based n limited simplified mdels. Fr example, in [35] a new multi-input and multi-utput PSFB-based tplgy slutin is presented, resulting in reduced vltage stresses n the pwer cmpnents and reduced filter size. Hwever, the influence n the resulting dynamic mdel f the cnverter is nt discussed. Als new digital cntrl techniques and enhanced intelligent cntrl methds have been recently investigated [36]-[39], neglecting the efficiency and/r the impact f parasitics n the cnverter cntrller design. Thus, n ne hand, the PSFB ppularity is increasing, thanks t the pssibility f high-efficiency and high-pwer-density designs. Hwever, n the ther hand, n enhanced dynamic lss-based mdels have been prpsed in last twenty years that take int accunt efficiency, despite the imprtance f this parameter. The parasitics have a great impact n the PSFB dynamic behavir, as it will be shwn and discussed in detail in Sectin III and Sectin IV f this paper. In this sectin, the fundamental limitatins f simplified dynamic mdels presented s far in literature are highlighted and a preliminary intrductin t the main parameters invlved in the dynamic mdeling f the cnverter is given. In Fig.1(a) the PSFB schematic circuit is given and in Fig. 1(b) the cnverter wavefrms f the vltage and current primary side and the vltage and current secndary side are shwn. The finite slpe f the primary side current I P depends n the leakage inductance L leak. This slpe reduces the duty-cycle f the secndary side vltage, with a detrimental impact n the dynamic characteristics f the cnverter [5].The PSFB circuit s secndary side is in itself very similar t a cnventinal buck tplgy.

5 (a) Fig. 1.PSFB schematic circuit (a); main circuit wavefrms (b). (b) Hwever, its small signal prperties are quite different, because f the cnverter s phase-shift peratin and the presence f the transfrmer leakage inductance, which jintly represent the rt cause f the lst duty phenmenn [5]. Fr simplicity, let us cnsider the ttal equivalent leakage inductance t be lumped n the transfrmer primary side. Leakage inductance prvides a first cntributin t resnant inductance. In rder t achieve sft switching in a PSFB cnverter, the leakage inductance alne may nt be sufficient. Often an additinal external inductr is added t the primary current path [] t achieve the desired resnant inductance. Hwever, a resnant inductance that is t large wuld result in lnger transitin times, higher value f lst duty and reduced dynamic range f the cnverter. A detailed and cmplete descriptin f the secndary vltage duty-cycle is included in [5], where equatin (1) fr secndary vltage effective duty-cycle is given as: n fsl leak V D Deff D D D IL Vin L fs In this equatin D is the duty cycle f the primary vltage set by the cnverter cntrller, ΔD is the lst f duty cycle due t the finite slpe f the rising and falling edges f the primary current, n=n s /n p is the transfrmer turns rati, V in and V ut are the cnverter input and utput vltages respectively, f s is the switching frequency, I L is the utput inductr current, L is the utput inductr and L leak is the leakage inductance f the transfrmer. Accrding t (1), the small signal transfer functins f the PSFB depend n the leakage inductance L leak, the switching frequency f s, the perturbatins f the utput filter inductr current i ˆL (1), the input vltage v and the ˆin primary vltage duty cycle ˆd. T accurately mdel the dynamic behavir f the PSFB, the cntributins f all these previus parameters have t be taken int cnsideratin. Cnsequently, the small-signal circuit mdel f a simple PWM switch Buck cnverter can be mdified in rder t btain the prper mdel fr a PSFB cnverter. Taking int accunt the duty cycle mdulatin due t the change f the utput filter inductr current ( d ) ˆi and t the change f the input vltage ( d ), the ttal ˆv change f the effective duty ( d ) can be given by (): ˆeff dˆ dˆ dˆ dˆ () eff i v Based n the abve, the resulting PSFB dynamic mdel discussed in [6] prvides results which deserve sme additinal cnsideratin fr a cmplete and full understanding f the PSFB ac small-signal analysis. The derived PSFB mdel in [6] neglects n-resistances, frward vltage drps and junctin capacitances f the slid state devices. All f these elements result in lsses which cntribute t the damping f the cnverter. Mrever, in [6] the ESR f the utput capacitr has been neglected in its entirety. Hwever, fr PSFB cnverter applicatins, electrlytic utput capacitrs are used rather than ceramic nes which might therwise justify a negligible ESR. Thus, the ESR f the utput capacitr cannt be ignred because it is respnsible fr a zer in the cnverter transfer functin. Accrdingly, in [6] the transfer functin f the PWM switch PSFB cnverter has been evaluated and the cntrl-t-utput transfer functin is given as in (3): G vd d nv in ˆ iˆ L ˆ Rd v in s L C s R d C Rlad Rlad 1 where Rd 4n fsl. The term ( leak Rd / Rlad 1) in equatin (3) is imprtant in the dynamic analysis f the cnverter as it jintly takes int accunt the influence f leakage inductance L leak, transfrmer turn rati n, and lad resistance R lad, in the cntrl-t-utput transfer functin. In [6] it is shwn hw the cntrl-t-utput changes by varying the rati Rd / R. Hwever, using assumptins lad mstly referred t the typical PSFB applicatins discussed in the 8s and 9s, a range f t.5 and a typical value f.5 is suggested fr the term Rd / R. lad Althugh valid in certain specific situatins, this apprximatin, tgether with the assumptin f having a unit value fr the transfrmer turn rati n are nt valid in general and hide the critically invlved dependence f the cntrl-t-utput transfer functin n the leakage inductance, transfrmer turns rati and lad resistance. III. ENHANCED DYNAMIC MODELING OF THE PSFB A. Frmulatin f the PSFB dynamic mdel An enhanced PWM switch-based mdel fr smallsignal analysis f the PSFB cnverter is prpsed in this paper and is discussed in detail in this sectin. The crrespnding circuit fr the PSFB PWM switch-based (3)

6 mdel is shwn in Fig.. The three terminals equivalent functinal blck (identified by ndes a, p, c ) includes the three terminals PMW switch blck (identified by ndes a, p, c [4]) and the equivalent lsses-dependent resistance R eq (included between terminals c and c ). In particular, the equivalent resistance R eq depends n the ttal pwer lsses f the cnverter and allws the PSFB efficiency t be taken int accunt within the prpsed dynamic mdel. As discussed in Sectin II, the circuit mdel f the effective duty is represented by means f a vltagecntrlled surce and a current-cntrlled surce (see Fig. ). Thus, the DC and the AC equivalent circuit f the PSFB are shwn in Fig. 3(a) and Fig. 3(b), respectively. Fig..Circuit mdel f the PWM switch fr the PSFB. Fig. 3. PSFB DC equivalent mdel (a) and small-signal equivalent mdel (b). (a) (b) The equatins f the equivalent DC PSFB cnverter circuit f Fig. 3(a) are summarized in (4). cmpensatr and it is als easily measurable. Frm Ia Deff Ic (4.a) (3) equatins (5) and (6), assuming in, iˆ ut and Vcp Deff Vap (4.b) slving fr v, the transfer functin G ˆut vd has been Vcp Req Ic Vc p (4.c) P = V I 1 R I (4.d) lss ut ut eq ut where V ap =nv in, V c p =V ut, I c and I a are indicated in Fig. 3(a) and P lss is the ttal pwer lss f the cnverter. The cnverter efficiency as a functin f the pwer devices parameters can be evaluated as shwn in [8]. Slving the system equatin given in (4) prvides the DC value f duty D eff and the equivalent lss-dependent lumped resistance R eq. The utput inductr DC series resistance DCR has been included in the resistance R eq. Fr the PSFB AC mdel, the equivalent AC PSFB cnverter circuit f Fig. 3(b) is cnsidered. The resulting circuit equatins are summarized in (5) and (6). iˆ D iˆ dˆ I (5.a) a eff c eff c ˆ ˆ cp Deff vap deffvap (5.b) ˆ ˆ cp Req s L ic vc p (5.c) ˆ ˆ ut i ˆ c ic iut R (5.d) lad 1 v ˆ ˆut ESR i C (5.e) sc dˆ dˆ dˆ dˆ (6.a) dˆ eff i v i Rd iˆ c (6.b) V ap dˆ I V D R ut eff d v c ap 4 fs L Vap (6.c) where ˆ ap nv, in ˆ c' p v and ut D' eff 1 D. Using the eff MATLAB Symblic Tlbx, the analytical expressins f the PSFB transfer functins have been evaluated and their explicit frmulatins are presented in the fllwing. The duty-t-utput transfer functin G vd represents the sensitivity f utput vltage t duty-cycle variatins, when input vltage and utput current are lcked at their steady-state values. The transfer functin G vd is mst imprtant in cntrl lp design. In fact, in Vltage Mde Cntrl (VMC), G vd is cnnected t the cntrl-t-utput transfer functin G / G G, where G PWM is vc ut ctr PWM vd the PWM mdulatr gain and v is the vltage errr ˆctr amplifier utput. The PWM mdulatr gain cnverts the vltage errr amplifier utput t duty cycle and is given as G PWM =1/V pp, where V pp is the peak f the PWM vltage ramp signal. is used t design the feedback evaluated and its analytical frmulatin is given in (7). With sme algebra, (7) can be re-written as in (8): G vd nv R s ESR C 1 (8) ut in lad ˆ ˆ d i ut L C R lad ESR s s ˆ n n v in G vd nv ut in ˆ dˆ i ut ˆ ESR 4 L ESR v Req n fslleak in s LC 1 s ESRC C Req 4n fslleak 1 1 Rlad Rlad R lad Rlad s ESR C 1 (7)

7 The natural frequency n and the damping rati have the analytical expressins given in (9): L C C 4 Rlad ESR Rlad Req n fslleak Rlad L n Rlad ESR Rlad Req n fslleak 4 R R 4n f L 1 lad eq s leak LC R lad ESR (9.a) (9.b) Accrding t (8), the transfer functin G vd exhibits a secnd-rder dynamic with a pair f ples, an additinal extra-zer which depends upn the utput capacitr, and a gain related t the utput filter parameters, the cnverter input and utput vltage and the transfrmer turns rati. Frm equatin (9.a) and (9.b), it can be seen hw the ESR f the utput capacitr nt nly adds a zer t PSFB dynamic system but als impacts the damping rati, as well as the natural frequency n. Furthermre, the appearance f the equivalent resistance R eq in the natural frequency term n als cnfirms that the resnance will change accrding t the PSFB lsses. Therefre, the parasitics cannt simply be neglected. The damping and resnance prperties f the PSFB secnd-rder system depend n the circuit parasitics, which must be all prperly cnsidered fr a crrect analysis f the system transient respnse. T this end, additinal cmments can be fund in the paper Appendix. The line-t-utput transfer functin G vg represents the sensitivity f utput vltage t input vltage variatins, when duty-cycle and utput current are lcked at their steady-state values. Frm equatins (5) and (6), nw assuming dˆ, iˆ ut and slving fr v, the transfer ˆut functin G vg has been evaluated and its analytical frmulatin is given in (1). Frm netwrk thery it is knwn that the plynmial denminatr is the same fr all the transfer functins f a dynamic system, as it depends n the characteristics f the netwrk itself. In particular, the transfer functin G vg is identical t the transfer functin G vd, except fr the DC gain. The DC gain f the transfer functin G vg depends n the vltage/current perating cnditins and n the circuit parasitics, whse effect n the PSFB damping and resnance prperties has already been emphasized fr the G vd. Finally, the lad-t-utput (r utput impedance) transfer functin Z ut represents the sensitivity f utput vltage t utput current variatins, when duty-cycle and input vltage are lcked at their steady-state values. Frm equatins (5) and (6), nw assuming dˆ, and slving fr v, the transfer functin Z ˆut ut has been evaluated and its analytical frmulatin is given in (11). in Accrding t (11), the transfer functin Z ut has a pair f ples and tw extra-zers, ne depending n the ESR f the utput capacitr and anther depending n the utput inductr, the equivalent resistance R eq, the switching frequency and the transfrmer parameters. Als, the transfer functin gain depends n the utput filter parameters and the cnverter utput specificatins. B. Experimental verificatin Experimental measurements f the pen lp transfer functins have been realized by means f the Texas Instruments high-efficiency evaluatin bard shwn in Fig.4, including the PSFB vltage-mde cntrller UCC895PW[4]. The fllwing perating cnditins were applied: V in =36V, V ut =14V, I ut =1A, f s =188kHz. Main pwer devices munted n the bard are listed in Table I. All the cnverter pen-lp transfer functins were measured using the OMICRON Lab Bde 1 vectr netwrk analyzer. Numerus small-signal measurements were perfrmed using analg small-signal injectin techniques [41]. In rder t verify the validity f the prpsed dynamic mdel, measurements f the utput filter cmpnents and f the transfrmer were als carried ut and the fllwing measured values were btained: C =1354uF, ESR =1.mΩ, L =5.3uH, DCR =35.4mΩ, L leak =191nH. Als, the cnverter s efficiency was at =96.6%. Fig. 4.PSFB bard used fr the experimental measurements. Table I. Main pwer devices munted n the bard. Main Devices Part numbers Manufact. Main attributes Primary V BSC13N8NS3-G Infinen ds=8v, I d=55a MOSFETs R ds,n=1.3mω, Secndary Super Fast Rect., ES1D Dides Dides V f=.9v, I f=1a Output SMT, L=4.7uH, SER918H-47 Cilcraft Inductr DCR=.86mΩ Output Aluminum, 35V, EEUFK1V15L Panasnic Capacitr C=15uF Input Aluminum, 1V, ECAAHG11 Panasnic Capacitr C=1uF Input C11C5K1RACTU Ceramic, 1V, Kemet Capacitr (x3) C=.uF n Transfrmer PN-549 (Custm) Paytn p=4, n s=, P max=94w V 4 f D R s ESR C 1 G nd n L Z ut s eff lad vg eff leak ˆ ˆ v in i ut V in R lad L L C R lad ESR s s n n dˆ ut R eq 4n fslleak sl s ESRC 1 R ut lad ˆ iˆ ut d LC Rlad ESR s sn n in (1) (11)

8 Phase [Degrees] Phase [Degrees] Phase [Degrees] Phase [Degrees] The measured and the simulated results fr the cntrlt-utput transfer functin is shwn in Fig. 5: there is excellent agreement between the experimental result (dashed gray line) and the prpsed PSFB enhanced dynamic mdel (black cntinuus line). Als, the experimental measurements (dashed gray line) and the simulated results (black cntinuus line) fr the input-tutput transfer functin G vg and the lad-t-utput transfer functin Z ut are shwn in Fig. 6 and Fig. 7, respectively. The resulting agreement between the measured and simulated transfer functins permits t validate the prpsed enhanced mdel fr small-signal analysis f the PSFB cnverter. C. Impact f ESL in the PSFB dynamic mdel At higher frequencies the agreement between the experimental results and the prpsed PSFB enhanced dynamic mdel can be imprved further by taking int accunt the effect f the Equivalent Series Inductance f the utput capacitr (labeled in the fllwing as ESL ) Enhanced Mdel Enhanced Mdel Fig. 5. Measured (dtted lines) and simulated (slid lines) cntrlt-utput transfer functin G vg - Enhanced Mdel G vg Z ut Z ut - Enhanced Mdel -4 Z ut - Enhanced Mdel Z ut Fig. 7. Measured (dtted lines) and simulated (slid lines) lad-tutput transfer functin. T include the ESL in the PSFB AC mdel equatin (5.e) shuld be replaced by equatin (1): 1 v ESR s ESL i ˆ sc ˆut C (1) Using a value f ESL =5nH, experimental and the simulated results are almst identical t higher frequency t 1MHz, as shwn in Fig. 8. The achieved agreement nce again cnfirms the accuracy f the prpsed dynamic mdel. Nevertheless, it shuld be nted that typically frequencies abve the pen-lp crssver frequency are f little interest in cntrl lp design. Therefre, the mdel withut the additin f the ESL is acceptable fr mst use cases Enhanced Mdel G vg - Enhanced Mdel G vg Fig. 6. Measured (dtted lines) and simulated (slid lines) input-tutput transfer functin Enhanced Mdel Fig. 8. Measured (dtted lines) and simulated (slid lines) cntrlt-utput transfer functin including ESL.

9 Phase [deg] Phase [deg] IV. IMPACT OF THE DYNAMIC MODEL ON PSFB COMPENSATOR DESIGN The prpsed dynamic mdel permits reliable cmpensatr design fr the PSFB, with a predictable and accurate value f the crssver frequency and an acceptable amunt f phase margin. The lp gain f the cnverter is given by T c =G va, where G va is the cmpensatr gain t be designed based n the cntrl-tutput transfer functin. Given the design specificatins mentined in Sectin III, the transfer functin can be calculated as derived in the same Sectin. In rder t clearly understand the impact f an imprper dynamic mdeling n the clsed lp transfer functins f the PSFB, the cmpensatr design fr the afrementined case study is discussed in the remainder f this sectin. The cmpensatr has been derived based n the K-factr apprach [4] by using the tw fllwing PSFB dynamic mdels: i. the mdel prpsed in this paper, labeled as the enhanced mdel, including the parasitic parameters; ii. the mdel prpsed in [6], labeled as the simplified mdel, where 4n fslleak Rlad.5 and =1%. The fllwing dynamic specificatins have been adpted fr the cmpensatr design: a crss-ver frequency f c =3.5kHz and a phase margin P m =65. It shuld be nted that a crss-ver frequency f arund 3kHz - 5kHz is usually the highest achievable crss-ver frequency fr an islated cnverter using pt-islatr in the cntrl lp. Therefre, it is necessary t ensure a predictable value f f c using the mdel t cmply with this specificatin. The cmpensatr design results btained with the enhanced and simplified mdels are shwn in Table II. Table II. Cmpensatr design fr enhanced and simplified mdels. Mdel Enhanced mdel Simplified mdel G G Cntrller Type f p1 1 s fz1 va, E s 1 s f p f p1 1 s fz1 va, S s 1 s f p Cmpensatr design f p1=347hz f z1=1.8khz f p=6.8khz f p1=83 Hz f z1=1.66 khz f p=7.39 khz The fulfillment f all the dynamic specificatins requires a Type-III cntrller, labeled as G va,e fr the enhanced mdel and G va,s fr the simplified mdel. In Fig.9(a) the uncmpensated lp gain T u,e (gray slid line) and the cmpensated lp gain T c,e= T u,e G va,e (black slid line) are shwn fr the enhanced mdel. In Fig.9(b) the uncmpensated lp gain T u,s (gray slid line) and the cmpensated lp gain T c,s= T u,s G va,s (black slid line) are shwn fr the simplified mdel. The switching frequency f s (dtted gray lines) and the resulting crss-ver frequency f c,e, f c,s (dashed lines) are als shwn fr the tw mdels in Fig. 9(a)(b). As can be seen frm Fig. 9(a), the cmpensatr designed using the enhanced mdel perfectly fits the dynamic specificatins, with a crssver frequency f 3.5kHz. The cmpensated lp gain T c,e- S=T u,e G va,s (dtted black lines) shwn in Fig. 9(b) can be analyzed t understand what happens if the cmpensatr designed with the simplified mdel G va,s is used t cntrl the real cnverter with lsses. In particular, the plt f T c,e-s shws that the crss-ver frequency and phase margin btained d nt cmply with the given dynamic specificatins: the resulting crss-ver frequency is f c,e- S=7.8kHz, whereas the crss-ver specificatin is 3.5kHz. Of curse, due t the presence f the pt-cupler ple, a crssver frequency f twice the designed value, in all likeliness, wuld result in instability in a real system. The additinal ple added by the pt-cupler and the higher than expected crssver frequency culd result in the slpe f the cmpensated lp gain magnitude t apprach 4dB/decade and thus vilate the pwer supply stability criteria. Mrever, as shwn in Fig. 9(b), the resulting phase margin is 5 whereas the desired phase margin is 65. This culd lead t stability issues fr systems where additinal phase lag can ccur, and f curse t lwer than permitted Mean Time Between Failures (MTBF) frm a cmmercial prduct pint. The analysis f the line step-respnse f the cnverter helps in the better understanding f the impact f pwer lsses n the reliability f the PSFB cmpensatr design. The cmpensated line-t-utput transfer functin G vgc can be used fr this purpse T u, E T c, E f c, E f s Phase margin f (a) T u, S T c, S T c, S - real f c, S f c, S - real f s kHz 3.5kHz Phase margin f (b) 7.8kHz Phase margin f 5 Fig. 9. Uncmpensated and cmpensated lp gain transfer functins fr enhanced (a) and simplified (b) mdel.

10 The G vgc has been evaluated in the three fllwing cases: - using the real transfer functin G vg given in (1) and the cmpensatr T c,e, designed accrding t the enhanced mdel prpsed in this paper: as a result, it is G vgc,e =G vg /(1+T c,e ); - using the real transfer functin G vg given in (1) and the cmpensatr T c,s, designed accrding t the simplified mdel: as a result, it is G vgc,e- S=G vg /(1+T c,s ); - using the simplified transfer functin G vg,s ( presented in [6]) and the cmpensatr T c,s designed accrding t the simplified mdel: as a result, it is G vgc,s =G vg,s /(1+T c,s ), being G vg,s evaluated frm (1), replacing ESR = and R eq =. The step respnses btained with these transfer functins are shwn fr G vgc in Fig. 1. V ut [mv] Fig. 1. Line step respnses using the cmpensated lp gain transfer functins T c,e (grey line), T c,e-s (black dashed line), T c,s (black line) The black cntinuus line plt shws what wuld happen if the PSFB were lss-less: the G vgc,s step respnse is characterized by an versht f 45mV. The black dashed line plt shws what happens if we use a cmpensatr designed fr a lss-less PSFB t cntrl a real PSFB: the G vgc,e-s step respnse is characterized by an versht f abut 9mV, which is abut twice the value expected using the lss-less mdel. The grey line plt shws what happens if we use a cmpensatr designed fr a real PSFB t cntrl a real PSFB: the G vgc,e step respnse is characterized by an versht f abut 9mV, which is what the PSFB really des. Thus, the simplified mdel hides the actual impact f parasitics n the real dynamic f the cnverter and leads t ver-ptimistic perfrmance predictins. As a cnsequence, time-cnsuming trial-anderrr prcedures may be required in rder t ensure that the cnverter achieves the required perfrmance. Instead, a prper cnsideratin f the parasitics effects allws fr a reliable cmpensatr design with predictable perfrmance. Indeed, the enhanced dynamic mdel prpsed in this paper enables straightfrward cmpensatr design with crrect and predictable values f crss-ver frequency and phase margin. CONCLUSIONS x 1 step respnse fr G vgc,e step respnse fr G vgc,e-s step respnse fr G vgc,s Time [sec] x 1-3 A new mdel fr the small-signal behavir f the Phase-Shifted Full Bridge cnverter has been presented in this paper. The glbal effect f circuit parasitics and efficiency has been analyzed, by means f a cmpact behaviral mdel, allwing the evaluatin f the cnverter pen-lp transfer functins. Experimental verificatins validate the prpsed behaviral mdel. The influence f the parasitics and efficiency n the cmpensatr design have als been investigated. The main differences between the cmpensated lp gain transfer functins fr the prpsed enhanced mdel and the pre-existing simplified mdel have been discussed. Examples highlight the impact f apprpriate dynamic mdeling f the PSFB n the perfrmances f the cntrller. The enhanced mdel fr the PSFB cnverter presented in this paper allws fr a stable, reliable and predictable cntrller t be designed meeting the crssver frequency and phase margin requirements. APPENDIX The pen-lp transfer functins given in (8)-(11) highlight the significant influence f the utput capacitr resistance (ESR ), the efficiency (thrugh the equivalent lss-dependent lumped resistance R eq ), the transfrmer (thrugh the turns rati n and the leakage inductance L leak ) and the switching frequency (f s ) n the ples and zers f the PSFB. It is wrth cnsidering that the lumped resistance R eq depends in turn n the ttal pwer lsses f the cnverter and, as a cnsequence, n the switching frequency as well. In Sectin III the influence f the circuit parasitics and the cnverter efficiency has been emphasized referring t the damping and resnance prperties f the PSFB. In this Appendix, by means f sme examples, the influence f the leakage inductance and efficiency n the pen-lp transfer functins is further investigated in rder t highlight the jint impact f parasitics and lsses n the dynamic behavir f the cnverter. Using the case study discussed in Sectin III, the Bde plts fr the pen-lp cntrl-t-utput transfer functin are shwn in Fig.s 11 and 1 fr different values f leakage inductance and efficiency. Nte that decreasing value f the cnverter efficiency crrespnds t increasing values f the equivalent lumped resistance R eq. In particular, in Fig.11 the has been evaluated fr a fixed value f the leakage inductance L leak =.μh and decreasing values f the efficiency, frm =98.6% t =9.6%. Cnversely, in Fig.1 the has been evaluated fr an increasing value f the leakage inductance, frm L leak =.μh t L leak =1μH, and a fixed value f the efficiency=96.6%. Fr leakage inductance L leak =.μh, magnitude shws mre damping while R eq increases, whereas the crss-ver frequency des nt change (Fig.11(a)). As a cnsequence, the phase margin in the regin f interest fr the crssver is lwer when the equivalent resistance R eq decreases, which means when the cnverter efficiency increases (Fig.11(b)). Fr fixed value f efficiency =96.6%, the crss-ver frequency changes frm arund 7kHz t 5Hz fr increasing values f leakage inductance L leak (Fig.1(a)). Als, a lwer DC gain value and a high sensitivity t duty-cycle perturbatins can be bserved nly in a limited lw-frequency range (frm t arund 1Hz fr L leak =1μH). Mrever, a significant increase in the phase can be nted in the range f frequencies frm 3kHz t 5kHz; where the crss-ver f the lp gain is likely t be placed (Fig.1(b)).

11 Phase [Degrees] Phase [Degrees] The previus analysis emphasizes that the key pint in PSFB cntrl design is the crrect determinatin f the verall lsses determined by the resnant inductance, the semicnductr devices and the passive cmpnents (a) (b) Fig. 11. PSFB cntrl-t-utput transfer functin mdificatin fr L leak=.μh, =[98.6,96.6, 94.6,9.6]% (frm gray t black) (a) (b) Fig. 1. PSFB cntrl-t-utput transfer functin mdificatin fr =96.6% and L leak=[.,.,, 1]μH (frm gray t black). Understanding this pint f view, the resnant inductance L leak plays a critical rle. In fact, it influences the damping rati bth directly and indirectly. L leak explicitly appears in the equatin (9.a), which shws the direct impact n the damping. But L leak als influences the ttal lsses, and thus in turn the lumped resistance R eq, which cntributes twards the damping. In this regard, it has been shwn that increasing L leak des nt necessarily lead t a lss reductin, as it can als cause a lss increase []. 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[39] Faa-Jeng Lin, Ming-Shi Huang, P-Yi Yeh, Han-Chang Tsai, Chi-Hsuan Kuan, DSP-Based Prbabilistic Fuzzy Neural Netwrk Cntrl fr Li-In Battery Charger, IEEE Trans. n Pwer Electrnics, vl. 7, n. 8, pp , Aug. 1. [4] Texas Instruments, Green Phase-Shifted Full-Bridge Cntrller with Synchrnus Rectificatin, available n-line. [41] Ridley Engineering, AP Parallel Frequency Respnse Analyzer, Applicatin Ntes, available n-line. [4] H. D. Venable, The k-factr: A New mathematical Tl fr Stability, Analysis, and Synthesis, Prc. f PwerCn 1, San Dieg, CA, -4 March Giulia Di Capua Giulia Di Capua (S 6, M 13) was brn in Avellin, Italy, in She received the B.S. Degree and the M.S. Degree in Electrnic Engineering frm the University f Salern, with hnrs, in 6 and 9, respectively. She received the PhD degree frm the Dctral Schl f Infrmatin Engineering at the same University, in 13. She is currently a Research Fellw in the Department f Infrmatin Engineering, Electrical Engineering and Applied Mathematics f the University f Salern. Her research interests include analysis and design f Pwer Management switching mde pwer supplies, with special attentin t ptimizatin switching cnverters and f magnetic cmpnents fr islated cnverters and t thermal characterizatin f magnetic cre fr pwer cmpnents in high-frequency switching applicatins. Seyed Ali Shirsavar received the B.Eng. (Hns.) degree in electrnic engineering and the Ph.D. degree frm the University f Reading, Reading, U.K., in 199 and 1998, respectively. After a perid f wrk in the industry designing embedded cntrller hardware, switch-mde pwer supplies, and high-perfrmance threephase inverters, he is currently a Lecturer in the University f Reading, where he teaches curses at all levels. His main research interests include pwer electrnics and in particular digital cntrl f switch mde pwer supplies. Michael Andrew Hallwrth (M'11) received the B.Eng. (Hns.) degree in Electrnic Engineering and the Ph.D degree frm the University f Reading, Reading, U.K., in 9 and 13 respectively. He is currently wrking in the pwer electrnics industry and is als cntinuing further research fr the University f Reading. His main research tpics include high efficiency pwer cnversin and the digital cntrl f switched mde pwer supplies. Nicla Femia (M 94, SM 13) was brn in Salern, Italy, in He received the Master Degree in Industrial Technlgies Engineering frm the Salern University, with hnrs, in Frm 199 t 1998, he was an Assistant Prfessr, frm 1998 t 1, he was an Assciate Prfessr, and since 1, he has been a Full Prfessr f Circuits Thery with the Department f Infrmatin and Electrical Engineering, University f Salern. He is the cauthr f mre than 11 scientific papers published in the prceedings f internatinal sympsia and in internatinal jurnals. His main scientific interests include the fields f circuit thery and applicatins and pwer electrnics. Dr. Femia was an Assciate Editr fr the IEEE Transactins n Pwer Electrnics frm 1995 t 3.