Simplified Control Technique for Three-Phase Rectifier PFC Based on the Scott Transformer

Transcription

1 Simplified Cntrl Technique fr ThreePhase Rectifier PFC Based n the Sctt Transfrmer A.A. Badin * and. Barbi ** Federal University f Santa Catarina Pwer Electrnics nstitute P.O.Bx 5119 CEP: Flrianplis, SCBrazil alceu@inep.ufsc.br * and ivbarbi@inep.ufsc.br ** Abstract: n this wrk, a new simplified cntrl is prpsed fr threephase rectifier based n the Sctt Transfrmer with split DC bus. The cntrl technique lp is independent fr each bst that integrates the rectifier. Therefre, it makes pssible with tw singlephase bsts t btain a unity pwer factr threephase rectifier. This rectifier is particularly attractive when galvanic islatin and minimum number f active switches are required. t is used PWM with instantaneus average current cntrl. Besides it has tw vltage cntrl lps that regulate the utput vltage and the split DC bus. n this paper will be presented analysis, simulatin and experimental results fr the three phase rectifier and the cntrl technique prpsed.. NTRODUCTON n recent years, the grwth in the use f electrical equipment has resulted in mre stringent internatinal standards and utility requirements t ensue that line current harmnic cntent f equipment cnnected t the ac mains is limited [1]. f such standards did nt exist, then sensitive electrical equipment cnnected t the mains wuld be damaged as a result f a distrted main vltage. Threephase acdc cnverters perating frm the ac utility mains have the ptential t inject current harmnics int the ac mains that may cause such a distrted vltage. These harmnics can be significantly reduced if the input pwer factr is crrected by shaping the input current in each f the three phases s that it is sinusidal and in phase with the phase vltage. Due t this, switchmde rectifiers fr pwer factr crrectin have gained cnsiderable attentin. n additin t unity pwer factr, safety and rbustness als are imprtant fr mediumpwer and highpwer. Due t that islated systems in lw frequency are used. The islated rectifiers have been widely used in the electrchemical industry and petrchemical industry. The threephase rectifier based n the Sctt Transfrmer has been prpsed by [2], and has been analyzed in its practical aspects by [3] and [4]. n this paper, the unity pwer factr threephase rectifier with split DCbus and a simplified cntrl lp technique, based n the Sctt transfrmer, is presented. The prpsed tplgy is shw in the Fig. 1. This rectifier has a split DCbus and switches vltages are V/2. The cntrl methd emplyed t cntrl the currents f the tw bst inductrs, L T and L M, is instantaneus average current cntrl. Each rectifier presents an independent current lp with an individual reference current, generating sinusidal secndary currents in phase with their respective secndary vltages. Each rectifier als presents an independent vltage lp and individual reference vltage. The utput vltage cmpensatrs are used t determine the amplitudes f the reference currents. VA VB VC A A(t) B B(t) C C(t) T T T M V sect(t) V secm(t) L T LT(t) L M LM(t) S T S M V ST V SM D T DP(t) D M DM(t) C T C M R M Fig. 1: Unity pwer factr islated threephase rectifier a new seriescnnectin technique.. STEADYSTATE ANALYSS V T V M V (t) The Sctt cnnectin is realized with tw single phase transfrmers, T M and T T. The primary windings are fed by tw different vltages, V AO (t) e V CB (t), that are generated frm a symmetrical three phase system V A (t) V B (t) e V C (t). The cnnectin is represented at Fig. 2(a). V sect (t) and V secm (t) represent a tw phase vltage system, with a phase angle 90 between then. The phasr diagram is represented at Fig. 2(b). n the unity pwer factr islated threephase rectifier theretical study, nly the secndary circuitry will be taken int accunt. Therefre, the secndary windings f the Sctt

2 transfrmer are cnsidered t be ideal AC pwer surces. The fullbridge dide rectifiers were substituted by pwer surces that represent the rectified secndary vltage V int (t) and V inm (t). The tplgy f Fig. 1 can be reduced t the circuit f Fig. 3. Fig. 3: Threephase rectifier equivalent circuit. Fig. 2: (a) Sctt cnnected transfrmers, (b) phasr diagram f Sctt Transfrmer The secndary vltages f the Sctt transfrmer are sine and csine wavefrms [5]. Therefre, the rectified vltages at the inputs f the bst cnverters are: VinT () t = sin( w t) (1) V () t = V cs( w t) (2) inm p The instantaneus average duty cycles f the switches are: dt () t = 1 sin( w t) (3) dm () t = 1 cs( w t) (4) VM The purpse f using a bst PFC is t crrect the pwer factr f the structure by frcing the inductr current t fllw the shape f the rectified secndary vltage. The bst inductr currents are, therefre, images f the rectified secndary vltages f (1) and (2) LT () t = Lp sin( w t) (5) LM () t = Lp cs( w t) (6) Where: Lp is the peak value f the bst inductr current. The current thrugh the switch f a bst cnverter is the current thrugh the bst inductr multiplied by the duty cycle. n the same manner, the current thrugh the bst dide is the current thrugh the bst inductr multiplied by the cmplementary duty cycle. Therefre, the currents thrugh the bst dides are defined as: DT () t = [1 dt ()] t LT () t (7) () t = [1 d ()] t () t (8) DM M LM Substituting (3), (4), (5) and (6) int (7) and (8) it is btained: 2 DT ( t) = Lp sin( w t) (9) 2 DM () t = Lp cs( w t) (10) V M Cnsidering a balanced lad, the resulting equivalent circuit can be seen in Fig. 4. DT (t) DM (t) C T C M n 1 V T (t) V M (t) R R V (t) n 2 Fig. 4: Equivalent circuit f the utput filter.

3 Fr the equatins f the nde n 1 and n 2, is btained the differential equatins given by: dv ( T ( t)) ( t) C T DT() t dt R (11) dv ( M ( t)) VM ( t) C M DM() t dt R (12) Slving the differential equatins is btained: V V T M Lp R w R CT V t () t = 2 8 w R C ( ( )) T Lp R w R CM V t VM () t = 2 8 w R C ( ( )) M (13) (14) Where V1 () t = cs(2 w t) 2 w R CT sin(2 w t) and V2 () t = cs(2 w t) 2 w R CM sin(2 w t). The V (t) is defined as the sum f the capacitrs vltage f the utput filters: V () t = V () t V () t (15) T M Substituting (13) e (14) int (15) and suppsing C T =C M is btained that: V () t = 2 K R (16) Lp v The high frequency cmpnents f current were discarded by cnsidering nly the instantaneus average values f the bst dide currents. Even s, ideally, the high frequency cmpnents f the current wuld flw thrugh utput capacitr, leaving the DC cmpnent free t flw thrugh the lad, resulting in a cnstant vltage utput. The utput pwer f the rectifier is cnstant, which is an advantage f the tplgy since the utput capacitr des nt need t cpe with any lw frequency pwer fluctuatin.. CONTROL STRATEGY Each bst PFC presents its wn current cntrl by means, as [6] and [7]. The external vltage lp is used fr each bst PFC in rder t guarantee the balance f the split DC bus vltage. A cmplete blck diagram f the cntrl lps can be seen in Fig. 5. Fig. 5: Cmplete blck diagram f the cntrl lps. Where: Vref is the reference vltage, ref T and ref M are the references current, C VM (s) and C VT (s) are the vltage cmpensatr, C T (s) e C M (s) are the current cmpensatr and V T e V M, are the utput vltage f each bst PFC. A. Current lp nstantaneus average current cntrl is ne f the mst widely methds used t crrect the pwer factr f rectifiers. This technique cnsists f mnitring and cntrlling the bst inductr current by means f high frequency switching, s that current fllws a sinusidal reference with minimum errr. The currenttcntrl transfer functin f the cnverter (H it (s) and H im (s)) was btained frm Fig. 4, and can be seen in (17). LT () s = HT () s = dt() s s LT (17) LM () s VM = HM () s = d () s s L (18) M The current lp is cnsidered t be much faster than the vltage lp and, therefre, its clsedlp transfer functin can be simplified and represented as the current sensr cnductance 1/R sh. This simplificatin des nt cmprmise the dynamics f the vltage lp because the simplified and cmplete clsedlp transfer functins f the current lp are identical at the frequency range f the vltage lp. M

4 B. Vltage lps T cntrl the vltage it is used tw vltage cntrl lps. A vltage cntrl lp is applied fr each bst PFC. A blck diagram f the vltage lps can be seen in Fig. 6. Bth transfers functins f the plant vltages lp were btained frm mdel f Fig. 4 and can be seen in (19) and (20). The equivalent series resistance (Rse) f the utput capacitr was taken int accunt. S R Rse C Rse M H () s = (19) VM V ( R Rse) S C ( R Rse) M H VT S R Rse C Rse T () s = V ( R Rse) S C ( R Rse) T (20) 29.A 20.A 10.A 0A 10.A 20.A 29.A 630ms 635ms 640ms 645ms 650ms 655ms 660ms 665ms 670ms Time Fig. 7: Line currents A (t), B (t) and C (t). n Fig. 8 shws the utput vltage f the each bst PFC, V T (t) and V M (t), and utput vltage V (t). Fig. 8: Output vltage V T (t), V M (t) and V (t)/2. The secnd simulatin aims t verify the perfrmance f the cntrl lps when the rectifier suffers lad variatins, frm 50% f the rated lad t 100%. The results fr the line currents can be seen in Fig A 20A 10A 0A 10A 20A Fig. 6: Vltage lp blck diagram. V. SMULATON RESULTS The results f tw simulatins are presented t check the validity f the study until this pint. The first simulatin aims t verify the perfrmance f the current lp. n Fig. 7 shws the line currents A (t), B (t) and C (t). The ttal harmnics distrtins (THD) f the line currents fr full lad peratin are: THD A =3.15%, THD B =3.10% e THD C =3.01% 30A 350ms 360ms 370ms 380ms 390ms 400ms 410ms 420ms 430ms 440ms 450ms Time Fig. 9: Line currents after a 50% increase in the lad. n Fig. 10 shws the utput vltage f the each bst PFC, V T (t) and V M (t), and utput vltage V (t), when the rectifier suffers a lad variatins, frm 50% f the rated lad t 100%.

5 410V 405V The THD f the line currents were: 4.7%, 4.8% and 4.5%. They are near sinusidal in shape. The pwer factr per phase was: 0.99, 0.99 and 0.99 respectively. 400V 395V 390V 385V 380V 0.75s 0.80s 0.85s 0.90s 0.95s 1.00s 1.05s 1.10s Time Fig. 10: Vltages V T (t) and V M (t) t a lad unbalanced. V EXPERMENTAL RESULTS A labratry prttype f the islated threephase rectifier based n the Sctt transfrmer with split DC bus was implemented t prve the theretical studies. Bth f the PFC mdules are cntrlled by Unitrde UC3854B. The design specificatins f the prttype can be seen in Table 1. Fig. 12: Phase vltage V A (t) (100V/divisin) and current A (t) (20A/divisin) Table 1: Design specificatins. Parameter Value Line frequency 60 Hz RMS line vltage 380 V Rated pwer 12 kw Output vltage 800 Vdc Switching frequency 20 khz Fig. 11 shw a phtgraph f the labratry prttype. Fig. 13: Phase vltage V B (t) (100V/divisin) and current B (t) (20A/divisin) Fig. 11: Phtgraph f the labratry prttype. Fig. 12, Fig. 13 and Fig. 14 shw the experimental results f the 12 kw prttype. The THD f the line vltages were 3.05%, 3.44% and 3.68%. Fig. 14: Phase vltage V C (t) (100V/divisin) and current C (t) (20A/divisin) Fig. 15 shw the input currents T (t) and M (t) f each PFC which are 90 phaseshifted and the amplitudes are equal and the utput pwer equal.

6 V. CONCLUSONS Fig. 15: Currents T (t) and M (t) at each PFC (20A/divisin) Fig. 16 shw the utput vltages V M (t), V T (t) and V (t)/2. n this paper a simplified cntrl technique fr unity pwer factr islated threephase rectifier with split DC bus, based n the Sctt transfrmer is presented. Using tw standard singlephase PFC mdules where each mdule is rated fr half the utput pwer. The resulting input line currents are near sinusidal in shape. The maximum vltage n the switches is V/2. This facts allws the use f lwer vltage switches which can allw the use f pwer MOSFET substituting traditinal GBTs. That wuld take t the increase the maximum frequency f peratin in the cnverters, making pssible a reductin f lsses and size. Frm the steadystate analysis, it was shwn that the utput pwer f the rectifier is cnstant, which is an advantage f the tplgy since the utput capacitr des nt need t cpe with any lw frequency pwer fluctuatin. A 12kW labratry prttype was implemented. The experimental results demnstrate the perfrmance f the prpsed system. REFERENCES Fig. 16: Output Vltages ripple (5V/divisin). Fig. 17 and Fig. 14 shw the experimental results t verify the perfrmance f cntrl lps when the rectifier suffers lad variatins, frm 67% f the rated lad t100%. [1] EEE Recmmended Pratictices and Requirements fr harmnics Cntrl in Eletric Pwer Systems, EEE Std. 519, [2] A. Ruffer and Ch.B. Andrianirina, A symmetrical 3phase 2switch PFCpwer supply fr variable utput vltage, Sympsium EPE 95: Eurpean Cnference n Pwer Electrnics and Aplicatins, Spain, [3] S. K. T. Miller and. Barbi, Practical aspects f the unity pwer factr islated threephase rectifier based n the Sctt transfrmer, Applied Pwer Electrnics CnferenceAPEC 2005, Austin, TX, [4] S. K. T. Miller and. Barbi, Unity pwer factr islated threephase rectifier, 6 th.nduscon nternacinal Cnference n ndustrial Applicatins, Jinville, Brazil, [5] S. K. T. Miller, Unity pwer factr islated threephase rectifier based n the Sctt transfrmer (in Prtuguese), Master s Degree Dissertatin, Federal University f Santa Catarina, nstitute f Pwer Electrnics, [6] A. de Suza, Singlephase high pwer factr rectifiers with reduced cnductin lsses and sftswitching (in Prtuguese) Ph.D. thesis, Federal University f Santa Catarina, nstitute f Pwer Electrnics, [7] P. C. Tdd, UC3854 cntrlled pwer factr crrectin circuit design, Unitrde Crp., Merrimack, NH, Unitrde Applicatin Nte U134, Fig. 17: Current T (t) and Vltage V T (t) after a 33% increase in the lad (20A/divisin).