Harmonic Limiting Standards and Power Factor Correction Techniques

Transcription

1 Harmnic Limiting Standards and Pwer Factr Crrectin Techniques P. Tenti and G. Spiazzi Department f Electrnics and Infrmatics University f Padva ia Gradenig 6/a, Padva - ITALY Phne: Fax: tenti@dei.unipd.it spiazzi@dei.unipd.it

2 OUTLINE - BASICS OF POWER FACTOR CORRECTION - REIEW OF HARMONIC STANDARDS - BASICS OF SINGLE-PHASE PFC TOPOLOGIES AND CONTROL - CONTROL TECHNIQUES FOR SINGLE-PHASE PFC'S AND COMMERCIAL CONTROL IC'S - INSULATED TOPOLOGIES - TECHNIQUES FOR IMPROING OUTPUT OLTAGE CONTROL SPEED - BASICS OF SOFT-SWITCHING TECHNIQUES - SMALL-SIGNAL MODELING - SINGLE-PHASE APPLICATION EXAMPLES 2

3 POWER FACTOR DEFINITION Input vltage and current are peridic wavefrms with perid T i. Pwer factr PF: PF i, I rms P i,rms where P is the average pwer: 1 P = T i T i v i i i dt and i,rms and I i,rms are : 1 2 i, rms v i dt T i T i 1 2 I i, rms i i dt T i T i 3

4 POWER FACTOR DEFINITION Being vltage and current peridic wavefrms we can write in Furier series: v i i i = = I k= 1 k= 1 2 2I k k sin sin ( kω + φ ) i k ( kω + γ ) i k 0, I 0 = average values k, I k = RMS values f harmnics The average pwer is: P = 0I 0 + k I k cs ( φ γ ) k k CONSEQUENCE: Current harmnic terms cntributes t active pwer nly in the presence f vltage harmnic terms f the same frequency. POWER FACTOR DEFINITION 0 PF 1 4

5 PF = 1 nly if current and vltage are prprtinal Pwer Factr Crrectin An ideal Pwer Factr Crrectr (PFC) takes frm the supply a current which is prprtinal t the supply vltage R em v i i = emulated resistance i 5

6 POWER FACTOR DEFINITION PARTICULAR CASE: SINUSOIDAL INPUT OLTAGE PF = I cs I ( φ ) i,rms 1 = I I 1 i,rms cs ( φ ) 1 Il DF..= I i,rms = DISTORTION FACTOR cs(φ 1 ) = DISPLACEMENT FACTOR D.F. 1 =, THD 1+ ( THD) 2 = I 2 i, rms I 1 I 2 1 (THD = Ttal Harmnic Distrtin) 6

7 PF = 1 implies: POWER FACTOR REQUIREMENTS zer displacement between vltage and current fundamental cmpnent (φ 1 = 0) zer current harmnic cntent EXAMPLES: cs(φ 1 ) = 0, D.F. 0 In bth cases PF<1 cs(φ 1 ) 0, D.F. = 0 7

8 WHY POWER FACTOR CORRECTION Increased surce efficiency - lwer lsses n surce impedance - lwer vltage distrtin (crss-cupling) - higher pwer available frm a given surce Reduced lw-frequency harmnic pllutin Cmpliance with limiting standards (IEC 555-2, IEEE 519 etc.) 8

9 BASICS OF ACTIE POWER FACTOR CORRECTION 9

10 POWER FACTOR CORRECTION TECHNIQUES PASSIE METHODS: LC filters pwer factr nt very high bulky cmpnents high reliability suitable fr very small r high pwer levels ACTIE METHODS: high-frequency cnverters high pwer factr (appraching unity) pssibility t intrduce a high-frequency insulating transfrmer layut dependent high-frequency harmnics generatin (EMI prblems) suitable fr small and medium pwer levels 10

11 ACTIE POWER FACTOR CORRECTION DEFINITION: Pwer Factr Crrectr (PFC): AC/DC cnverter with sinusidal current absrptin (Current Prprtinal T Supply ltage) v i i i = = sen I i i sen ( ϑ) ( ϑ), ϑ = ω t i The cnverter behaves like an equivalent resistance R em given by: R em = I i i 11

12 ACTIE POWER FACTOR CORRECTION: BASIC CONSIDERATIONS Input pwer: p i 2 ( ϑ) = v i ( ϑ) i i ( ϑ) = 2 i,rmsi i,rmssin ( ϑ) = I ( 1 cs( 2ϑ) ) i,rms i,rms = Cnsidering unity efficiency: I = P= I i,rms i,rms P = utput pwer 12

13 PFC WITH CAPACITIE FILTER ASSUMPTIONS: cnstant utput vltage unity efficiency n lw-frequency pulsating energy stred in the dc/dc stage ( ϑ ) = i' ( ϑ) p i 13

14 PFC WITH CAPACITIE FILTER i ( ϑ) = p ( ϑ) i 2 i ' ( ϑ) = average value f ' ( ϑ) = 2Isin ( ϑ) i in a switching perid ltage cnversin rati M': M ( ϑ) = v g ( ϑ) = i g i ( ϑ) ( ϑ) Lad seen by the dc/dc stage: R ( ϑ) = i ( ϑ) = M ( ϑ) 2 v i g g ( ϑ) ( ϑ) = M 2 ( ϑ) R em 14

15 PFC WITH CAPACITIE FILTER R R ( ϑ) = 2 2 sin M M ( ϑ) =,M = sin ϑ ( ϑ) ( ) g Fr a PFC we have: R M ( ϑ) ( ϑ) 2 = R em a dc/dc cnverter when used as rectifier perates as a PFC with cnstant cntrl if : M ( ϑ) R ( ϑ) 15

16 PFC WITH CAPACITIE FILTER OUTPUT FILTER DESIGN Output filter capacitr current: i c ( ϑ) = i' ( ϑ) I = I cs( 2ϑ) If is the desired peak-t-peak utput vltage ripple, then: I C ω i 16

17 PFC WITH INDUCTIE FILTER ASSUMPTIONS: cnstant utput current unity efficiency n lw-frequency pulsating energy stred in the dc/dc stage pi ( ϑ) v' ( ϑ) = I v ' ( ϑ) = average value f ' ( ϑ) = 2sin 2 ( ϑ) v in a switching perid 17

18 PFC WITH INDUCTIE FILTER ltage cnversin rati M': ( ϑ) ( ϑ) ( ϑ) v' ig M ( ϑ) = = = 2M sin v I g ( ϑ) Lad seen by the dc/dc stage: R ( ϑ) = v' ( ϑ) 2 I = 2Rsin ( ϑ) 18

19 POWER FACTOR CORRECTORS: STANDARD CONFIGURATION TWO STAGE PFC: CASCADE CONNECTION PREREGULATORS: AC/DC cnverters with high pwer factr and pr utput vltage regulatin LOW EFFICIENCY: THE SAME POWER IS PROCESSED TWICE 19

20 BASIC PREREGULATORS: BOOST TOPOLOGY CHARACTERISTICS: Inherent input filter (lw input current harmnic cntent) Simple tplgy high pwer factr Output vltage greater than peak input vltage n start-up r shrt circuit prtectin n high-frequency insulatin 20

21 BASIC PREREGULATORS: BOOST TOPOLOGY Assumptin: CCM OPERATION switching frequency much greater than line frequency (quasi-statinary apprach). Main wavefrms in a switching perid 21

22 BASIC PREREGULATORS: BOOST TOPOLOGY OPERATION AS DC/DC CONERTER ltage cnversin rati : M d = duty-cycle = 1 1 d OPERATION AS AC/DC CONERTER In rder t draw a sinusidal current the duty-cycle must be mdulated during the line perid: d ( ϑ) = 1 g sin ( ϑ) (This is an apprximatin because CCM peratin cannt be maintained during the whle line perid) 22

23 BASIC PREREGULATORS: BUCK + BOOST TOPOLOGY CHARACTERISTICS: S 1 and D 1 prvide start-up and shrt circuit prtectin buck-mde peratin fr v g higher than utput vltage and bst mde-peratin fr v g lwer than utput vltage high cnductin lsses (fur semicnductrs in series) 23

24 BASIC PREREGULATORS: FLYBACK TOPOLOGY CHARACTERISTICS: Simple tplgy high pwer factr with cnstant duty-cycle in Discntinuus Cnductin Mde (DCM) peratin inherent start-up and shrt circuit prtectin high-frequency insulatin transfrmer high input current harmnic cntent 24

25 BASIC PREREGULATORS: FLYBACK TOPOLOGY DCM OPERATION Main wavefrms in a switching perid 25

26 BASIC PREREGULATORS: FLYBACK TOPOLOGY DCM OPERATION OPERATION AS DC/DC CONERTER ltage cnversin rati : M = d, k = k d = duty-cycle L = transfrmer magnetizing inductance (primary side) R = lad resistance T s = switching perid M 2L RT s R autmatic PFC when used as rectifier OPERATION AS AC/DC CONERTER Average input current: i g ( ϑ) = v g ( ϑ) L d 2 T s At cnstant duty-cycle and switching frequency the input current is sinusidal 26

27 CONTROL TECHNIQUES FOR SINGLE-PHASE PFC'S AND COMMERCIAL CONTROL IC'S 27

28 BOOST PREREGULATOR PEAK CURRENT CONTROL Input current wavefrm 28

29 PEAK CURRENT CONTROL CHARACTERISTICS: CONSTANT SWITCHING FREQUENCY CONTINUOUS CONDUCTION MODE (CCM) OPERATION - lw device current stresses - lw RMS current - small EMI filter POSSIBILITY TO SENSE ONLY SWITCH CURRENT - efficiency imprvement - pssibility t implement a pulse-by-pulse current limit SUBHARMONIC OSCILLATIONS (fr duty-cycle > 50%) LINE CURRENT DISTORTION (increases fr high line vltages, light lad and high amplitude f cmpensating ramp) COMMUTATION NOISE SENSITIITY HARD REERSE RECOERY OF FREEWHEELING DIODE (increased cmmutatin lsses and EMI) 29

30 PEAK CURRENT CONTROL IDEAL REFERENCE CURRENT WAEFORMS 3 I ref [A] I ref [A] T i 0 0 T i i =115 rms i =230 rms DISTORTION REDUCTION TECHNIQUES ADDING A DC OFFSET TO CURRENT REFERENCE (functin f bth line vltage and lad current) PROGRAMMED DISTORTION CURRENT REFERENCE - line dependent DC ffset - cnstant ffset plus sft clamp 30

31 CURRENT CLAMPING CONTROL CHARACTERISTICS: ERY SIMPLE CONTROL STRUCTURE LINE CURRENT DISTORTION BELOW 10% FOR LIMITED LOAD AND LINE ARIATIONS UNIERSAL INPUT OLTAGE OPERATION CANNOT BE EASILY ACCOMPLISHED 31

32 BOOST PREREGULATOR AERAGE CURRENT CONTROL Input current wavefrm 32

33 AERAGE CURRENT CONTROL CHARACTERISTICS: CONSTANT SWITCHING FREQUENCY CONTINUOUS CONDUCTION MODE (CCM) OPERATION - lw device current stresses - lw RMS current - small EMI filter COMPLEX CONTROL SCHEME - need f inductr current sensing - need f a multiplier COMMUTATION NOISE IMMUNITY HARD REERSE RECOERY OF FREEWHEELING DIODE (increased cmmutatin lsses and EMI) SEERAL CONTROL IC's AAILABLE 33

34 BOOST PREREGULATOR HYSTERETIC CURRENT CONTROL Input current wavefrm 34

35 HYSTERETIC CURRENT CONTROL CHARACTERISTICS: WIDE SWITCHING FREQUENCY ARIATION CONTINUOUS CONDUCTION MODE (CCM) OPERATION - lw device current stresses - lw RMS current - small EMI filter COMPLEX CONTROL SCHEME - need f inductr current sensing - need f a multiplier COMMUTATION NOISE SENSITIITY HARD REERSE RECOERY OF FREEWHEELING DIODE (increased cmmutatin lsses and EMI) SMALL INPUT CURRENT DISTORTION NEAR ZERO CROSSING OF LINE OLTAGE TO AOID HIGH SWITCHING FREQUENCY 35

36 BOOST PREREGULATOR BORDERLINE CONTROL (Operatin at the bundary between DCM and CCM) Input current wavefrm 36

37 BORDERLINE CONTROL CHARACTERISTICS: AUTOMATIC PFC (CONSTANT SWITCH ON TIME) ARIABLE SWITCHING FREQUENCY (functin f lad current and instantaneus line vltage) DISCONTINUOUS CONDUCTION MODE (DCM) OPERATION - high device current stresses - high RMS current - large EMI filter - reduced switch turn n lsses and increased turn ff lsses SIMPLE CONTROL SCHEME - n need fr a multiplier (hwever sme IC's make use f it) - need fr sensing the instant f inductr current zering SOFT RECOERY OF FREEWHEELING DIODE 37

38 BOOST PREREGULATOR DISCONTINUOUS CURRENT PWM CONTROL Input current wavefrm 38

39 DISCONTINUOUS CURRENT PWM CONTROL CHARACTERISTICS: CONSTANT SWITCHING FREQUENCY DISCONTINUOUS CONDUCTION MODE (DCM) OPERATION - high device current stresses - high RMS current - large EMI filter - reduced switch turn n lsses and increased turn ff lsses NO NEED OF CURRENT SENSING SIMPLE PWM CONTROL INPUT CURRENT DISTORTION (WITH BOOST CONERTER) - distrtin can be reduced by subtracting a fractin f rectified line vltage frm the errr vltage r by mdulating the clck frequency with rectified line vltage SOFT RECOERY OF FREEWHEELING DIODE 39

40 FLYBACK PREREGULATOR DCM OPERATION Input current wavefrm 40

41 DCM OPERATION CHARACTERISTICS: AUTOMATIC PFC (CONSTANT SWITCH ON TIME) CONSTANT SWITCHING FREQUENCY DCM OPERATION - high device current stresses - high RMS current - large EMI filter - reduced switch turn n lsses and increased turn ff lsses NO NEED OF CURRENT SENSING SIMPLE PWM CONTROL SOFT OF RECOERY OF FREEWHEELING DIODE 41

42 FLYBACK PREREGULATOR CCM OPERATION - CHARGE CONTROL Main wavefrms 42

43 CCM OPERATION - CHARGE CONTROL CHARACTERISTICS: CONSTANT SWITCHING FREQUENCY CONTINUOUS CONDUCTION MODE (CCM) OPERATION - lw device current stresses - lw RMS current - relatively large EMI filter (current ripple is small, but input current is discntinuus) SUBHARMONIC OSCILLATIONS (fr duty-cycle > 50%) COMPLEX CONTROL SCHEME - need f inductr current sensing - need f a multiplier COMMUTATION NOISE IMMUNITY HARD REERSE RECOERY OF FREEWHEELING DIODE (increased cmmutatin lsses and EMI) 43

44 CONTROL IC'S Cnstant frequency peak ML4812 (Micr Linear) current cntrl TK84812 (Tk) Cnstant frequency UC1854/A/B family (Unitrde) average current cntrl UC1855 (Unitrde) TK3854A (Tk) ML4821 (Micr Linear) TDA4815, TDA4819 (Siemens) TA8310 (Tshiba) L4981A/B (SGS-Thmsn) LT1248, LT1249 (Linear Tech.) Hysteretic cntrl CS3810 (Cherry Semic.) Brderline cntrl TDA4814, TDA4816, TDA4817, TDA4818 (Siemens) SG3561 (Silicn General) UC1852 (Unitrde) MC33261, MC33262(Mtrla) L6560 (SGS-Thmsn) Tw stage PFC with UC1891/2/3/4 family (Unitrde) average-current cntrl ML4824, ML4826 (Micr Linear) TK65030 (Tk) Tw stage PFC with ML4819 (Micr Linear) peak-current cntrl TK84819 (Tk) Buck-bst cnstant ML4813 (Micr Linear) frequency autmatic cntrl 44

45 INSULATED POWER FACTOR CORRECTOR TOPOLOGIES 45

46 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS DCM OPERATION Cuk cnverter Sepic cnverter 46

47 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS DCM OPERATION Inductr and dide current wavefrms during a switching perid fr a Sepic cnverter DCM peratin = dide current zeres during switch turn ff interval 47

48 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS DCM OPERATION Dide current = sum f inductr currents CONSEQUENCE: By chsing suitable values fr inductrs L 1 and L 2 it is pssible t btain a lw high-frequency input current ripple 48

49 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS Simulated wavefrms f a Sepic preregulatr c1 49

50 CHARACTERISTICS: CUK PREREGULATORS CONSTANT SWITCHING FREQUENCY GOOD TRANSFORMER EXPLOITATION DCM OPERATION - high device current stresses - small EMI filter - reduced switch turn n lsses and increased turn ff lsses - sft dide turn ff SIMPLE CONTROL SCHEME - n need f current sensing - n need f multiplier POSSIBILITY OF MAGNETIC COUPLING (REDUCTION OF MAGNETIC STRUCTURE SIZE AND INPUT CURRENT RIPPLE) 50

51 CHARACTERISTICS: SEPIC PREREGULATORS CONSTANT SWITCHING FREQUENCY POOR TRANSFORMER EXPLOITATION DCM OPERATION - high device current stresses - small EMI filter - reduced switch turn n lsses and increased turn ff lsses - sft dide turn ff SIMPLE CONTROL SCHEME - n need f current sensing - n need f multiplier POSSIBILITY OF MAGNETIC COUPLING (REDUCTION OF MAGNETIC STRUCTURE SIZE AND INPUT CURRENT RIPPLE) 51

52 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS CCM OPERATION EXAMPLE: Sepic cnverter with average current mde cntrl PROBLEM: design f the inner current lp 52

53 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS CCM OPERATION G id Transfer functin between duty-cycle and input current: () s = where D'=1-D. D 2 D L APPROXIMATION: G 2 + id D D 2 L 1 () s sl (fr the bst preregulatr is: G Ic D L 2C L 2 s + s D D D L 2 1L2C1 s 1+ s 2 2 D L 2 + D L1 D 1 Sepic id () s D depends n input vltage sl Cuk D g + n g + n I c I1+ I2 I + ni 2 C 1 C 1 C n C C 1 2 a a + n C 2 2 L 2 L 2 L n 2, i.e. cnstant gain) b b 53

54 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS 60 db CCM OPERATION Transfer functin plt Gid () s 40 a) 20 0 b) KHz Frequency Gid () s 0 deg a) -90 b) KHz Frequency a) π=π/2, b) π=π/18 54

55 PREREGULATORS BASED ON CUK AND SEPIC CONERTERS CCM OPERATION A damping R d -C d netwrk acrss energy transfer capacitr C 1 is used t prperly shape the transfer functin 60 db Gid () s 40 a) 20 0 b) KHz Frequency 0 deg Gid () s a) -90 b) KHz Frequency a) π=π2, b) π=π/18 55

56 INSULATED BOOST PREREGULATORS FULL-BRIDGE BOOST CONERTER TWO-SWITCH BOOST CONERTER A cupling winding t the input inductr is added t implement start-up and verlad prtectin: during these cnditins the cnverter perates in flyback mde 56

57 INSULATED BOOST PREREGULATORS CHARACTERISTICS: DIFFICULT TRANSFORMER IMPLEMENTATION - lw leakage inductance is essential NEED OF A SUITABLE CLAMP CIRCUIT HIGH OLTAGE STRESS IN THE TWO-SWITCH IMPLEMENTATION 57

58 PARALLEL RESONANT PREREGULATOR OPERATION AS DC/DC CONERTER ltage cnversin rati: M v p = = v g 2 π j 1 fn + Q f n, f n = f f r f r 1 =, Q = R C 2π LC L r p p r 58

59 PARALLEL RESONANT PREREGULATOR GAIN CHARACTERISTICS M Q= f n 59

60 PARALLEL RESONANT PREREGULATOR OPERATION AS AC/DC CONERTER Q ( θ) = R' Z ( θ) r = R 2sin 2 1 ( θ) Z r 20 Q factr variatin during a half line cycle 16 Qmin=2 Q ( θ ) π π 2 Near the zer crssing the circuit is lightly damped HIGH GAIN Near the peak f ac line the circuit is heavily damped LOW GAIN θ 60

61 PARALLEL RESONANT PREREGULATOR OPERATION AS AC/DC CONERTER CONSEQUENCE: Gd pwer factr (>90%) is btained withut active cntrl f the line current. NOTE: The same result hlds als fr the series/parallel (LCC) resnant cnverter. Fr this cnverter, an active cntrl is necessary t maintain zer vltage switching cnditin (peratin must remain n the right side f resnant peaks in all perating cnditins) 61

62 FAST RESPONDING POWER FACTOR CORRECTOR TOPOLOGIES OBJECTIES: COMPACTNESS HIGH POWER FACTOR TIGHT AND FAST OUTPUT OLTAGE REGULATION HIGH-FREQUENCY INSULATION 62

63 TWO STAGE PFC: PARALLEL CONNECTION Abut 68% f input pwer ges directly t the utput thrugh stage 1, while stage 2 prcesses nly 32% f input pwer 63

64 TWO STAGE PFC: PARALLEL CONNECTION P i < P Bst cnverter cntrls pwer factr Frward cnverter regulates utput C B stres energy C L is small 64

65 TWO STAGE PFC: PARALLEL CONNECTION P i > P t 2 cntrls pwer factr t 3 regulates utput 65

66 SINGLE STAGE PFC: PARALLEL POWER PROCESSING need fr several switches cmplex cntrl discntinuus input current at least fr a part f the line cycle (large EMI filter) 66

67 SINGLE STAGE PFC: PARALLEL POWER PROCESSING EXAMPLE: FLYBACK CONERTER P i < P t 2 cntrls pwer factr t 1 regulates utput C B stres energy C L is small 67

68 SINGLE STAGE PFC: PARALLEL POWER PROCESSING EXAMPLE: FLYBACK CONERTER P i > P t 1 cntrls pwer factr t 2 regulates utput 68

69 SINGLE STAGE PFC: BIFRED (Bst Integrated with Flyback Rectifier/Energy strage/dc-dc cnverter) Main wavefrms DCM input current ensures high pwer factr duty-cycle regulates utput C B stres energy C L is small SINGLE STAGE PFC: BIBRED 69

70 (Bst Integrated with Buck Rectifier/Energy strage/dc-dc cnverter) Main wavefrms DCM input current ensures high pwer factr duty-cycle regulates utput C B stres energy C L is small 70

71 SINGLE STAGE PFC: BIFRED, BIBRED CHARACTERISTICS: DCM OPERATION - high device current stresses - big EMI filter TANK CAPACITOR OLTAGE B IS LOAD AND LINE DEPENDENT - high device vltage stresses - limited lad range SOLUTIONS: ARIABLE FREQUENCY CONTROL - trade-ff between vltage stress and frequency range f cntrl DISCONTINUOUS OUTPUT CURRENT OPERATION 71

72 SINGLE STAGE PFC: S2IP2 FAMILY (Single-Stage Islated Pwer-factr crrected Pwer supplies) COMBINING SWITCHES a) when the ff vltages are the same b) when the ff vltage f the left switch is always higher than the ff vltage f the right switch c) when the ff vltage f a switch can be higher r lwer than the ff vltage f the ther switch 72

73 SINGLE STAGE PFC: S2IP2 FAMILY EXAMPLE: BOOST+FLYBACK 73

74 SINGLE STAGE PFC: S2IP2 FAMILY CHARACTERISTICS: SINGLE POWER STAGE WITH SINGLE HIGH-SPEED CONTROL LOOP (PWM CONTROL) TANK CAPACITOR OLTAGE B INDEPENDENT OF LOAD CURRENT DCM OPERATION OF BOTH PFC AND CURRENT-FED DC/DC CONERTER STAGES - high device current stresses - big EMI filter 74

75 SINGLE STAGE PFC: DITHER RECTIFIERS CONCEPT Adding t the lw-frequency input signal a high-frequency signal with amplitude higher than B increases the cnductin interval f the dead-zne element (dide-capacitr rectifier) 75

76 SINGLE STAGE PFC: DITHER RECTIFIERS EXAMPLE: OLTAGE DOUBLER + HALF-BRIDGE CONERTER The cnnectin is mved frm pint A t pint B. In this way, the high-frequency signal present n the inverter leg is added t the input vltage. An inductr is needed t smth the input current. 76

77 SINGLE STAGE PFC: DITHER RECTIFIERS EXAMPLE: OLTAGE DOUBLER + HALF-BRIDGE CONERTER CHARACTERISTICS: DCM OPERATION - high device current stresses - big EMI filter TANK CAPACITOR OLTAGE B IS LOAD AND LINE DEPENDENT - high device vltage stresses - limited lad range ARIABLE FREQUENCY CONTROL 77

78 TECHNIQUES FOR IMPROING OUTPUT OLTAGE CONTROL SPEED 78

79 NATURE OF THE PROBLEM - 1 GOAL: T imprve the dynamic respnse f pwer factr preregulatrs by manipulatin f the utput vltage feedback signal withut additinal sensing and with limited increase f cntrl cmplexity 79

80 NATURE OF THE PROBLEM - 2 Output vltage behavir: v () t = + v() t = sin( 2ω t) DC DC 2ω P i C i The vltage errr signal cntains a lw-frequency ripple at twice the line frequency CONSEQUENCE: the bandwidth f the vltage lp must be kept belw the line frequency in rder t avid input current distrtin 80

81 LINE FEEDFORWARD The lw-pass filter prvides a vltage prprtinal t the RMS input vltage which is squared and used in the multiplier t divide the current reference this avids heavy cmpensating actins by the vltage errr amplifier during line transients 81

82 CONTROL SCHEME WITH NOTCH FILTER A ntch filter tuned at twice the line frequency is inserted in the feedback path in rder t remve the utput vltage lw-frequency ripple frm the feedback signal COMMENTS: the filter must be well tuned with high quality factr the bandwidth is limited belw twice the line frequency 82

83 CONTROL SCHEME WITH SAMPLE & HOLD By sampling the utput vltage errr signal at a rate equal t the vltage ripple near zer crssing f the line vltage, the average utput vltage is sensed. COMMENTS: a high pwer factr is maintained in bth transient and steady-state cnditins the bandwidth is limited belw twice the line frequency 83

84 CONTROL SCHEME WITH RIPPLE COMPENSATION P v() t = sin( 2ωit) 2ω C i The utput vltage ripple is estimated and subtracted t the feedback signal s that the errr amplifier prcesses a ripple-free signal Under unity pwer factr cnditin, input pwer is given by: p where h is cnverter efficiency. i ηp () t = ηp cs( 2ω t) 2 i Errr signal v(t) can be estimated frm input pwer signal thrugh: Eliminatin f DC cmpnent Phase shifting f ninety degrees Multiplicatin by a prper gain 84

85 CONTROL SCHEME WITH RIPPLE COMPENSATION COMMENTS: G c ( s) = K s c in the presence f distrted input vltage, netwrk G c (s) turns ut t be cmplicated a secnd multiplier is needed the bandwidth can be increased abve twice the line frequency 85

86 CONTROL SCHEME WITH "REGULATION BAND" REGULATION BAND APPROACH TYPE 1 The current reference amplitude is kept cnstant as lng as the utput vltage remains within a defined regulatin band. When the utput vltage ges utside f this band a high gain cntrller changes rapidly the current reference amplitude s as t bring the utput vltage back int the regulatin band COMMENTS: crrect average utput vltage is btained nly at nminal cnditin in which the vltage ripple amplitude is equal t the dead zne amplitude slw input current dynamic respnse at lad step changes 86

87 CONTROL SCHEME WITH "REGULATION BAND" REGULATION BAND APPROACH TYPE 2 In rder t vercme the prblem represented by the steady-state errr n the utput vltage f the previus cntrl technique, a lw-bandwidth PI cntrller can be used which ensures stability and n DC errrs. When the utput vltage ges utside the band, the gain f the vltage errr amplifier is increased in rder t enhance the crrective actin 87

88 COMPARISON OF CONTROL STRATEGIES BOOST POWER FACTOR PREREGULATOR TABLE 1 - Cnverter parameters g=220rms =380 fs=50khz L=2mH C=470µF P=600W Errr vltage amplifier transfer functin G v K I s () s = 1 + s ωz TABLE 2 - Errr vltage amplifier parameter values S.C. N.F. S.H. B.#1 B.#2 R.C. KI Ka 8.8 Kd 223 ωz (Ka=13.8, Kb=1, Kd=21.4) S.C. = Standard Cntrl N.F. = Ntch Filter S.H. = Sample & Hld B.#1 = Regulatin Band TYPE 1 B.#2 = Regulatin Band TYPE 2 R.C. = Ripple Cmpensatin 88

89 STANDARD CONTROL LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] REF- Time Output vltage errr signal [s] [A] i g Time [s] Rectified input current NOTCH FILTER 89

90 LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] - REF Time Output vltage errr signal [s] [A] i g Time Rectified input current [s] 90

91 SAMPLE & HOLD LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] - REF Time Output vltage errr signal [s] [A] i g Time Rectified input current [s] 91

92 REGULATION BAND TYPE 1 LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] - REF Time Output vltage errr signal [s] [A] i g Time Rectified input current [s] 92

93 REGULATION BAND TYPE 2 LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] - REF Time Output vltage errr signal [s] [A] i g Time [s] Rectified input current 93

94 RIPPLE COMPENSATION LOAD STEP CHANGE FROM 100% TO 10% OF RATED POWER AND ICE ERSA (SIMULATED RESULTS) [] - REF Time Output vltage errr signal [s] [A] i g Time Rectified input current [s] 94

95 BASICS OF SOFT-SWITCHING TECHNIQUES 95

96 WHY SOFT TRANSITIONS? EMI (ELECTRO-MAGNETIC INTERFERENCE) REDUCTION - cmpliance with EMC (Elettr-Magnetic Cmpatibility) standards - input filter size reductin INCREASE OF SWITCHING FREQUENCY - cnverter size reductin - fast dynamic (high lp bandwidth) INCREASE OF EFFICIENCY 96

97 SOFT SWITCHING SOLUTIONS QUASI-RESONANT OR RESONANT TOPOLOGIES - increased current and/r vltage stresses - increased cnductin lsses (resnant cmpnents in series with main pwer path) - difficulties t maintain sft-switching cnditin fr wide line and lad ranges AUXILIARY CIRCUIT - "PWM like" current and vltage wavefrms - need f an auxiliary switch - little increase f cntrl cmplexity - sft-switching cnditin easily maintained fr wide line and lad ranges 97

98 REERSE RECOERY PROBLEM IN BOOST RECTIFIERS INCREASED SWITCHING LOSSES INCREASED EMI INCREASED DEICE CURRENT STRESSES 98

99 ZT-PWM BOOST CONERTER - 1 (ZT: Zer ltage Transitin) ASSUMPTIONS: cnstant bst inductr current during cmmutatin cnstant utput vltage Main wavefrms in a switching perid S S r DS I L I S I Lr D I D I L T T T T T T T

100 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 0 -T 1 ) S S r DS I S I L I Lr D I D I L T T T T T T T

101 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 1 -T 2 ) S S r DS I S I L I Lr D I D I L T T T T T T T

102 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 2 -T 3 ) S S r DS I S I L I Lr D I D I L T T T T T T T

103 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 3 -T 4 ) S S r DS I S I L I Lr D I D I L T T T T T T T

104 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 4 -T 5 ) S S r DS I S I L I Lr D I D I L T T T T T T T

105 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 5 -T 6 ) S S r DS I S I L I Lr D I D I L T T T T T T T

106 ZT-PWM BOOST CONERTER - 1 PRINCIPLE OF OPERATION (T 6 -T 0 ) S S r DS I S I L I Lr D I D I L T T T T T T T T 0 106

107 ZT-PWM BOOST CONERTER - 1 CHARACTERISTICS: SOFT-SWITCHING FOR BOTH MAIN SWITCH AND RECTIFIER CONSTANT FREQUENCY OPERATION HIGH EFFICIENCY ZERO-CURRENT TURN ON OF THE AUXILIARY SWITCH HARD TURN OFF OF THE AUXILIARY SWITCH 107

108 ZT-PWM BOOST CONERTER - 2 A "flying" capacitr C 1 is added in rder t achieve sft turn ff f the auxiliary switch. Mde 1 ( C1max <) 108

109 ZT-PWM BOOST CONERTER - 3 An auttransfrmer is added in series t the resnant inductr acting like a vltage surce t bring the resnant current t zer after the cmmutatin S r turns ff at zer current 109

110 SMALL-SIGNAL MODELING 110

111 SMALL-SIGNAL MODEL OF A PFC OPERATING IN CCM Pwer balance: vi ii = v0 i0 v i = i + vˆ where i i = I i + îi v 0 = 0 + vˆ i 0 = I 0 + î0 i 0 (RMS values) 111

112 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN CCM Under PFC cnditins the input current is sinusidal and its RMS value depends n cntrl vltage c : Substituting we btain: 2 i i v i = k v c v i k v c = v i 0 0 After perturbatin and linearizatin (small-signal apprximatin): 2 2 i c i k v i k v I0 0 = i + c v M i i v r i km v 1 0 = + c v 0 r0 where M 0 0 =, r = 0 I i

113 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN CCM In the same way, frm the pwer balance, we btain: 2 i i k v M i = c + v r i 0 M r i g i r 0 g f g c i 0 r M 2 k i I 0 0 2M r km i 113

114 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN CCM TRANSFER FUNCTION BETWEEN CONTROL OLTAGE AND G vc OUTPUT OLTAGE () s = r p vˆ vˆ 0 c = rp = g c 1 + scr r0 R L r + R 0 L p r p =R L /2 r p =R L r p = resistive lad cnstant current lad cnstant pwer lad 114

115 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN DCM (FLYBACK, CUK, SEPIC) Pwer balance: vi ii = v0 i0 v i = i + vˆ where i i = I i + îi v 0 = 0 + vˆ i 0 = I 0 + î0 i 0 (RMS values) 115

116 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN DCM Under PFC cnditins the input current is sinusidal and its RMS value depends n duty-cycle δ: i i Tv s i = 2L eq 2 δ where L eq depends n cnverter tplgy. Substituting we btain: 2 vt i 2L s eq 2 δ = v i 0 0 After perturbatin and linearizatin (small-signal apprximatin): 2 2 2YD i i 2YD i i i v I0 0 = i + δ v where Y i T = 2 L s eq 116

117 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN DCM 2 2YD i i M v 2YD i i 1 0 = i + δ v M r 0 0 where M 0 0 =, r = 0 I i 0 In the same way, frm the pwer balance, we btain: 2 ii = 2YD i i δ + D Yi v i 117

118 SMALL-SIGNAL MODEL FOR A PFC OPERATING IN DCM MODEL PARAMETERS M r i g i r 0 g f g c 2 0 2YD 2 2DY i i i i i I0 M 0 1 i DY i M 2Y D FLYBACK CUK SEPIC L eq L L1 L2 nl+ L n=transfrmer turns rati (N 2 /N 1 ) L L L + L TRANSFER FUNCTION BETWEEN DUTY-CYCLE G v AND OUTPUT OLTAGE () s = r p vˆ δˆ 0 = rp = g c 1 + scr r0 R L r + R 0 L p 118

119 DESIGN OF BOOST PFC OPERATING IN CCM WITH AERAGE CURRENT MODE CONTROL 119

120 POWER STAGE SCHEME R ' D ' i L D + in C f 1 D D 1 2 C f 2 L J 4 S Rp 1 C Z L + 0 D D 3 4 R s S Rp 2 - J J 1 2 J 3 J 5 J 6 CHARACTERISTICS: Input vltage: Output vltage: Output pwer: Switching frequency: in = RMS = 380 P = 600W fs = 70kHz 120

121 POWER STAGE DESIGN 1) Inductr peak current (average value in a switching perid) P = η P g where η is cnverter efficiency I η L 2 g = P I = Wrst case: minimum input vltage I L = = 992. A L 2P η g (1) 121

122 2) Input inductr value POWER STAGE DESIGN Duty-cycle in CCM: δ ( ϑ) ( ϑ) g tn = 1, δ = ; ϑ = ωit T s Peak-t-peak input current ripple: i L ( ϑ) = g ( ϑ) ( ϑ) L t n = f s g L δ( ϑ) (2) (3) The maximum ripple ccurs at half the input vltage peak. Frm the allwed ripple the input inductr value is fund. (example: relative ripple = 30% L = 0.46 mh. 122

123 3) Output capacitr value POWER STAGE DESIGN C I = ω i (4) where is the desired peak-t-peak vltage ripple and I is the utput current. (Example: relative ripple <5% C > 260 µf, we use C=470µF) 4) Switch peak current ( π 2) i L îs = Î L + = 10.9A 2 (5) 123

124 5) Switch RMS current POWER STAGE DESIGN RMS current is determined by first averaging the switch current ver a switching perid and secnd averaging ver the line perid. Neglecting the inductr current ripple we btain: I s, rms I where M M 2 M 3π = is vltage cnversin rati g Cnsidering the minimum input vltage we btain: Is, rms = 563. A. 6) Freewheeling dide peak current (average value) I = 2 I = 316. A (7) D, avg (6) 124

125 CONTROL STAGE DESIGN IC: SGS-THOMSON L4981A COMPONENT ALUES cc = 18 R7 = 3.3 kω R13 = 18 kω C4 = 100 nf R2 = 150 kω R8 = 3.3 kω R14 = 5.6kΩ C5 = 1 nf R3 = 1 MΩ R9 = 47 kω C6 = 68 pf R4 = 560 kω R10 = 33 Ω C1 = 15 nf C7 = 10 µf R5 = 33 kω R11 = 33 kω C2 = 220 nf C8 = 1 nf R6 = 1.2 MΩ R12 = 1.5 MΩ C3 = 220 nf C9 = 10 µf 125

126 CONTROL STAGE DESIGN IC: SGS-THOMSON L4981A 126

127 1) Shunt resistance RS: CONTROL STAGE DESIGN Chsing R s = 0.054Ω the pwer lss is: P R I 2 L R S 265. W (8) = = S 2 2) Switching frequency: f C8 and R11 determine the switching frequency: s = C 24. R 8 11, hertz (9) Chsing C8=1nF gives R11=33kΩ 3 Reference current IAC: I AC = R g 6 (10) The suggested value fr R6 is 1.2MΩ. Crrespndingly, IAC is between 106µA at minimum line vltage and 306µA at maximum line vltage. 127

128 4) Feedfrward vltage RMS: CONTROL STAGE DESIGN R3, C3, R4, R5, C4 frm a lw pass filter which must give at pin 7 a DC vltage between 1.5 and 6.5. Suggested values are: R3=1MΩ, R4=560kΩ, R5=33kΩ, C3=220nF, C4=100nF: = R 5 R + R + R RMS g g = α = (11) π This lw-pass filter must give a gd attenuatin at twice the line frequency. 5) Peak current limiter: We chse Ipk,lim=11A: I pk,lim = 100 A R 14 µ R S (12) frm which R14=5.6kΩ. 128

129 6) R7 and R8 values: CONTROL STAGE DESIGN If the current errr amplifier has enugh gain at line frequency we have: RS IL R7 IMULT OUT (13) = where IMULT-OUT is the multiplier utput current, which is related t the utput vltage f the vltage errr amplifier A-OUT by: I MULT OUT = I AC A OUT 2 RMS 128. which is valid if pin 6 (LFF) is cnnected t pin 11 (REF). (14) Impsing that the maximum input current ccurs with a vltage A-OUT=5, we btain R7=R8=3.3kΩ. 129

130 CONTROL STAGE DESIGN 7) Over vltage prtectin:,max R 1 + = 12 REF R 13 (15) Chsing R12=1.5MΩ and R13=18kΩ gives,max=425. 8) Sft-start: Cnnecting a capacitr between pin 12 and grund a ramp vltage is generated which causes the duty-cycle t vary frm minimum t nminal value. Suggested value: C9 = 10µF. 9) Feedback signal divider: REF = R R p2 + R p1 p2 (16) Rp1=1MΩ e Rp2=12kΩ + 4.7kΩ trimmer. As suggested a filter capacitr C7 = 10µF is cnnected between pin 11 (REF) and grund. 130

131 CURRENT REGULATOR DESIGN Apprximated pwer stage transfer functin (between duty-cycle and input current) fr frequency abve the utput filter crner frequency: G () s ( s) i g d() s sl i = = (17) 131

132 CURRENT REGULATOR DESIGN The current lp transfer functin is: T i () s = R G () s sl 1 sc s ri (18) where, sc = 5 is the amplitude f the internal ramp f the PWM generatr. m Current errr amplifier: () ( s) ωri ( 1 + sτzi ) G ri s = = () ( ) (19) εi s s 1 + sτ pi where 1 ωri = R 8 5 τ zi = R9 C5 τ pi R C = C 9 C + C ( C + C ) R 1 8 C 5 if C 5 >> C R C if C >> C 6 (20) (21) (22) 132

133 CURRENT REGULATOR DESIGN If fzi < fc < fpi where fc is the crssver frequency, then: R 9 G ri ( jωc ) R 8 R 9 2πfc L sc Ti ( jωc ) = 1 = R R 8 s (23) (24) As far as the phase is cncerned: ( jω ) f + arctg f f arctg f c c Ti c = = mϕ 180 (25) zi pi where mϕ is the desired phase margin. Given fc, the phase margin and chsing fs/2<fpi<fs s as t attenuate the high-frequency ripple R9, C5 and C6 values are btained. Example: fc = 15 khz, fpi = 50 khz and mϕ = 60 fzi = 3.5kHz, R9=47kΩ, C5=1nF, C6=68pF. 133

134 OLTAGE REGULATOR DESIGN Transfer functin between cntrl vltage and utput vltage: G v () s where, r p = r r = Z + Z L 0 c L () s rp = g c () s 1 + scrp g, rms g k M r, c =, =, M = I g, rms (26) (27) ZL = RL = r ZL = ZL = - RL resistive lad cnstant current lad cnstant pwer lad and k is defined by the relatin: I g, rms g, rms = v k c (28) In the L4981A cntrller, feedfrward term RMS eliminates the dependence f gain g c frm input vltage. 134

135 OLTAGE REGULATOR DESIGN Frm eqs. (13-14) we can write (R M =R 7 ): I g,rms = R R 7 S I MULT OUT = = R R R R 7 S 7 S R R g,rms 6 g,rms 6 A OUT 2 RMS A OUT 2 2 2α g,rms (29) which crrespnds t (28) if: k = 2R R 2 R S g,rms R 7 π R 3 + R 4 + R 5 2 (30) 135

136 OLTAGE REGULATOR DESIGN The vltage regulatr transfer functin is: G rv () s where ω rv = ε C v ( s) () s = ω s rv ( 1 + τ ) zv ( 1 + sτ ) R = R R C C R p2 REF p1+ p C2 R1 with R1=Rp1 Rp2 τ zv = R2 C2 τ = R C // C R C sec >> pv 2 pv ( 1 2 ) C1 (31) (C2>>C1) (32) (33) (34) Cnsidering a crssver frequency higher than the pwer stage ple we have: g jω c c ω C rvτzv =1 (35) Chsing fc = Hz, fi<fpv<2fi and a suitable phase margin, the regulatr parameters can be calculated. Example: fc = 20Hz, fpv = 70Hz and mϕ = 60 fzv = 5Hz, R2=150kΩ,C1=15nF, C2=220nF. 136

137 DESIGN OF A SEPIC PFC OPERATING IN DCM POWER STAGE SCHEME PROTOTYPE PARAMETERS g = 220 rms ± 20% = 36 P = 100W f s = 100 khz L 2 = 74 µh C 1 = 0.68 µf C 2 = 10 µf n =

138 1) Operatin as dc/dc cnverter. SEPIC MAIN EQUATIONS The vltage cnversin rati is: M M Ig D = = = n g I 1 D Ig D = = = (DCM) I K g (CCM) where n=n 2 /N 1 is transfrmer turns rati, D is duty-cycle and parameter K is given by: K Le =, with L RT e = s LL L + L 1 2 In the abve equatins T s is the switching perid and L 2 is the transfrmer magnetizing inductance. Critical parameter: K crit = ( 1 D) n 2 2 = 1 K > K crit 2 ( n + M) K < Kcrit CCM DCM 138

139 SEPIC MAIN EQUATIONS Average inductr current I 2 : I2 = n id = n I 2) Operatin as a rectifier. Inductr current wavefrms in DICM When perating as a rectifier, the dc input vltage g is substituted by the rectified line vltage: v g ( θ) = sin( θ) g where θ = ω i t. Cnsequently, the vltage cnversin rati becmes: m () θ = v g where M=/ g. = M ( θ) sin( θ) 139

140 SEPIC MAIN EQUATIONS Under pwer factr crrectin cnditins: i 2 () θ = n i () θ = n 2I () θ 2 D sin The apparent lad r(q) seen at the secndary side f the transfrmer is given by: r ( θ) = i D = R 2 ( θ) 2sin ( θ) Thus the parameter k becmes functin f angle q 2Le 2 k ( θ) = = 2K asin ( θ),k a = r T k crit ( θ) ( θ) = s sin 2 ( θ) ( θ) ( M + n sin ) 2 2L RT Fr the cnverter t perate in DCM the fllwing cnditin must be satisfied: K a < 2 1 ( M + n sin() θ ) 2 e s 140

141 SEPIC MAIN EQUATIONS The average current drawn by the cnverter, at cnstant duty-cycle and switching frequency, is sinusidal and in phase with the line vltage and is given by i g D 2 s () θ = v ( θ) 2L T e g = v g R ( θ) em where, R em Le = 2 2 DT s is the emulated resistance. The cnverter duty-cycle results: D = M 2K a 141

142 POWER STAGE DESIGN INPUT DATA: minimum and maximum input vltage peak value gmin, gmax ; utput vltage ; utput pwer P; switching frequency f s ; initial value fr transfrmer turns rati n. 142

143 POWER STAGE DESIGN DESIGN PROCEDURE: calculate minimum and maximum vltage cnversin rati M min, M max evaluate K a fr π= π /2 and M max (minimum line vltage) 1 K a = α, α = ( M + n) max find the value f inductance L e frm K a definitin find the value f duty-cycle D; calculate the value f inductances L 1 and L 2 frm L e and the desired input current ripple calculate device current and vltage stresses as well as peak inductr currents; repeat the prcedure fr different values f transfrmer turns rati; chse the slutin which best meets device ratings. 143

144 POWER STAGE DESIGN NOTE: particular attentin must be given t the selectin f capacitr C 1. Three cnstrains must be taken int accunt: vltage u 1 must fllw the input vltage shape withut distrsin its vltage ripple must be as lw as pssible C 1 shuld nt cause lw-frequency scillatins with inductrs L 1 and L