An FPGA-based Fully Digital Controller for Boost PFC Converter

Transcription

1 644 Jurnal f Pwer Electrnics, Vl. 15, N. 3, pp , May 015 JPE ISSN(Print): / ISSN(Online): An FPGA-based Fully Digital Cntrller fr Bst PFC Cnverter Li Lai * and Ping Lu * Schl f Micrelectrnics and Slid-State Electrnics, University f Electrnic Science and Technlgy f China, Chengdu, China Abstract This paper intrduces a nvel digital ne cycle cntrl (DOCC) bst pwer factr crrectin (PFC) cnverter. The prpsed PFC cnverter realizes the FPGA-based DOCC cntrl apprach fr single-phase PFC rectifiers withut input vltage sensing r a cmplicated tw-lp cmpensatin design. It can als achieve a high pwer factr and the peratin f lw harmnic input current ingredients ver universal lads in cntinuus cnductin mde. The trailing triangle mdulatin adpted in this apprach makes the acquisitin f the average input current an easy prcess. The cntrller implementatin is based n a bst tplgy pwer circuit with lw speed, lw-reslutin A/D cnverters, and ecnmical FPGA develpment bard. Experimental results demnstrate that the prpsed PFC rectifier can btain a PF value f up t and a minimum THD f at least 1.9% using a 10 W prttype. Key wrds: Cntinuus Current Mde, Digital Cntrl, Pwer Factr Crrectin I. INTRODUCTION Using a single-phase pwer factr crrectin (PFC) bst rectifier t imprve the pwer factr and energy quality f an electric system is necessary accrding t internatinal energy standards, such as IEC [1] and IEEE-519 []. Bst PFC cnverter is the mst ppular amng many tplgies because f its simplicity and significant dynamics perfrmance [3]. Numerus research results n the bst PFC cntrl apprach have been presented. The mst widely adpted cntrl methd fr bst PFC cnverters is the average current mde [4], [5]. Despite its many advantages, such as lw harmnics input current and insensitivity t nise, the inherent drawbacks f the bst PFC cnverter are the cmplicated tw-lp cntrl and three independent vltages r currents t be measured in sme applicatins. The ne-cycle cntrl (OCC) f bst PFC cnverters is prpsed in [6], which intrduces the nnlinear cntrl apprach with a simple structure and lw cst. The benefit f nnlinear cntrl lies in eliminating the need t sense the input vltage and in using a simple integratr t replace the cmplicated multiplier in the average current mde cntrl apprach. The OCC apprach is widely Manuscript received Oct. 3, 014; accepted Feb. 8, 015 Recmmended fr publicatin by Assciate Editr Hnnyng Cha. Crrespnding Authr: pingl@uestc.edu.cn Tel: , Univ. f Electrnic Science and Tech. f China * Schl f Micrelectrnics and Slid-State Electrnics, University f Electrnic Science and Technlgy f China, China 015 KIPE implemented in sme cmmercial bst PFC cntrl micrchips r slutins [7], [8]. Different mdificatins [9]-[11] have been reprted based n the OCC methd. Hwever, applicatins f the cnventinal OCC are limited mstly t the analg field. Digital implementatin bst PFC cnverters have attracted increasing attentin in recent years. Varius presented cnverters are based n the digital realizatin, mdificatin, and extensin f the average current cntrl apprach [1]-[19]. Given that the mst widely reprted cntrl apprach f digital PFC cnverters is implemented n DSP r micrcntrllers, the digital realizatin f the average current mde cntrl apprach based n FPGA is presented in [0]. Other cntrl methds are presented in [0]-[3]. A nvel detectin mechanism is prpsed in [3] based n the DSP implementatin fr mixed cnductin mde (MCM) digital cntrllers. A simple digital cntrl scheme is als prpsed in [3] t btain the accurate average current in discntinuus cnductin mde (DCM). Other cntrl appraches include the precalculated duty cycle cntrl presented in [0], [1]. As previusly presented, several digital OCC appraches have been reprted. The mst significant bstacle t implementing OCC apprach is imitating the integratin part in digital implementatin. An accumulatr is used in [] t calculate the sum f input current samples t btain the average input current value. This methd requires fast A/D cnverters and adds a heavy calculatin burden t the cntrller in every switching cycle.

2 An FPGA-based Fully Digital Cntrller fr 645 rectifier bridge AC C1 L GATE DRIVE S D C R1 R LOAD R3 dt S T S T S (1-d)T S T S T S (b) A/D i L [n] D CALCULATION G in PWM PI COMPENSATION DOCC cntrller + - V ref A/D V[n] dts/ T S T S (c) (1-d)/T S T S T S (d) Fig. 1. Bst PFC rectifier with DOCC cntrl. The current paper prpses an FPGA-based digital OCC (DOCC) bst PFC perating under Cntinuus Current Mde (CCM) cnditin. This bst PFC rectifier adpts the trailing triangle mdulatin methd t capture the average input current f every switching cycle. The cmpensatin part f the cntrller is designed n a new vltage lp small signal mdel withut an explicit current lp cmpensatin part, but results in a high pwer factr and lw THD level ver a large lad range. The rest f this paper is rganized as fllws. Sectin II intrduces the principle f the DOCC apprach, the input current sampling methd, and the system stability analysis. Sectin III describes the sketchy structure f the prpsed cntrller implemented n FPGA and the criteria f system implementatin issue. Sectin IV presents the experimental results fr a 10 W bst DOCC PFC prttype. Sectin V cncludes this paper. II. ANALYSIS OF THE DOCC APPROACH The basic bjective f a PFC rectifier is t ensure that the input current is synchrnized with the grid vltage (with the same frequency and phase), as shwn in Fig.1. This prcess can be written as i L = vingin, where i L is the average inductr current in ne switching cycle, v in is the rectified grid vltage, and G in is the emulated input admittance. Using the quasi-state apprximatin in the CCM bst PFC peratin and assuming v in and v are cnstant values in ne switching cycle T s, we btain v ( 1 d) = vin, where d is the switching duty rati and v is the utput vltage. The bjective f the PFC cntrller can be expressed as fllws: il = Ginvin = Ginv ( 1 d) (1) Eq. (1) indicates that the duty rati shuld be applied t the switching cnverter in every duty cycle. Given that v in is expressed in terms f v and d, sensing the input vltage is unnecessary. v is sampled by a lw-cst A/D cnverter. G in is cmputed by the cmpensatin part f the vltage lp, which will be analyzed in a detailed derivatin in the fllwing Fig.. Sketch map f the pulse width mdulatin (PWM) types. Trailing edge mdulatin. (b) Leading edge mdulatin. (c) Trailing triangle mdulatin. (d) Leading triangle mdulatin. sectins. The mst tricky prblem is the acquisitin f the average current f the duty cycle. Fur basic current sample methds (i.e., trailing edge mde, leading edge mde, trailing triangle mde, and leading triangle mde) are used in a switching pwer system, as shwn in Fig.. Triangle mdulatin is adpted in the DOCC current sampling peratin methd because trailing edge mdulatin r leading edge mdulatin is unsuitable in average current acquisitin. Given that the rectifier can enter the DCM mde, the current at the T s / instant can be difficult t track and sample. Hence, the trailing triangle mdulatin is utilized fr the prttype design in this paper. Fig. shws that the pwer switch is always turned n at the beginning f every switching cycle, but is turned ff at the dt s / instant. The switch is nt turned n until the (1 d/)t s instant. The sample current i L [n 1] at an instant is the average current f the (n 1)th switching cycle. The quasi-state apprximatin shws that the switching frequency is much faster than the input current frequency. Thus, we can take the sample average current i L [n 1] at an instant as the average current criterin i L [n] in the nth switching cycle by assuming tw cnsecutive switching cycles with the same average current. This apprximatin can prvide significant cnvenience in cntrl analysis and system implementatin. Adpting the trailing triangle mdulatin fr average current i L [n] acquisitin has the fllwing primary merits. 1) The average current f the switching cycle is btained thrugh a relatively simple methd withut the need fr an accumulatr []. This cnditin can save n hardware cnsumptin in FPGA implementatin. The current sampled at a fixed instant n the switching frequency makes the utilizatin f lw-cst and lw-speed A/D cnverters pssible. It als makes the design f sampling circuit easy. ) The average current criterin is acquired at the beginning f the switching cycle. This apprach leaves sufficient time t calculate the apprpriate duty rati fr the switching cycle nline. Assuming that the input current is higher than the criterin

3 646 Jurnal f Pwer Electrnics, Vl. 15, N. 3, May 015 sampling sampling 1 d i L G id a b G ic K il i avg [n-1] i avg [n] V ref V e G vc G in G v V dt s / (1-d/)T s T S T S Fig. 3. Input current sample peratin with trailing triangle mdulatin. K v (b) (b) Fig. 5. Sketch maps. Current-lp structure. (b) Vltage-lp structure. G k =1 Fig. 4. Rt lcus plt f T i ( fr implementatin n the prpsed DOCC PFC cntrller. value by sme disturbance r ther interference, the acquired average current is als higher. The duty rati f the fllwing switching cycle is lwer than the nrmal level t crrect the input current t the nrmal level based n Eq. (1). When the input current is lwer than the nrmal level, the ppsite prcess is implemented t crrect it. This mechanism guarantees that the fluctuatin f input current des nt influence the system stability. The small signal stability f cntrl law (Eq. 1) can be analyzed based n the quasi-state apprximatin frm anther perspective. The current lp cmpensatin transfer functin is expressed in the discrete dmain as fllws: d( ic( = il( G 1 = Ginv () In ne switching cycle vin v vin i L[ n + 1] = il[ n] + dts ( 1 d) Ts L L (3) The linearizatin f Eq. (3) yields the duty rati t current transfer functin as fllws: il( vts Gid = = (4) d( z 1 The discrete time current pen lp transfer functin is btained in Eq. (5) by cmbining Eq. (), Eq. (4), and the input current sampling cefficient K il. The sketch map f the current lp is shwn in Fig. 5. KiLTs Ti ( = KiLGid ( Gic( = (5) GinL( z 1) The rt lcus technique in Fig. 4 shws that the current lp is stable when the parameter G k = K il T s /G in L < 1, whereas the cnditin that guarantees the bst PFC cnverter that perates in CCM is G c = T s /G in L < 1 [4]. Fig. 6 illustrates the CCM, DCM, and MCM current perating mdes fr bst PFC cnverters. We can cnclude that the current lp f the DOCC bst PFC rectifier is always stable withut any explicit cmpensatin part when it always perates in the CCM cnditin [4]. The current rectifier lp is still pssibly stable (G k < 1) because the current sampling gain K il is generally less than 1 when the DOCC bst PFC perates in MCM r DCM (G c > 1). The emulated input admittance G in can be btained thrugh an analysis f the system vltage lp, as shwn in Fig. 5(b). Althugh mst analyses f the nnlinear-cntrl bst PFC is based n the small signal intrduced in [4], the current study simplifies the analysis by assuming that the pwer system efficiency clsely apprximates 1. Thus, Vinrms Iinrms = vi = P (6) The V inrms in Eq. (5) represents the rt mean square (RMS) value f input vltage v in, I inrms represents the RMS value f the input current, and i dentes the utput current f the system. Fig. 6 can be expressed as fllws: Iinref KvVinrmsGin I inrms = = (7) KiL KiL I inref dentes the RMS value f the input reference current, and K v is the utput vltage sampling cefficient. Cmbining Eqs. (6) and (7) results in the fllwing: KvVinrms Gin = vi (8) KiL The fllwing equatin is btained when the disturbance t Eq. (8) is added:

4 An FPGA-based Fully Digital Cntrller fr 647 i L MCM peratin CCM peratin DCM peratin T n / T ff T n / T s Fig. 6. Illustratin f the PFC perating in CCM, DCM, and MCM. vvinrms K K il ( G in in T s + g ) = ( V + v )( I + i ) (9) We then btain the fllwing after the small signal analysis f Eq. (9): KvV inrms I i = gin v (10) KiLV V The utput current can be expressed as fllws: dv P i = C + (11) dt v The small signal expressin f Eq. (10) is as fllws: i v d v I = C (1) dt V Cmbining Eqs. (10) and (1), the small signal relatinship between v and G in, after the discretizatin f the transfer functin by the zer-rder hld methd is btained in Eq. (13), where T ss represents the sampling time f the discretizatin prcess. v ( KvVinrmsTss Gv ( = = (13) K CV ( z 1) g ( il in Designing a stable feedback vltage lp is necessary t respnd t the lad variatin, parameter ffset f pwer devices, and input vltage V inrms fluctuatin. A tradeff exists between the utput vltage dynamics perfrmance and limited lp bandwidth in this part. The prprtin-integratin cmpensatin part G vc is used in this study t set the crssver frequency f the vltage lp at apprximately 0 Hz (with a 60 phase margin) t suppress the secnd harmnics f the utput vltage while guaranteeing the required vltage-lp dynamics perfrmance. The cmpensated vltage lp gain and phase margin are shwn in Fig. 7. III. IMPLEMENTATION ISSUES Determining the switching frequency f s is dependent n specific applicatin circumstances. A high switching frequency generally means a lw utput vltage ripple level under the same capacitr and inductr cnditin. A mre serius t Fig. 7. Clsed vltage-lp gains T v ( with the G vc cmpensatin scheme. inductr, µh DCM MCM CCM Output pwer, W Fig. 8. Illustratin f the bst PFC perating in different mdes. electrmagnetic interference prblem als ccurs, which causes lwer system efficiency. We set the switching frequency at apprximately 50 khz after the tradeff prcess. The switching perid being the integer multiples f the cntrller clck perid is simpler fr the design f the digital PWM (DPWM) functin. Thus, we determine f s = 48.8 khz in this prttype implementatin. The input inductr value affects the ripple level f the input current, as well as the current perating mde f the system shwn in Fig. 8. Eq. (1) shws that the entire cntrl system is based n the assumptin that the rectifier perates in the CCM mde. Eq. (14) divides the CCM and MCM regins as btained frm [4]. It determines the minimum inductr value fr the CCM peratin. Eq. (15) divides the DCM and MCM regins. We represent the bundaries between CCM, MCM, and DCM ver lad variatin in Fig. 8 while maintaining the input vltage V inrms (50 V), switching frequency f s (48.8 kh, and utput vltage V (80 V) cnstant. 1 Gin (14) Lfs Vin max ( 1 ) V Gin < (15) Lfs The inductr L shuld satisfy the fllwing relatin t guarantee the cntinuus input current during the peratin: Vin max L (16) fsiin max We btain L > 40 μh with P max = 18 W, V inmax = 71.7 V,

5 648 Jurnal f Pwer Electrnics, Vl. 15, N. 3, May 015 PWM signal Cyclne Ⅲ: EP3C6F484C6 FPGA FPGA develpment bard Electrnic lad Gate Driver 48.8kHz DPWM A/D i L [n] Gain3 G ine [n] Accumulatr Z -1 Multiplier Gain1 Gain Z -1 Glbal clck frequncy=50mhz Divider + V ref _ Output vltage sample V A/D V [n] Vltage regulatr Pwer experiment bard Islating transfrmer Pwer analyzer Fig. 9. Diagram f the prpsed PFC cntrller scheme. TABLE I CONVERTER SPECIFICATIONS Parameter Value Parameter Value f s 48.8 khz L 500 μh T s 0.5 μs R1 390 kω V inrms 50 V R 10 kω V 80 V R3 0.1 Ω C1 0.1 μf Gain1 C 1000 μf Gain 899 P 10 W Gain I inmax = 3.6 A, and f s = 97.6 khz. We then take L = 500 μh with a certain safety margin. The value f the utput capacitr C is calculated accrding t its hld time Δt. Hld time expresses the time duratin fr the capacitr vltage hld in a prescribed range withut any f the pwer surce incme. The said value can be expressed based n the law f cnservatin f energy: 1 C( V V ) max min = t Pmax (17) The utput vltage ripple shuld generally be σ < 5%. Given that the reference utput vltage is V = 80 V, V max = 84 V and V min = 76 V are btained. In this study, the utput capacitr value is calculated as 1000 μf when the hld time Δt is set as 5 ms. The cntrller implementatin based n FPGA can achieve multi-mdel system integratin with few peripheral devices and rutings. The parallel cmputing character f FPGA can als guarantee the real-time requirement f several cmplex algrithms. Table I lists the parameters f the prpsed bst PFC prttype. We nly utilize the upper eight-bit digital utput f the selected A/D cnverter LTC141. The MSB f the digital utput indicates the utput value sign. Thus, the utput range f LTC141 is.5 V t.5 V, and the gain f the selected A/D cnverters is K ad = 7 / Fig. 1 and Table I shw that the gain f the utput vltage divider netwrk that cnsists f R1 and R is K v = 0.05, and the utput vltage amplificatin cefficient is K av = 1. The equivalent cefficient Fig. 10. Pht f the experiment set-up fr the prpsed bst PFC. f the utput vltage sampling part is K ve = K ad K v K av = With the same principle (i.e., the sampling resistr R3 = 0.1 Ω, input current amplificatin cefficient K ai = 5, and gain f the sampling resistance is set at K il = 0.5), we btain the equivalent gain f input current sampling part K ile = K ad K il K ai = 5.5. Fig. 10 illustrates the experiment set-up f the prpsed bst PFC rectifier. An islating transfrmer with a transfrmer rati f 1:1 is used fr safety cnsideratin. V inrms = 50 V is btained by the vltage regulatr. We use the IT8514 DC electrnic lad t generate the system lad and lad step. The PF and THD are measured by a WT10 digital pwer meter. The equivalent emulated input admittance G ine [n] is the indicatr f lad cnditin fr the prpsed prttype in Fig. 11. G ine [n] can be used t assess the lad cnditin and judge the lad variatin. In this study, the value range f G ine [n] is apprximately 500 t 800 fr an ptimal bst PFC perfrmance. G ine [n] < 500 indicates that the PFC rectifier enters the MCM/DCM. Eq. (14) divides the CCM and MCM regins [4], whereas Eq. (15) divides the DCM and MCM regins. Fig. 11 shws that the PF significantly decreases because the entire cntrl system is based n the assumptin that the rectifier perates in the CCM mde. The system THD descends when G ine [n] < 500 because the harmnics current prprtin increases as shwn in Fig. 11(b). Fig. 11(c) shws the relatin between emulated input admittance G ine [n] and utput pwer P under different inductr values. IV. EXPERIMENTAL RESULTS Fig. 1 shws the PWM wavefrm (upper, ch1) and cnversin signal wavefrm (under, ch). The falling edge f the cnversin signal wavefrm triggers the input current sampling prcess instantaneusly. The input current is always sampled at a fixed instant n the switching frequency. Fig. 13 shws the input vltage wavefrm (upper, ch) and average input current wavefrm (under, ch1) after the prpsed PFC that perates in a 10 W lad. The average input current is

6 An FPGA-based Fully Digital Cntrller fr 649 Pwer Factr THD [%] Output pwer, W Output pwer, W (b) (b) 300uH inductr L 470uH indcutr L 870uH indcutr L 300uH inductr L 470uH indcutr L 870uH indcutr L ch1:i in ch1:0.a/div Fig. 14. Input current envelpe wavefrm in a 10 W lad. ch1:i in ch1:0.a/div 1000 Gine[n] uH inductr L 470uH indcutr L 870uH indcutr L Fig. 15. Input current envelpe wavefrm in a 40 W lad Output pwer, W (c) (c) Fig. 11. Prpsed digital cntrller perfrmance with input inductr. Pwer factr. (b) THD, and (c) G ine [n]. ch1:v in ch1: PWM signal CCM ch3:i in ch1:40.0v/div, ch3:0.a/div ch: cnversin signal ch1,ch:1.0v/div Fig. 1. DPWM and cnversin signal wavefrm. ch:0.0v/div ch1:0.5a/div ch1:0.4a/div, ch:0.0va/div Fig. 13. Input current and vltage wavefrm with PFC. Fig. 16. Input current wavefrm in a 10 W lad. perfectly synchrnized with the input vltage. Fig. 14 shws the input current envelpe captured by the hall current sensr at a 10 W lad. Fig. 15 is the input current wavefrm at a 40 W lad. As previusly analyzed, the PFC rectifier enters the MCM/DCM mde. Fig. 16 shws the wavefrm f the input current captured at sampling resistance R3 (under, ch3) and input vltage wavefrm (upper, ch1) at a 10 W lad. The system always perates in CCM under this lad level. Fig. 17 shw the wavefrm f the input current captured at sampling resistance R3 (under, ch3) and input vltage wavefrm (upper, ch1) at a 40 W lad. The system perates in CCM when the input vltage is near the peak value f the rectified cycle, whereas it perates in DCM when the input vltage is near the minimum value. This scenari indicates that the system enters the MCM under this lad level, which results in a high harmnics level and lw PF value (Fig. 11).

7 650 Jurnal f Pwer Electrnics, Vl. 15, N. 3, May 015 DCM CCM Fig. 17. Input current wavefrm in a 40 W lad. V =9.5V t r =1360ms ch1:v in ch3:i in ch1:40.0v/div, ch3:0.a/div ch3:v ch4:i ch3:10.0v/div, ch4:0.64a/div, t:00ms/div Ntably, the system takes a lnger regulatin time t return t stability when the lad step is frm 10 W t 64 W cmpared with reverse lad step prcess frm 64 W t 10 W. This scenari is the typical phenmenn fr single-ended bst tplgy because it has n energy release path in the lad drp step prcess. V. CONCLUSION This paper presents an FPGA-based fully digital cntrller fr bst PFC cnverters. The prpsed PFC cnverter realizes the DOCC cntrl apprach, which requires n input vltage sensing, tw-lp cmpensatin part design, r cmplicated average current sampling and calculatin prcess. It btains a high pwer factr and the peratin f lw harmnic input current ingredients ver a large lad range under CCM. Implementatin f the prpsed PFC system and structure f the FPFA-based cntrller are discussed in detail. Experimental results demnstrate that the prpsed PFC rectifier can btain a PF value f up t 0.999, and the minimum THD decreases t 1.9% by a 10 W prttype that perates in 50 V input line vltage. The feasibility and suitable dynamics respnse under variable lad cnditins f the prpsed prttype are satisfactry. Fig. 18. Output vltage regulatin frm 10 W t 64 W lad step. t r =85ms V u =68.V ch3:v ch4:i ch3:10.0v/div, ch4:0.64a/div, t:100ms/div Fig. 19. Output vltage regulatin frm 64 W t 10 W lad step. We exhibit the utput vltage v wavefrms t verify the validity f the vltage lp. Fig. 18 shws the utput vltage regulatin prcess frm 10 W t 64 W lad step. The said figure shws that the maximum versht utput vltage is V = 9.5 V, and the system takes apprximately 1360 ms t regulate the vltage t steady state (80 V). Fig. 19 shws the utput vltage regulatin prcess frm the 64 W t 10 W lad step, which is the reverse prcess f the lad step in Fig. 4. The utput vltage elapses by 85 ms befre it recvers t 80 V, and the minimum undersht utput vltage is V u = 68. V. REFERENCES [1] Electrmagnetic Cmpatibility Part 3: Limits Sectin : Limits fr Harmnic Currents Emissins (equipment input current_16 A per phase), IEC , [] IEEE Recmmended Practices and Requirements fr Harmnic Cntrl in Electrical Pwer Systems, IEEE Std , 199. [3] F. Q. Wang, H. Zhang, and X. K. Ma, Intermediate-scale instability in tw-stage pwer-factr crrectin cnverters, IET Pwer Electrn., Vl. 3, N. 3, pp , May 010. [4] L. Dixn, High pwer factr switching preregulatr design ptimizatin, in Prc. Unitrde Pwer Supply Design Sem., pp , [5] M. Rdriguez, M. V. M. Lpez, F. J. Azcnd, J. Sebastian, and D. Maksimvic, Average inductr current sensr fr digitally cntrlled switched-mde pwer supplies, IEEE Trans. Pwer Electrn., Vl. 7, N. 8, pp , Aug. 01. [6] D. Maksimvíc, Y. Jang, and R. W. Ericksn, Nnlinear-carrier cntrl fr high-pwer-factr bst rectifiers, IEEE Trans. Pwer Electrn., Vl. 11, N. 4, pp , Jul [7] IR1150 DATASHEET NO.PD6030, Internatinal Rectifi er. [8] ICE1PCS01 DATASHEET V1. 18 Feb 005, Infinen Technlgies AG. [9] J. P. Gegner and C. Q. Lee, Linear peak current mde cntrl: A simple active pwer factr crrectin cntrl technique fr cntinuus cnductin mde, in Prc. IEEE Pwer Electrn. Spec. Cnf., Vl. 1, pp , 1996.

8 An FPGA-based Fully Digital Cntrller fr 651 [10] S. Ben-Yaakv and I. Zeltser, PWM cnverters with resistive input, IEEE Trans. Ind. Electrn., Vl. 45, N. 3, pp , Jun [11] Z. Lai and K. A. Smedley, A family f cntinuuscnductin-mde pwer-factr-crrectin cntrllers based n the general pulse-width-mdulatr, IEEE Trans. Pwer Electrn., Vl. 13, N. 3, pp , May [1] J. Rajagpalan, F. C. Lee, and P. Nra, A general technique fr derivatin f average current mde cntrl laws fr single-phase pwer-factr-crrectin circuits withut input vltage sensing, IEEE Trans. Pwer Electrn., Vl. 14, N. 4, pp , Jul [13] J. Zhu, Z. Lu, Z. Lin, Y. Ren, Z. Qian, and Y. Wang, Nvel sampling algrithm fr DSP cntrlled kw PFC cnverter, IEEE Trans. Pwer Electrn., Vl. 16, N., pp. 17-, Mar [14] D. M. Van de Sype, K. De Gusseme, A. P. Van den Bssche, and J. A. A. Melkebeek, A sampling algrithm fr digitally cntrlled bst PFC cnverters, IEEE Trans. Pwer Electrn., Vl. 19, N. 3, pp , May 004. [15] A. Olayiwla, B. Sck, M. R. Zlghadri, A. Hmaifar, M. Walters, and C. Dss, Digital cntrller fr a bst PFC cnverter in cntinuus cnductin mde, Prc. IEEE Cnf. n Industrial Electrnics and Applicatins, pp. 1-8, 006. [16] S. Bus, P. Mattavelli, L. Rssett, and G. Spiazzi, Simple digital cntrl imprving dynamic perfrmance f pwer factr preregulatrs, IEEE Trans. Pwer Electrn., Vl. 13, N. 5, pp , Sep [17] D. M. Van de Sype, K. De Gusseme, A. P. Van den Bssche, and J. A. A. Melkebeek, Duty-rati feedfrward fr digitally cntrlled bst PFC cnverters, IEEE Trans. Ind. Electrn., Vl. 5, N. 1, pp , Feb [18] S. Bibian and H. Jin, Digital cntrl with imprved perfrmance fr bst pwer factr crrectin circuits, Prc. IEEE Applied Pwer Electrnics Cnf. and Expsitin, pp , 001. [19] W. Zhang, Y. F. Liu, and B. Wu, A new duty cycle cntrl strategy fr pwer factr crrectin and FPGA implementatin, IEEE Trans. Pwer Electrn., Vl. 1, N. 6, pp , Nv [0] A. Garcia, A. de Castr, O. Garcia, and F. Azcnd, Pre-calculated duty cycle cntrl implemented in FPGA fr pwer factr crrectin, in Prc. IEEE 35th Annu. Ind. Electrn. Cnf., pp , 009. [1] S. Mn, L. Crradini, and D. Maksimvic, Auttuning f digitally cntrlled bst pwer factr crrectin rectifiers, IEEE Trans. Pwer Electrn., Vl. 6, N. 10, pp , Oct [] A. de Castr, P. Zumel, O. Garcia, T. Riesg, and J. Uceda, Cncurrent and simple digital cntrller f an AC/DC cnverter with a pwer factr crrectin based n an FPGA, IEEE Trans. Pwer Electrn., Vl. 18, N. 1, pp , Jan [3] C. W. Clark, F. Musavi, and W. Eberle, Digital DCM detectin and mixed cnductin mde cntrl fr bst PFC cnverters, IEEE Trans. Pwer Electrn., Vl. 9, N. 1, pp , Jan [4] R. W. Ericksn and D. Maksimvíc, Fundamentals f Pwer Electrnics, Nrwell, MA: Kluwer, 001. Li Lai was brn in Mianyang, China. He received his B.S. in Micrelectrnics Technlgy degree frm the University f Electrnic Science and Technlgy f China (UESTC), Chengdu, China, in 009. He is currently wrking tward a Ph.D. in Micrelectrnics at the UESTC. His current research interests include digital cntrl f pwer systems, PFC cnverters, and PWM cnverter/inverter systems. Ping Lu finished her B.S. in Autmatin Cntrl and M.S. in Industrial Autmatin degrees frm Chngqing University, Chngqing, China in 1990 and 1993, respectively. She finished her Ph.D. in Circuits and Systems frm the UESTC, Chengdu, China in 004. She cnducted research n electrical engineering and autmatin at the UESTC frm 1993 t 000. Since 001, she has been cnducting research n smart pwer ICs and pwer systems at the UESTC. At present, she is with the State Key Lab f Electrnic Thin Films and Integrated Device, and is a prfessr at the UESTC. Her current research interests include pwer management ICs and cntrl techniques fr high-efficiency pwer systems.