A Novel Matrix Converter Topology With Simple Commutation

Transcription

1 A Nvel Matrix Cnverter Tplgy With Simple Cmmutatin Abstract-Matrix cnverter is very simple in structure and has pwerful cntrllability. Hwever, cmmutatin prblem and cmplicated PWM methd keep it frm being utilized in industry. This paper disclses a nvel matrix tplgy with advantages ver the usual matrix cnverter tplgy. Firstly, it has the same perfrmance as a cnventinal matrix cnverter in terms f vltage transfer ratin capacity, fur quadrant peratin, unity input pwer factr, n DC capacitr and pure sine wavefrms with nly high rder harmnics in bth line and lad side. Secndly, the PWM methd utilized at cnventinal inverter can be used, which can largely simplify its cntrl cmplexity. Thirdly, all the switches at line side turn n and turn ff at zer current; the cnverter des nt have any cmmutatin prblems as required by the cnventinal matrix cnverter. Theretical analyses and simulatin results are prvided t verify its feasibility. I. INTRODUCTION The matrix cnverter, first intrduced in 1980 [1], has experienced revived attentin recently. The matrix cnverter tplgy is shwn in Fig. 1. Cmpared with the cnventinal AC/DC/AC cnverter, it has the fllwing merits: 1) N large energy strage cmpnents, such as large DC capacitrs r inductrs, are needed. As a result, a large capacity and cmpact cnverter system can be designed. ) Fur-quadrant peratin is straightfrward, by cntrlling the switching devices apprpriately, bth utput vltage and input current are sinusidal with nly harmnics arund r abve switching frequency []. Hwever, this tplgy des nt yet fund much applicatin in industry. The majr reasn is that it has ptential cmmutatin prblems requiring a cmplex cntrl circuit as well as, in general, a biplar snubber. In additin the cntrl algrithm, develped by Venturini [1], typically requires a PLA (prgrammable lgic array) fr efficient cmputatin. Cmmutatin prblems are mainly caused by the need t adhere t the safe peratin f fur quadrant switches. Several slutins have been published t slve this issue[5][6]. Hwever, they generally intrduce a multistepped switching prcedure r an additinal prtectin circuit, which largely increases the cmplexity f the matrix cnverter. Until nw, these slutins d nt appear t be sufficient t enable the matrix cnverter leave the research labs int the industrial area. Besides cmmutatin prblem, in rder t get sinusidal wavefrm at bth input and utput sides, bth the frward sequence and negative sequence cmpnent shuld be calculated and added tgether. It requires very cmplex cmputatinal burden and additinal PWM circuits. Other researchers have als fcused n eliminating the DC capacitrs in a traditinal AC/DC/AC cnverter [],[4]. Lixiang Wei, Thmas. A Lip Department f Electrical and Cmputer Engineering University f Wiscnsin-Madisn 1415 Engineering Drive Madisn, WI, 5706, USA 1 These circuits can effectively eliminate the DC side capacitr, but the line current cntains large amunt f lw rder harmnics. Special prblems arise in ensuring cmmutatin as a result f the altered circuit tplgy. In this paper, a matrix cnverter tplgy is develped which has nt yet been previusly reprted. The new cnverter has fllwing advantages: It has the same perfrmance as the cnventinal matrix cnverter, such as gd vltage transfer rati capacity, fur quadrant peratin, unity input pwer factr, pure sine wavefrms with nly high rder harmnics in bth input current and utput vltage. Pulse width mdulatin algrithms f cnventinal inverters can be utilized, which can greatly simplifies its cntrl circuit. All switches at the line side turn n and turn ff at zer current. Hence, this new cnverter des nt experience the cmmutatin prblems f a cnventinal matrix cnverter. N large energy strage cmpnents are needed except relatively small size ac filter making these filter mre easily t be integrated int a system package. In this paper, the basic peratin f this tplgy is first discussed. A suitable PWM algrithm is then develped. This algrithm maintains bth input line current and utput vltage wavefrms as sinusidal simultaneusly as well as guaranteeing zer current turn-n and turn-ff f the line side cnverter. Finally, bth system and circuit level simulatin results are prvided t verify its feasibility. System level simulatin study is cnducted using MATLAB/ SIMULINK t verify its sinusidal input and utput perfrmance. On the j = 1 Vin1 i = 1 S11 S1 S1 S1 S S Iin1 Iin Iin Vin Vin S1 S S Iut1 Iut Iut Fig. 1. Cnventinal matrix cnverter tplgy /01/$10.00 (C) 001

2 Fig. Basic tplgy f the prpsed matrix cnverter ther hand, the SABER simulatin language is emplyed fr a circuit level simulatin t demnstrate zer current turn n and turn ff characteristics, which ultimately leads t a simple snubber fr bth sides f the cnverter. The experimental results, nt present in this article, are in prgress and will be prvided in the near future. II. PROPOSED TOPOLOGY Fig. illustrates the mdified matrix cnverter tplgy presented in this paper. Althugh it is still termed a matrix cnverter and has the same pwer switches as cnventinal switch layut, it is als similar t the traditinal AC/DC/DC cnverter system and t previus prpsed capacitrless DC link circuits [],[4]. On the lad side, the arrangement has the same cnventinal inverter as fr the AC/DC/AC cnverter. As a cnsequence, traditinal PWM methds may be used t generate the utput vltage wavefrm. Hwever, in rder t ensure prper peratin f this cnverter, the DC side vltage shuld always be psitive. On the line side, the cnverter has a rectifier which is similar t traditinal ne except that the switches are all bidirectinal. This mdificatin als prvides the distinguishing feature which differs this cnverter frm circuits f previus researchers [],[4]. The main bjective f this rectifier is t maintain pure sinusidal input current wavefrms as well as maintain psitive vltage n the DC side. In cntrast t the AC/DC/AC cnverter, the DC capacitrs can nw be replaced by a small filter n the line side. Fr purpses f analysis, ne can assume that the switching frequency is far greater than fundamental frequencies f bth the input vltage surce and utput current surce. Thus during each switching cycle, bth the input vltage and utput current can be assumed as cnstant. Assuming a stiff vltage surce n the line side and stiff current sink n the utput side, the DC side vltage is essentially decided by the switching functins f the rectifier and the input vltage, the DC side current is determined by the cmbinatin f utput switching functins and utput current. It is assumed that, n the input side V sa = Vm cs θa = Vm cs( ωit) V = Vm cs θb = Vm cs( ωit ) (1) V sc = Vm cs θc = Vm cs( ωit + ) and n the lad side, iu = I csθ i = I cs( ω t+ϕ ) iv = Ics( ω t +ϕ ) iw = I cs( ω t+ϕ + ) In Eqs. (1) and () : ω i, ω are the input and utput angular frequencies ϕ : initial electric angle f the U phase utput current. V m, I : amplitudes f input vltage, utput current respectively. III. PROPOSED PWM METHOD A. PWM Methd fr the rectifier side In rder t simplify the analysis f the rectifier, it is suppsed that there is n input filter in the line side. Hence: L = 0 ; R = 0 ; C = 0 f V x = V sx, i sx = ix, x = a, b, c f The aim f the pulse width mdulatin f the rectifier is t maintain psitive vltage in the dc side as well as t maintain the input pwer factr as unity. () /01/$10.00 (C) 001

3 Since the input line vltages are balanced, there are tw pssible cnditins fr the input phase vltages. 1) Tw vltages are psitive, and ne is negative Suppsing that phases A and B are psitive, phase C is then negative. One can derive: V = V + V sc sa Under this cnditin, switch S cn must be maintained in the cnducting state while S ap, Sbp are mdulated. All ther switches keep in ff state. While S ap is turned n, the DC vltage is equal t V ac and is psitive. The duty rati f switch S ap is given by, cs θa d ac = cs θc While S bp is turned n, the DC vltage equals t V bc and is als psitive. The duty rati f Sbp is given by, csθ d b bc = cs θc () (4) Vm = csθc Utilizing the same apprach, ne can btain the crrespnding duty rati and switching state fr all ther circuit cnditins. The average value f DC vltage during each f these switching cycle is Vm = csθin where, cs( θ in ) = max( cs( θa ), cs( θb ), cs( θc ) ). Figure. shws the PWM sequence fr bth input and utput side cnverters. One can determine frm this figure that n the rectifier side, nly tw cmmutatin events ccur during each switching cycle. The duty cycle d 1, d and switching pattern while 5 < θa < are shwn in Table. I. While < θ < a, ne can establish the crrespnding values 6 6 and patterns with the same apprach. (9) The average DC side vltage in this switching cycle is = dac ( Vsa Vsc ) + dbc ( V Vsc ) (5) Substituting (1), (), and (4) in (5), ne can finally btain Vm = csθ c ) Tw vltages are negative, ne is psitive Suppsing that phases A and B are negative, phase C is then psitive. One can establish that V = V + V sc sa Under this cnditin, switch S cp remains in cnducting state, switches S an, Sbn are mdulated. All ther switches remain in ff state. During the time when S an is turned n, the DC vltage equals V ca and is psitive. The duty rati f S an can be expressed as, cs θa d ac = cs θc When S bn is turned n, the DC vltage equal V cb and is psitive. The duty rati f is csθ d b bc = cs θc Sbn Finally, the average value f the DC vltage during this switching interval is = d ac (Vsc Vsa ) + dbc (Vsc V ) (8) Substituting Eqs. (1), (6), and (7) in (8), ne btains (6) (7) B. PWM methd fr the inverter side Once the PWM sequences f the rectifier have been decided, ne can apply varius PWM methds fr the inverter, including space vectr PWM, SPWM, etc. Here, the space vectr PWM methd will be utilized fr the inverter side. Vm Initially, it is assumed that the DC vltage is, and the expected utput vltage is v Vm V _ ref = k θ ; 0 < k < (10) j j where: V v = V + V e + V e _ ref θ = ϕ Rectifier Side Switching Mde: su + ψ sv sw is the utput vltage angle ψ is the angle between utput vltage and current. Inverter Side Switching Mde: Inverter SVPWM Mde Average DC Bus Current Average DC Bus Vltage t start t t t cm d1 t s d ts t 1 t 0 / t 0 / + t 1 t 0 / + t1 + t " t 1 " t " t t s k I csψ csθin Vm ( csθin ) Fig.. PWM sequence fr the prpsed cnverter t end /01/$10.00 (C) 001

4 TABLE I DUTY CYCLE AND SWITCHING PATTERN OF THE RECTIFIER θ a 5 ~ ~ ~ Duty Cycle d 1 d d 1 d d 1 d Values d ba d ca d bc d ac d cb d ab Cnducting S ap S cn S bp Switches S bn S cn S bp S ap S cn S an 011 V v,t ki csθ = in [sin( θ )csθ sin θ cs( θ + )] i i sin = ki cs( θ θi )cs θin = ki cs ψ csθin (14) Mrever, frm (1), ne can establish that the duty cycle f vectrs V v 1, V v and V v 0 equal each ther ver bth intervals d 1, d. When θ >, using the same methd, ne can again btain the crrespnding time duratins fr the relevant vectrs. Mrever, it can be shwn that the average dc current ver each cycle always equals Eq. (14). 000 v Vm V = k θ V v 1, t Vm Fig. 4. Space vectr PWM fr inverter ver the instant while 0 < θ < Figure 4 shws the space vectr PWM fr inverter while 0 < θ <. The time duratin f V 1, V are k sin( θ) t k sin( θ 10 = ts ; ) t t 0 = s (11) sin sin In actual system, the average DC vltage is V m cs θ in s that the time duratins f V 1, V and V0 fr this case are; t1 = t10 csθin ; t = t0 csθin ; t0 = ts t1 t (1) The time sequence f the inverter side switching is shwn in Fig.. The varius time intervals in the figure can be derived as: t1 = tcm d1t0 ; t = t1 d1t1 ; t = t + d1t t1 = tcm + dt0 ; t = t1 + dt1 ; t = t + dt tcm = tstart + d1t s ; t end = tstart + ts (1) Since i dc equals alternately i u, i w and 0 fr vectrs V v 1, V v and V v 0 respectively, ne btains the average dc current fr this switching perid as: t1iu tiw idc _ avg = ts, 4 C. Wavefrms f bth input current and utput vltage Suppsing 0 < θ <, < θa <, frm Fig. and 6 6 Table 1, it can be seen that during the d 1 perid in which S ap, S bn are cnducting, ne btains i sa1 = i1 = idc, and i sc1 = 0 ; During the perid d, switches S ap and Scn are cnducting in which case i sa = isc = idc, and i = 0. Over this switching cycle è in = èa. The average input currents during this switching cycle are i i i sa = i = k I csψ csθ dc _ avg dc _ avg = d i = k I csψ csθ 1 = d i = k I csψ csθ dc _ avg c (15) The utput vltage vectr is: v V = d1v csθ k θ + dv csθ sab a sac a b a k θ Substituting Eq. (5) int (16), ne can finally determine that the actual utput vltage vectr is v V m V = k θ (16) (17) D. Cmmutatin Prblem Frm Fig., while the rectifier side is cmmutating, the inverter side vectr is V v 0. This result indicates that during cmmutatin the DC side current is zer. Hence, at this instant, all currents ne the rectifier side are zer s that zer current turn-n and turn-ff n the rectifier side can be guaranteed. This feature largely simplifies the cmmutating prblems always assciated with cnventinal matrix cnverters. In additin, switching lsses f the input side devices are significantly reduced. E. Discussin Frm abve analysis, with the prpsed PWM methd, the prpsed matrix cnverter tplgy has the fllwing characteristics: The input currents are pure sine waves with nly high rder switching harmnics, input pwer factr is maintained at unity and the maximum magnitude f the /01/$10.00 (C) 001

5 input phase current is k I csψ. The utput vltage remains a pure sine wave with nly high rder harmnics. The magnitude f utput vltage V m vectr is k, the maximum value f k is r the same as the highest transfer rati f the cnventinal matrix cnverter. All switches n the rectifier side turn n and turn ff at instants f zer current s that the cmmutatin prblems f the traditinal matrix cnverter are cmpletely avided. IV. SIMULATION RESULTS The prpsed tplgy has been extensively investigated under bth system and circuit level simulatins. The system level simulatin is made utilizing MATLAB/SIMULINK. This sftware represents all the switches as ideal switches. The PWM signal, input current and utput vltage wavefrms are btained t test the feasibility f prpsed cntrl methd. The parameters f the cnverter fr the MATLAB simulatin are: Input Line vltage: 480V; Input frequency: 60Hz Filter inductr: 00µH; Resistr: 0.Ω Filter capacitr: 0µF; Output resistr: 10Ω Output inductance: 5mH; Mdulatin level k: 0.80 Output frequency: 5Hz Fig. 5 shws MATLAB simulatin results fr the prpsed matrix cnverter. In Fig. 5(a), the PWM signal, input cnverter phase current and utput line vltage are shwn. In Fig. 5(b), the wavefrms listed are dc vltage, dc current, utput current, input line vltage and line current. Frm Fig. 5(a), it can be nted that the phase currents f the rectifier are mdulated during each cycle. Their values are cmprised f the three phase utput currents. On the ther hand, the utput vltages are als mdulated, and are cmpsed f prtins f the three phase input vltages. Frm Fig. 5(b), ne can nte the dc vltage and dc current traces. These wavefrms are mdulated in each switching cycle and are cmprised f input vltage and utput current respectively. Mrever, ne can establish that the DC vltage fluctuates between the magnitude f the line vltage and ne half f this value. Frm Fig. 5(b), it can be nted that the wavefrms f three phase utput currents are essentially sinusidal. This result, in turn, demnstrates that there are n lw rder harmnics in the utput vltage. Fig. 5(b) als shws the wavefrms f input phase vltage and phase current. Frm this figure, it can be bserved that the input phase current is als sinusidal. It can be fund in this figure that, the phase angle f current is leading the vltage. This result is caused by chice f the parameters f input filter. Simulatin studies using the SABER sftware were als made t investigate mre detail with the switch zer-current turn-n and turn-ff capability n the rectifier side. The circuit simulatin uses dide mdels with a reverse recvery (a) (b) Fig. 5. Simulatin result fr the prpsed matrix cnverter functin. The IGBT mdel used is IRGB40U. It was assumed that during simulatin, n the rectifier side, S ap keeps cnducting, and S bn and S cn are mdulated. On the inverter side, it is assumed that S vp and S wp turn n, and S up is mdulated. The current I a at this instant is 0A. Fig. 6 shws the simulatin result under SABER. The wavefrms shwn frm tp t bttm are V dc, V su, I dc, PWM inverter and PWM rectifier gate vltages respectively. Frm this result, it can be fund that the DC current is very small (0.06A - 0.1A) while the rectifier side is cmmutating. Thus in rder t avid vltage peaks while the rectifier is cmmutating, a small value f snubber capacitrs can parallel with the rectifier side switches t eliminate the cmmutatin vltage spikes /01/$10.00 (C) 001

6 Fig. 6. Circuit level simulatin using SABER cnversin technique eliminates reactive cmpnent", in Prc. POWERCON 7, 1980, pp. E-1-E-15. [] D.G. Hlmes and T.A. Lip, "Implementatin f a cntrlled rectifier using AC-AC matrix cnverter thery", IEEE Trans. n Pwer Electrnics, vl. 7, N. 1, 199, pp [] S. Kim, S-K. Sul and T.A. Lip "AC/AC pwer cnversin based n matrix cnverter tplgy with unidirectinal switches", IEEE Transactin n Industry Applicatins, vl.6, N. 1, 000, pp [4] J.-S. Kim, S-K. Sul, "New cntrl scheme fr AC-DC- AC cnverter withut DC-link electrlytic capacitr", in Prc. PESC 9, pp [5] J.-H. Yum, B.-H. Kwn, "Switching technique fr current-cntrlled ac-t-ac cnverters", IEEE Trans. n Industrial Electrnics, vl. 46, N., 1999, pp [6] K. Min, Y. Okuma, and K. Kurki, "Direct-linked-type frequency changer based n DC-clamped bilaterial switching circuit tplgy", IEEE Trans. n Industry Applicatins, vl. 4, N. 6, 1998, pp At present, a circuit realizatin f the new cnverter is being realized in hardware. It is expected that the experimental results will be btained in the near future. V. CONCLUSION This paper presents a new matrix cnverter tplgy. It cmbines the cntrl methd f the traditinal PWM methd fr AC/DC/AC system with the needs f a matrix cnverter and thus fulfills the functinal advantages f the matrix cnverter. Theretical analysis and simulatin results shw that the cnverter has fllwing perfrmance features: Bth the input current and utput vltage can be pure sine wavefrms with nly harmnics arund r abve switching frequency. The cnverter can prvide a unity input pwer factr. Fur quadrant peratin is pssible. N DC link capacitrs are needed, which means that a large capacity, cmpact cnverter system can be designed. Has the same vltage transfer rati capacity as cnventinal matrix cnverter. Cnventinal PWM methds can be applied fr cntrlling the utput side cnverter. This feature largely simplifies the cmplexity f cntrl. The cnverter is cmpletely free f the cmmutatin prblems assciated with cnventinal matrix cnverters. The cnverter ffers the pssibility f better efficiency than the cnventinal matrix cnverter since switching f the input side cnverter nly takes place during instant f zer dc link current. REFERENCES [1] M. Venturini, "A new sine wave in, sine wave ut, /01/$10.00 (C) 001