Simplified model and submodule capacitor voltage balancing of single-phase AC/AC modular multilevel converter for railway traction purpose

Transcription

1 IET Pwer Electrnics Research Article Simplified mdel and submdule capacitr vltage balancing f single-phase AC/AC mdular multilevel cnverter fr railway tractin purpse ISSN Received n 0th February 015 Revised n 16th Octber 015 Accepted n nd Octber 015 di: /iet-pel Wanxun Liu, Kai Zhang, Xiasen Chen, Jian Xing State Key Labratry f Advanced Electrmagnetic Engineering and Technlgy, Huazhng University f Science and Technlgy, Wuhan, HuBei, Peple s Republic f China kaizhang@hust.edu.cn Abstract: A single-phase AC/AC mdular multilevel cnverter MMC) can interact directly with 5 kv railway grid withut a bulky 50 Hz step-dwn transfrmer. This brings in great savings in size and cst. Submdule SM) vltage balancing f this kind f MMCs remains a majr technique issue. This study prpses a vltage-balancing slutin fr this scenari which cnsists f intra- and inter-arm vltage balancing methds. The frmer cmbines the advantages f carrier phase-shifted pulse-width mdulatin PWM) and phase dispsitin PWM based vltage-balancing methds. It nly uses tw prprtinal regulatrs, easing the cntrl system significantly. The latter is based n a pwer channel between the upper and lwer arms. It avids interferences with input/utput vltage and current, and gets rid f cmmn mde current cmpnent which wuld be injected int the grid with cnventinal inter-arm balancing methds. By assuming perfect vltage-balancing, a simplified mathematical mdel is als develped, which reveals mre clearly the pwer cnversin relatinship. Simulatins and experiments verify the prpsed vltage-balancing methds and the mathematical mdel. Nmenclature C N T c T U T1, U T U UCi, U LCi u U, u L, i U, i L u S, i S, f S u, i, f U S CU, U S CL U S U, U S L 1 Intrductin capacitance f each SM capacitr number f SMs in ne arm SM capacitr vltage carrier perid utput fundamental perid vltages acrss primary and secndary windings f transfrmer, respectively vltage f the ith SM capacitr in upper arm and lwer arms, respectively, i = 1,,, N vltage and current f upper and lwer arms, respectively grid vltage, current, and frequency utput vltage, current, and frequency sums f SM capacitr vltages f the upper and lwer arms averaged SM capacitr vltages f the upper and lwer arms Amng varius multilevel cnverter tplgies, the mdular multilevel cnverter MMC) [1] has becme the mst prmising ne due t advantages such as perfect mdularity with identical individual cells, distributed energy strage, simple vltage scaling, pssibility f a cmmn DC bus cnfiguratin, simple realisatin f redundancy, flexibility fr chsing a grid side cnverter, and s n. In the recent decade, a lt f research n the MMC has been dne, with the applicatin areas ranging frm high-vltage direct current HVDC), STATCOM, renewable energy utilisatin t medium vltage MV) drives [ 6]. Hwever, research wrk n applicatin f single-phase AC/AC MMCs fr railway tractin drives is relatively limited [7]. This paper cncentrates n railway tractin applicatin f the MMC, where the MMC is cnnected with the 5 kv/50 Hz railway grid withut a transfrmer. The MMC utputs a medium-frequency square-wave vltage, which can be prcessed by a much smaller, medium-frequency islatin transfrmer. The secndary winding f the islatin transfrmer can be cnnected t a traditinal tractin cnverter. The schematic f such a tractin drive is shwn in Fig. 1a. Each phase/leg f the MMC is cmpsed f many identical submdules SMs). It is imprtant t keep the SM capacitr vltages in balance within each phase, since prper peratin f the MMC is based n this assumptin. Hwever in practical peratins, an MMC is prne t SM vltage imbalance. Taking the pulse-width mdulatin PWM) strategies ften used with MMCs fr example, the phase dispsitin PWM PDPWM) causes vltage imbalance naturally due t its uneven distributin f switching frequencies). Fr the carrier phase-shifted PWM CPSPWM), vltage imbalance can als ccur due t differences in cmpnent parameters device lsses, capacitances, etc.) and cntrl actins amng different SMs. Withut prper balancing cntrl, the vltage imbalance amng the SMs can g beynd certain limit and cause a lt f prblems, such as uneven distributin f lsses amng the pwer devices switches, vervltage f sme SMs, distrted utput vltage wavefrm, r even instability f the MMC system. Therefre, vltage balancing has becme a majr research interest fr varius kinds f MMCs. Vltage-balancing task can be divided int tw subtasks: i) keep the SM vltages within each arm even; ii) keep the ttal SM vltages f the upper and lwer arms even. These are called intra-arm and inter-arm vltage balancing, respectively, in this paper. As t the intra-arm vltage balancing, there are mainly tw grups f methds fund in the literature: CPSPWM-based methds [8] and PDPWM-based methds [9 13]. There are als ther intra-arm vltage-balancing methds [14 16], but with relatively less applicatins. In CPSPWM-based methds [8], intra-arm vltage balancing is achieved with N N being the number f SMs within ne arm) IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy

2 Fig. 1 Schematic f a tractin drive a Tplgy f the single-phase AC AC MMC fr railway tractin drives b Auxiliary circuit fr prpsed inter-arm balancing same fr the ther leg) prprtinal regulatrs fed by the errrs between SM capacitr vltages and their references in ne leg. These regulatrs then minimise the errrs by changing the mdulating signals f the SMs. Hwever, with the increase f the number f SMs, the number f SM-level balancing regulatrs and PWM cmparatrs als increases, which raises the hardware and sftware cst significantly. Besides, changing the mdulating signals f the SMs may affect the input/utput pwer quality. PDPWM is used extensively in MMCs due t its easy implementatin. Hwever, an intrinsic feature f PDPWM is uneven distributin f switching frequencies amng the SMs within ne arm, which gives rise t an uneven distributin f switching lsses amng the SMs, and which causes severe vltage imbalance. T achieve the intra-arm balancing, methds based n vltage srting algrithm are usually emplyed [9 13]. In thse methds, capacitr vltages are measured and srted during each carrier perid. If the arm current is in charging directin, the SMs with highest vltages are given the pririty t be turned ff, and the SMs with lwest vltages are given the pririty t be turned n. The ppsite situatin happens when the arm current is in discharging directin. In this way, SM vltages in ne arm are balanced within a tight bund. Hwever, since the aim f thse methds is nt equalising the switching frequencies amng the SMs, the prblem f uneven switching frequencies assciated with PDPWM may still persist. Besides, altering the riginal distributin f gating signals in this way may intrduce extra switching actins that are slely fr the purpse f vltage balancing while ttally unnecessary fr utput vltage synthesising [1]. These extra switching actins increase switching lsses. On the ther hand, the vltage srting algrithm, which has t be executed every carrier perid, pses a heavy cmputatinal burden, thus resulting in increased demand fr hardware and sftware resurce. In [1], an imprvement is made such that nly SMs currently ff are selected when extra SMs need t be turned n, and the ppsite situatin happens if extra SMs are t be turned ff. This alleviates the extra switching prblem t sme extent. In [13], full srting algrithm is avided by taking care f the lwest and highest capacitr vltages nly. Methds that can effectively deal with all three drawbacks mentined abve i.e. uneven switching frequencies, extra switching actins, and cmputatinal burden) are yet t be fund. In this paper, a new intra-arm vltage-balancing methd based n CPSPWM is prpsed, which has the fllwing features: i) evenly distributed gating pulses fr all SMs; ii) n vltage srting algrithm; iii) nly tw balancing regulatrs fr each arm; iv) input/utput pwer quality will nt be affected; and v) n need t mnitr the directin f arm current. Fr inter-arm vltage balancing als called arm balancing), the existing slutins [8, 17, 18] can all be summarised as cmmn mde injectin methd. That is, a cmmn mde here the term cmmn mde means the signal is cmmn fr upper and lwer arms) cmpnent f the same frequency with the utput is injected int bth arms f ne phase leg s as t exchange active pwer. Hwever, fr grid-cnnected systems, such as shwn in Fig. 1a, the injected cmmn mde current will flw int the grid and affect the input pwer quality. In [19], pwer channels between upper and lwer arms are intrduced t vercme the lw-frequency vltage fluctuatin prblem assciated with MV drives. This cncept can als be used fr inter-arm vltage balancing. Hwever, it is impractical t use N pwer channels here. This paper prpses a new inter-arm vltage-balancing methd in which ne pwer channel is intrduced between the upper and lwer arms. The pwer channel is basically a bidirectinal DC/DC cnverter cnsisting f tw half-bridge mdules and a medium-frequency transfrmer. Active pwer is exchanged by means f phase-shifting cntrl f the bidirectinal DC/DC cnverter. In additin t the vltage-balancing methd, mdelling and cntrl f the MMC are als addressed in this paper. In [0], the authr established a mathematical mdel based n state-space equatins. In [1], an averaged mdel is established n the basis f individual SMs. As a result, the equivalent arm mdule is defined. Hwever, these mdels are a bit cmplicated when describing in a macrscpic way the pwer relatinship amng the input, the utput, and the SM capacitrs. In [], the mdel f the MMC is simplified with an equivalent bst buck circuit. Hwever, it des nt apply easily t the system shwn in Fig. 1a. In this paper, under the assumptin that the intra-arm and inter-arm vltage balancing are bth wrking well, an analgy f the main circuit shwn in Fig. 1a t a traditinal PWM rectifier fllwed by a PWM inverter is made. A much simplified and straightfrward mathematical mdel f the main circuit is then established. Based n this mdel, existing cntrl schemes fr single-phase cnverters can be readily used t cntrl the MMC shwn in Fig. 1a. The paper is rganised as fllws. A simplified mathematical mdel is established in Sectin. In Sectin 3, the prpsed intra-arm and inter-arm vltage-balancing methds are presented. The cmplete cntrl system fr ne phase leg f the MMC is given in Sectin 4. In Sectin 5, the prpsed methd is validated with simulatin and experimental results. Mathematical mdel In this sectin, under the assumptin f perfect capacitr vltage balancing, a simplified mdel f the MMC is established. The verall cntrl system f the MMC cnsists f tw layers: uter IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy 016

3 input/utput) cntrl and inner vltage balancing) cntrl. The frmer can be easily designed based n the established mdel. Equivalent circuit f ne phase leg f the MMC is shwn in Fig. a. Accrding t Kirchhff s vltage law u s = L di U dt + M di L dt + i UR + u U + u 1) and 4) yields L + M) di s dt + Ri s = u s u U + u L ) = u s u cm L M) di dt + Ri = u U u L ) u = u diff u 8a) 8b) u s = L di L dt + M di U dt + i L R + u L u ) u U and u L can be seen as btained by mdulating UCU S ttal SM capacitr vltage f the upper arm) and UCL S ttal SM capacitr vltage f the lwer arm), respectively Adding and subtracting ) frm 1) yield L + M) di U + i L ) + i dt U + i L )R = u s u U + u L ) 3) u U = u ru U S CU = u rs u r )U S CU u L = u rl U S CL = u rs + u r )U S CL 9a) 9b) Suppse L M) di U i L ) + i dt U i L )R = u U u L ) u 4) { u U + u L = u cm u U u L = u diff where u cm and u diff are the cmmn-mde and differential-mde cmpnents f the upper- and lwer-arm vltages. Slving 5) fr u U and u L gives { u U = u cm u diff 6) u L = u cm + u diff The current relatinship is as fllws: i U i L = i i U + i L = i s 5) 7a) 7b) where i s is usually called circulating current. Substituting 7) int 3) where u ru, u rl u rs, u r are the mdulating signals crrespnding t u U, u L, u cm, u diff, respectively. Due t the inner cntrl that will be discussed in next sectin U S CU = U S CU = U S C 10) where UC S is the ttal capacitr vltage f ne phase leg. By taking 9) and 10) int cnsideratin, 8) is changed int 11) L + M) di s dt + R i s = u s u rs U S C L M di dt + R i = u r S u 11a) 11b) Equatin 11a) is similar t the relatinship f a single-phase PWM rectifier, that is, if we lk u s as the surce vltage and u rs U S C as the AC-side vltage f rectifier. A similar analgy can be made between 11b) and relatinship f a single-phase PWM inverter, with u r U S C / being the AC-side vltage f the inverter and u the lad vltage. These tw cnverters exchange pwer via ttal leg capacitr C leg = C/N. Fig. Equivalent circuit f ne phase leg f the MMC a Equivalent circuit b Simplified circuit mdel c Further simplified VVVF transfrmer mdel f ne leg f the MMC IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy

4 Accrding t the wrking principle f the MMC, dynamic equatins fr arm capacitr vltages U S CU and U S CL are C ducu S = u N dt ru i U 1a) C ducl S = u N dt rl i L 1b) With 10) and 1), dynamic equatin fr leg capacitr vltage U S C can be derived as C du S ) C i = u N dt rs i s + u r 13) On the basis f 10) and 11), an equivalent circuit f Fig. a can be derived as shwn in Fig. b. In Fig. b, the u s lp is analgus t a PWM rectifier, the u lp is analgus t a PWM inverter, and the leg capacitr lp is analgus t the cmmn DC link that links the tw cnverters. Fig. b clearly demnstrates the pwer flw relatinship amng the input, the utput, and the SM capacitrs. Just like a cnventinal back-t-back PWM cnverter system, the pwer flw can als be reversed. Frm the input/utput pint f view, Fig. b can be further simplified int Fig. c, which can be seen as a variable-vltage variable-frequency VVVF) transfrmer, with the rectifier part n the primary side and the inverter part n the secndary side. 3 Capacitr vltage-balancing cntrl inner cntrl) The simple and straightfrward MMC mdel presented in the previus sectin depends n prper functining f the balancing cntrl f the SM capacitrs vltages, the aim f which is t make the ttal leg capacitr vltage UC S evenly distributed amng all SM capacitrs f that phase leg. This is als called inner cntrl in this paper, as cmpared with the uter cntrl which deals with the cntrl f input current, utput vltage as well as ttal leg capacitr vltage f the MMC, and which will be discussed in next sectin. As described in Sectin 1, SM capacitr vltage-balancing cntrl i.e. inner cntrl) can be further divided int intra-arm vltage balancing and inter-arm vltage balancing. 3.1 Intra-arm vltage balancing Take the lwer arm fr instance. The pwer f the SMs is expressed as p SM = u rs + u r + u x ) i s i ) 14) where u x is an added mdulating cmpnent fr vltage balancing. Equatin 14) can be rewritten as p SM = u rs + u r ) i s i ) + U C u x i s i ) 15) The secnd term n the right side f 15) cntains average pwer if u x is f the same frequency as i s r i. This is the idea f mst intra-arm vltage-balancing methds. The prpsed intra-arm vltage-balancing methd will be used with CPSPWM, in which the gating pulses are evenly distributed amng all SMs, and which results in relatively small imbalance cmpared with PDPWM. Thus, it is unnecessary t regulate all SMs f ne arm. Here, nly the tw SMs with the highest and lwest vltages are cmpensated. The cmpensating signal, which cntains the directin f the utput current, is added t the mdulating signal f the SM with the highest vltage, and subtracted frm the SM with the lwest vltage, making the frmer discharged and the latter charged. The mdulating signals f the tw SMs after cmpensatin are expressed as u r high = u rs + u r + Dd u r lw = u rs + u r Dd 16a) 16b) where Δd = ΔD i / i is the cmpensating signal, the amplitude f which is DD = high lw )C I T 17) In which T is the utput current perid, _high and _lw are the highest and lwest SM vltages, I is the amplitude f utput current i. Derivatin f 17) is based n the idea that the vltage difference is t be cmpensated in ne utput fundamental perid, althugh the algrithm is implemented at carrier frequency. On the basis f 15) and 16), pwers f the tw SMs are derived in 18). Nte that pwer terms that d nt cntain average cmpnents are neglected fr simplicity p SM high = u rs i s u r i + Dd i p SM lw = u rs i s u r i Dd i 18a) 18a) The DC cmpnents f the first tw terms n the right sides f 18a) and 18b) crrespnd t input and utput pwer f the MMC, which nrmally cancel each ther. The DC cmpnents f the third terms n the right sides serve the purpse f vltage balancing. As a result, vltage f the SM with highest vltage will decrease whereas the SM with lwest vltage will increase. By ding s, all capacitrs vltages within ne arm can be regulated within a tight bund. It is imprtant t nte that the arm vltage wuld nt be affected because the cmpensating signals fr the tw SMs are always cmplementary. Als nte that the speed f vltage balancing wuld nt be affected by the utput current since the latter has been taken int accunt, as shwn in 18). The schematic diagram f the prpsed intra-arm balancing methd is shwn in Fig. 3a. 3. Inter-arm vltage balancing It is necessary t briefly intrduce the cnventinal inter-arm balancing methd. Subtract 1b) frm 1a), and cnsider u ru = u s / u cm u diff ) UCU S u rl = u s / u cm + u diff ) UCL S 19) Dynamic equatin f the difference vltage between the upper and lwer arms can be derived C du S D = C N dt N du S CU U S CL ) dt = u s u cm i UC S u diff i UC S s 0) In 0), if u cm cntains utput vltage cmpnent, r i s cntains utput current cmpnent, bth will prduce average pwer t change the vltage-difference between upper and lwer arm, which can be used fr inter-arm balancing as the cnventinal methd did. The prblem is the apprach will intrduce utput frequency cmpnent int the grid see 3)). In this paper, inter-arm balancing is carried ut with an auxiliary circuit cnnecting ne upper arm and ne lwer arm within each IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy 016

5 Fig. 3 Schematic diagram f the prpsed intra-arm balancing methd a Schematic diagram fr the prpsed intra-arm vltage-balancing methd taking upper arm fr example) b Pwer flw with bth intra-arm and inter-arm balancing methds when U S U, U S L phase leg. The circuit, which is actually an islated, bidirectinal DC DC cnverter, has already been shwn in Fig. 1b. The prpsed methd has fllwing features. i) Inter-arm balancing is nw cmpletely decupled with arm vltage and current. Therefre, the input pwer quality will nt be affected. ii) Only ne such circuit is needed fr a phase leg with N SMs. iii) Capable f zer vltage switching, the circuit features lw switching lss. iv) The current stresses f the pwer devices in the auxiliary circuit are quite lw, because the circuit nly needs t transfer enugh energy t eliminate the imbalance f the arm-capacitr vltages. v) By prperly selecting the tw SMs t be cnnected by the auxiliary circuit, insulatin stress f the high-frequency transfrmer can be greatly reduced. The pwer exchanged with the bidirectinal DC DC cnverter can be easily cntrlled by varying the phase-shift angle between the primary and secndary vltages, which are high-frequency square waves t reduce the size f the islating transfrmer. The relatinship between transmitted pwer and the phase-shift angle is as fllws [3, 4] P = U T1 U T w 1 w ) vl p 1) In 1), U T1, U T are square-wave vltages amplitude f the transfrmer, ω is the frequency f the vltages, and j is the phase-shift angle. The phase-shift angle is calculated accrding t the difference between the ttal capacitr vltages f the upper and lwer arms, which is restricted in a range f π/ t π/ t avid multiple slutins. The relatinship between inter-arm pwer P) and average SM capacitr vltages f the tw arms U S U, U S L ) are based n the assumptin that the energy transferred frm ne arm t the ther are shared evenly amng N SM capacitrs f each arm by means f the intra-arm balancing cntrl. Crdinatin f these tw balancing actins will be discussed in mre detail in the next subsectin. 3.3 Crdinatin between inter-arm balancing and intra-arm balancing Since nly ne DC DC cnverter is used fr each phase leg, the sent/received energy f the tw cnnected SMs shuld be distributed t ther N 1 SMs within the same arm in a timely fashin by means f the intra-arm balancing methd mentined earlier in Sectin 3.1), therwise severe intra-arm imbalance will arise. This basically requires that the pwer transmitted via the DC DC cnverter fr inter-arm balancing purpse) shuld nt exceed the maximum pwer dented as P m ) that can be exchanged between SMs with the highest and lwest capacitr vltages within each arm. P m is clsely related t the mdulatin index m. Under rated cnditin, m is usually set arund 0.9. A larger m leaves smaller rm fr mdificatin f the mdulating signal, thus smaller P m. Fr the prpsed intra-arm vltage-balancing methd, P m can be calculated as P m = C du C dt u C C du C U dt C 1 m) I ) The crrespnding maximum phase-shift angle fr the auxiliary DC DC cnverter is therefre w m = p p 4ap, a = P mvl U C 3) Fig. 3b depicts the capacitr vltage-balancing prcess f a whle phase leg taking int accunt the tw balancing methds, where U S U, U S L is assumed. As shwn in Fig. 3b, excessive capacitr energy f the lwer arm is transmitted frm SM 1 f that arm t SM N f the upper arm via the auxiliary DC DC cnverter. Meanwhile, the sent energy f SM 1 f the lwer arm is supplied frm SM SM N f the same arm, and the received energy f SM N in the upper arm is distributed t SM 1 SM N 1 f the same arm, with the prpsed intra-arm balancing methd. 3.4 Insulatin issue f the transfrmer in the auxiliary circuit It is necessary t reduce the vltage between the tw windings f the islating transfrmer in the auxiliary DC DC cnverter. Otherwise, high insulatin stress may raise the cst and/r shrten the life f the transfrmer. If nly inter-arm pwer transfer is cncerned, the DC DC cnverter can be cnnected t any ne SM f each arm. Hwever, the insulatin vltage can be ttally different. Fr example, the whle grid vltage 5 kv in practice) will be impsed between the primary and secndary windings f the transfrmer when the auxiliary circuit is cnnected t SM 1 f the upper arm and IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy

6 Table 1 N U N L Fur cmbinatins f N U and N L #1 # #3 #4 ceiling u s / u ) ceiling u s / u ) ceiling u s / u ) ceiling u s / u ) ceiling u s / + u ) ceiling u s / + u ) ceiling u s / + u ) ceiling u s / + u ) SM N f the lwer arm. A quick investigatin f the MMC tplgy reveals that t reduce the vltage withstd by the transfrmer as much as pssible, the auxiliary DC DC cnverter has t be cnnected t the bttm SM SM N ) in the upper arm and the tp SM SM 1 ) in lwer arm, as already shwn in Fig. 1b. The fllwing derivatin will prve that the maximum vltage impsed between the windings f the transfrmer is n higher than 4 with such a cnnectin. Fr mst f the PWM strategies PDPWM, CPSPWM, etc.), the numbers f inserted SMs fr the upper and lwer arms at any time f peratin are cmbinatin in Table 1. The expressin f U AB in this situatin is {[ U AB = u s ceiling u s / u ) ] [ ceiling u ) ]} s/ + u U C [ = u s ceiling u s / u ) + ceiling u s / + u )] + 4U C 5) N U = ceiling u s / u ), r ceiling u s / u ) 4a) Since the first tw terms n the right side f 5) always amunt t a negative value, we have U AB, 4 6) N L = ceiling u ) s/ + u, r ceiling u ) s/ + u 4b) Therefre, there are fur cmbinatins f pssible values f N U and N L, as listed in Table 1. Vltage between pint A and pint B will be investigated next, since this is the maximum pssible vltage that will be withstd by the transfrmer i.e. when S a f the upper half-bridge and S b f the lwer half-bridge are bth turned n). First f all, it is easy t realise that the wrst case scenari i.e. U AB being the highest) happens when bth SMs cnnected by the auxiliary circuit are inserted as shwn in Fig. 4a), while the best case scenari happens when these tw SMs are bypassed as shwn in Fig. 4b). On the ther hand, U AB always gets higher when there are fewer inserted SMs amng the N 1 SMs that are nt cnnected by the auxiliary circuit. With the abve tw bservatins, it becmes clear that the highest U AB happens when the case f Fig. 4a is cincident with This effectively demnstrates that the vltage between the tw windings f the transfrmer will always be <4. It shuld be nted that u U, u L > 0 has been assumed fr the abve discussin. Fr ther cases, the same results as 6) can als be derived. 4 Overall cntrl system f the MMC Shwn in Fig. 5 is the verall cntrl system f the MMC, which is used during the simulatins and experiments, and which reveals mainly the uter cntrl that deals with the cntrl f input current, utput vltage, and ttal leg capacitr vltage f the MMC. The inner cntrl discussed in the previus sectin is als dented in Fig. 5 t highlight its place in the verall cntrl system. Seen frm the grid side, the MMC is like a traditinal PWM rectifier. Therefre, a dual-lp capacitr vltage uter lp and grid current inner lp) cntrl structure cmmnly used with PWM rectifiers is emplyed here. The gal f the dual-lp cntrl structure is t maintain UC S at its reference level while keeping unity pwer factr at the grid side. If necessary, a similar dual-lp cntrl structure can als be used fr the utput side i.e. the inverter part) f the MMC. Fr simplicity, pen-lp cntrl is adpted fr the utput vltage. Since reference UC S is a cnstant, a prprtinal integral PI) cntrller is used in the vltage uter lp. The transfer functin f the PI cntrller is G PI = k up + k ui s 7) where k up and k ui are the prprtinal and integral gains f the PI cntrller, respectively. T make the ttal capacitr vltage U S C less susceptible t sudden changes f lad current I, feed-frward cmpnent I ff is added t the uter lp I ff = U I cs b) U S 8) Fig. 4 a Wrst case b Best case Scenaris fr U AB where β is pwer factr angle f the lad. The current inner lp frces the input current t fllw its reference i s. Since the latter is a sinusid in steady state, a quasi-prprtinal-resnant PR) cntrller [5] is emplyed, the IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy 016

7 Fig. 5 Overall cntrl blck diagram f the MMC system Table Key parameters fr simulatin transfer functin f which is Items Symbls Values grid vltage rms) U s 5 kv grid frequency f s 50 Hz rated pwer P MW utput vltage U 13 kv utput frequency f 1 khz SM capacitance C 000 µf a rated capacitr vltage 7000 V number f SMs per arm N 4 self-inductance f arm inductr L 7.3 mh mutual inductance f arm inductr M 6.8 mh lad resistance R lad 85 Ω carrier frequency f c khz a Tw 4000 µf nes in series fr the tw SMs cnnected by the auxiliary DC DC cnverter k G PR = k ip + ir v c s s + v c s + v 9) where ω is the resnant frequency equal t the grid frequency in this case). ω c is called cutff frequency [6], which enlarges the passband f the cntrller s as t make the system mre rbust against frequency mismatch in practical applicatins. The utput f the current cntrller, u L+M), is the intended vltage drp acrss inductr L+M) shwn in Fig. b. With feed-frwarded grid vltage u s, the reference vltage u cm f the equivalent rectifier, r intended sum f upper- and lwer-arm vltages, is btained. Fig. 5 als depicts the prcess in which mdulating signals u ru and u rl are derived frm u cm. The mdulating signals then g Fig. 6 Simulatin results f the prpsed intra-arm vltage-balancing methd a Upper-arm SM capacitr vltages and cmpensating cmpnent in the mdulating signal withut/with prpsed intra-arm balancing methd b Enlarged view f circled area in Fig. 6a Fig. 7 Perfrmance f the prpsed inter-arm balancing methd a SM capacitrs vltages f bth arms and vltages acrss the windings f auxiliary transfrmer withut/with prpsed inter-arm balancing methds b Enlarged views f the circled areas in Fig. 7a IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy

8 Table 3 Circuit parameters fr experiment Items Symbls Values grid vltage rms) U S 150 V grid frequency f S 50 Hz rated pwer P 300 W utput vltage U 100 V utput frequency f 1 khz SM capacitance C 500 µf a rated capacitr vltage 100 V number f SMs per arm N self-inductance f arm inductr L 1. mh mutual inductance f arm inductr M 1.0 mh lad resistr R lad 0 Ω carrier frequency f c 4 khz a Tw1000 µf nes in series fr the tw SMs cnnected by the auxiliary DC DC cnverter thrugh the prpsed intra-arm vltage-balancing cntrl t generate the gating signals fr the SMs. In the meantime, inter-arm vltage balancing is carried ut with prper cntrl f the bidirectinal DC DC cnverter. 5 Simulatin and experimental results 5.1 Simulatin results T verify the prpsed mathematical mdel, the vltage-balancing methds, and the verall cntrl system, a Matlab/Simulink mdel is built, with key parameters listed in Table. The 7000 V SM capacitr vltage is chsen t reduce the number f SMs, s as t reduce the cmplexity f the simulatin mdel. In practice this vltage shuld be much lwer t facilitate the use f cmmercially viable pwer devices. Fig. 6a shws the simulatin results f the prpsed intra-arm vltage-balancing methd. Initially, there are significant differences amng the fur SM capacitr vltages f the upper arm. After the intra-arm vltage-balancing cntrl is activated at 0.4 s, these vltages cnverge t the set value f 7000 V quickly and smthly. The mdificatin cmpnents fr the mdulatin signals f the fur SMs are als presented, with the enlarged view f the circled area shwn in Fig. 6b. As can be seen frm Fig. 6b, therearenlytw nn-zer cmpensatins at any time, which are cmplementary t each ther. This avids influence n the arm vltages. Fig. 7a demnstrates the perfrmance f the prpsed inter-arm balancing methd. It can be seen that after the balancing cntrl is activated at 0.5 s, the initial differences between the SM capacitr vltages f the upper and lwer arms U UC1 U UC4, U LC1 U LC4 ) quickly cnverge t a negligible level. It is als imprtant t nte that during this transient prcess, there are n nticeable differences between the capacitr vltages f the tw SMs that are cnnected by the auxiliary DC DC cnverter U UC4 and U LC1 ) and thse f the ther SMs, which is due t a successful crdinatin between the inter-arm balancing cntrl and the intra-arm balancing cntrl, as described in Sectin 3. Fig. 7a als shws the vltages acrss the primary and secndary windings f the transfrmer U T1, U T ) in the auxiliary DC DC cnverter, with the enlarged views f the circled areas separated shwn in Fig. 7b. Fig. 8 Experimental wavefrms with prpsed intra- and inter-arm vltage-balancing methds a SM capacitr vltages in ne leg withut and with the prpsed intra-arm balancing methd experimental result) b SM capacitr vltages in ne leg, and the gating signals fr upper IGBTs Sa1,Sa) f tw half-bridge mdules f auxiliary circuit withut and with the prpsed inter-arm balancing methd c Input vltage and current d Output vltage and current IET Pwer Electrn., 016, Vl. 9, Iss. 5, pp & The Institutin f Engineering and Technlgy 016

9 5. Experimental results A test set-up f the single-phase AC AC MMC is built, with the key parameters listed in Table 3. The medium-frequency transfrmer and the AC DC AC railway drive that fllw the MMC in Fig. 1a are replaced with a resistive lad in the experiments. The cntrl hardware emplys digital signal prcessrs DSPs) and fieldprgrammable gate arrays FPGAs), with mst f the cntrl calculatin implemented in the DSPs and generatin f PWM signals implemented in the FPGAs. Fig. 8a shws the experimental wavefrms f intra-arm vltage balancing fr the upper and lwer arms. Fig. 8b shws the experimental wavefrms f inter-arm vltage balancing, including the driving signals fr the upper insulatedgate biplar transistr IGBTs) Sa1, Sa) f the tw half-bridges f the auxiliary DC DC cnverter. Shwn in Fig. 8c and d are the input vltage/current and utput vltage/current. The input current is cntrlled accrding t unity pwer factr. The utput vltage is cntrl as a 1 khz square wave. There is nticeable switching ripple in the utput vltage since it is directly feeding the resistive lad withut any filtering. 6 Cnclusin Intra-arm and inter-arm balancing methds are prpsed fr a single-phase AC AC MMC fr railway drive applicatins. The prpsed intra-arm balancing methd is based n CPSPWM, which cmbines the advantages f bth CPSPWM- and PDPWM-based methds. The prpsed inter-arm balancing methd is based n an auxiliary circuit, which decuples balancing cntrl with arm vltages, therefre des nt affect the input/utput pwer quality. With the tw balancing strategies wrking tgether t guarantee an even distributin f SM capacitr vltages, a simplified mathematical mdel is als established fr the single-phase AC AC MMC, which reveals the pwer transfer relatinship mre clearly and serves as a basis fr selecting prper strategies fr uter-layer cntrl system f the MMC. Simulatin and experimental results verify the effectiveness f mathematical mdel and vltage-balancing methd. 7 Acknwledgments This wrk was supprted by the Natinal Natural Science Fundatin f China Prject N ) and the Pwer Electrnics Science and Educatin Develpment Prgram f Delta Envirnmental & Educatinal Fundatin Prject N. DREG014013). 8 Reference 1 Lesnicar, A., Marquardt, R.: An innvative mdular multilevel cnverter tplgy suitable fr a wide pwer range. 003 IEEE Pwer Tech Cnf. Prc., Blgna, 003, vl. 3, n. 6, pp. 3 6 Zha, X., Xing, L., Gng, J., et al.: Cascaded multilevel cnverter fr medium-vltage mtr drive capable f regenerating with part f cells, IET Pwer Electrn., 014, 7, 5), pp Rafferty, J., Xu, L., Mrrw, J.: Analysis f vltage surce cnverter-based high-vltage direct current under DC line-t-earth fault, IET Pwer Electrn., 015, 8, 3), pp Alexander, A., Thathan, M.: Mdeling and analysis f mdular multilevel cnverter fr slar phtvltaic applicatins t imprve pwer quality, IET Renew. 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