An Enhanced Bulk-Driven Folded-Cascode Amplifier in 0.18 µm CMOS Technology

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1 Circuits and Systems, 202, 3, Published Online April 202 ( An Enhanced Flded-Cascde Amplifier in 0.8 µm CMOS Technlgy Arash Ahmadpur,2, Pya Trkzadeh 2 Department f Electrnic Engineering, Islamic Azad University, Lahijan Branch, Lahijan, Iran 2 Department f Electrnic Engineering, Islamic Azad University, Science and Research Branch, Tehran, Iran ar.amp@liau.ac.ir, trkzadeh_lm@yah.cm Received March 4, 202; revised April 3, 202; accepted April 0, 202 ABSTRACT A new cnfiguratin f Flded-Cascde (BDFC) amplifier is presented in this paper. Due t this mdifying, significant imprvement in differential DC-Gain (mre than db) is achieved in cmpare t the cnventinal structure. Settling behavir f prpsed amplifier is als imprved and accuracy mre than 8 bit fr 500 mv vltage swing is btained. Simulatin results using HSPICE Envirnment are included which validate the theretical analysis. The amplifier is designed using standard 0.8 µm CMOS triple-well (level 49) prcess with supply vltage f.2 V. The crrect functinality f this cnfiguratin is verified frm 50 C t 00 C. Keywrds: Flded-Cascde (BDFC) Amplifier; DC-Gain; (BD); Flded-Cascde (FC); CMOS. Intrductin Design f high-perfrmance integrated circuits is becming increasingly challenging with the persistent trend tward reduced supply vltages, especially in analg part. This requires traditinal analg circuit slutins t be replaced by new appraches t get the best perfrmance and mre flexible mixed-mde structure strategies that are cmpatible with future standard CMOS technlgy trends. This cmbinatin f the analg and digital parts shuld be dne in an ptimal way and the ptimizatin prcess is applicatin dependent [-4]. The main bttleneck in analg circuits is the peratinal amplifier. Meanwhile, fully differential amplifiers have better perfrmance cmpared t the single ended amplifiers. The single-stage amplifiers are inherently less prne t instability; mst applicatins use the amplifier in a clsedlp feedback cnfiguratin which can result in instability. This pssible instability is likely t manifest under high frequency peratin. Hwever, single-stage amplifiers suffer f lwer vltage gain cmpare t the multistage amplifiers, especially in lw-vltage applicatins and future deep sub-micrn technlgies. Hwever multistage amplifiers intrduce mre lw frequency ples and available cmpensatin techniques limit the amplifier s speed; nevertheless, they cnsume much mre pwer. On the ther hand, achieving high gain/swing perfrmance is hardly pssible fr single-stage amplifiers [5]. Fully differential flded-cascde (FC) amplifier is being used in many lw-vltage and high bandwidth applicatins and des nt suffer frm mirrr ple limitatins. This structure is utilized in many cases and exhibits a superir perfrmance because f its special features like ptentially high gain, single parasitic ple, wide bandwidth, acceptable limitatin f the cmmn mde (CM) vltage range [5-8]. Besides, bulk-driven (BD) amplifiers r cmplex gain enhancement techniques are ther techniques that have been already intrduced t bst the vltage gain f amplifiers. Recently, a number f techniques fr increase in the gain f BD amplifiers have been reprted [9-]; but fr a sufficient gain, mst f them utilize multi-stage r gain-bsting structures. This paper presents the design f a mdified structure f single-stage BDFC amplifier that has significant perfrmance in cmparisn with the cnventinal BDFC amplifier. It is shwn that the prpsed amplifier has higher DC-Gain, withut degrading f the frequency and transient respnses, due t the actin f the new merge circuit tplgy. The prpsed structure is dne in 0.8 µm triple-well CMOS prcess fr switched-capacitr applicatins. The design prcedures f this paper are rganized as fllws. Sectin 2 analyses the small signal f cnventinal and prpsed BDFC amplifiers and intrduce the bias and cmmn-mde feedback (CMFB) structures. Sectin 3 presents the simulatin results. Finally the cnclusin is given in Sectin 4. Cpyright 202 SciRes.

2 88 A. AHMADPOUR ET AL. 2. Amplifier Circuits 2.. Cnventinal Flded-Cascde Amplifier A typical PMOS BDFC amplifier in differential mde capable f perating with lw supply vltage is depicted in Figure. Because f high perfrmance and wide applicatins, the detailed analysis f this structure has been explained in [5,6]. NMOS and PMOS transistrs ac currents are derived by: ids gmvgs gmbvbs gdsvds () i g v g mb v sb g ds v sd (2) sd m sg where g m, g mb, and g ds are gate transcnductance, bulk transcnductance, and utput cnductance, respectively. By using Equatins () and (2) and cnsidering Vi Vi and V V, the differential DC-Gain f crrespnding amplifier is calculated by: A g R g R R v mb ut mb 2 Rut rds5 gm5 gmb5 rds rds3 rds7 rds9rds7 gm7 gm7 g r r r g r r m5 ds5 ds ds3 m7 ds7 ds9 (3) (4) By applying gd apprximatins, the differential DC- Gain f this amplifier is calculated as: A g v mb g r r r g r r g r r r g r r m5 ds5 ds ds3 m7 ds7 ds9 m5 ds5 ds ds3 m7 ds7 ds9 (5) In a typical 0.8 µm CMOS prcess, a vltage gain abut f 39 db and unity gain bandwidth (UGBW) f apprximately 4.5 MHz with phase margin f 89.7 fr a capacitive lad f pf is achievable (bias current f branches is 40 µa). T increase the DC-Gain f cnventinal FC amplifier, a new technique is prpsed in Sectin B Prpsed Structure The T achieve high DC-Gain in amplifier, the bulk terminals f transistrs M 5 t M 8 is used in new cnfiguretin, which NMOS and PMOS devices are in ppsite phases. These transistrs are auxiliary transistrs which increases the utput resistance, s DC-Gain will bst. Figure 2 shws the prpsed amplifier withut bias and CMFB circuits. Using Kirchhff s Current Law at the nde V, the KCL Equatin becmes: i i i (6) sd ds5 ds3 therefre, using Equatins () and (2), result in: vd vd9 gmb vi r r r ds ds3 ds9 cnsidering ids5 isd 7 isd 9 and V V2, and als using Equatins () and (2), result in: r r r r g g v g r r v r v ds7 ds9 ds7 ds9 m7 mb7 D9 mb7 ds7 ds9 ds9 r r g g v r v ds9 ds5 m5 mb5 D ds5 D9 g r r v r v mb5 ds5 ds9 ds rds5 rds7gm7 gmb7 vd9 r r g g v ds ds m mb D m5 mb5 ds5 ds7 ds5 ds7 (7) (8) (9) (0) g g r r v r r v using (8) t (0), Equatins are btained as fllws: r r g r g g v ds7 ds9 mb7 ds5 m5 mb5 D r r g g v ds5 ds7 m7 mb7 D9 () Figure. Cnventinal flded-cascde amplifier. Cpyright 202 SciRes.

3 A. AHMADPOUR ET AL. 89 Figure 2. Prpsed flded-cascde amplifier. ds g r r g g g r v mb7 ds7 ds5 m5 mb5 mb5 9 D g r g r v mb5 ds5 mb7 ds7 r r g g g r v r g r g r v ds5 ds7 m7 mb7 mb5 ds9 D9 ds9 mb5 ds5 mb7 ds7 substituting () t (3) int (7) results in: v2 mb ut mb 2 (2) (3) A K g R K g R R (4) gm5 gmb5 7 R K r r r ut 2 ds ds3 ds5 where K and 2 rewriting (4), s A g v2 mb r r g g ds5 ds7 m7 m K g r r r 2 m5 ds5 ds ds3 K is g K g r K g. r mb5 ds5 2 mb7 ds7 g r mb5 ds9 g r mb5 ds9 g r r r mb7 ds7 m7 ds5 ds7 gmb5 rds5 gmb7 rds 7 mb7 ds7 m5 ds5 ds ds3 gmb7rds7 gm5rds5 rds rds3 g r r g r g r r r g r r m7 ds5 ds7 m7 ds5 ds7 (5) (6) (7) It is clear that with increasing the K and K 2, the utput resistance will be bsted. A significant enhancement in the ttal value f A v2 is btained cnesquently. Indeed K will be cntrlled by chsing apprpriate biases and sizes f M 5 t M 8, especially cntrlling the bulk terminals f V and V 2 f these transistrs. Hwever, gmb5r ds9 must be greater than, because excluding it might take K t zer and decrease the DC-Gain, s befre fabricatin, the prpsed amplifier must be simulated in the crners f fabricatin prcess and wide temperature ranges. In this design prcedure, K.33 and K are btained, respecttively. Bias circuit and CMFB blck which utilized in the cnventinal and prpsed structures is shwn in Figures 3 and 4, respectively. 3. Simulatin Results In this sectin, simulatin results f the prpsed amplifier are shwn and are cmpared with the cnventinal structure. Amplifiers have been designed in a typical 0.8 µm CMOS prcess with the same capacitr lad and pwer cnsumptin and then simulated by HSPICE envirnment using level 49 parameters. A clsed-lp cnfiguratin with pf capacitrs is used t study the linearity and step respnse f the amplifiers, which is shwn in Figure 5. With the mentined value f capacitrs, clsed-lp gain f the amplifiers is apprximately 0 db. HSPICE AC simulatin results f the prpsed and the cnventinal FC amplifiers are shwn in Figure 6. The UGBW and phase margin f bth structures are apprximately equal. As demnstrated in Figure 6, the prpsed amplifier achieves a DC-Gain abut 50 db which is db higher than DC-Gain f the cnventinal amplifier in the same pwer supply and prcess. It is cnsiderable that by chsing a greater amunt f bth K and K 2 in Equatin (6) higher DC-Gain can be achieved. Ttal Harmnic Distrtin (THD) f bth amplifiers fr input CM vltage up t.2 Vp-p was tested. Fr 50 KHz and.2 Vp-p input frequency, THD f cnventinal and prpsed structures were db and 42.2 db, respectively. Figure 7 shws THD cmparisn f prpsed and cnventinal amplifiers in different CM vltage swing. As demnstrated f these tests, the cnventinal FC amplifier achieves higher linearity in lwer Cpyright 202 SciRes.

4 90 A. AHMADPOUR ET AL. Figure 6. Open-lp frequency respnse f amplifiers. Figure 3. Bias circuit fr bth amplifiers. Figure 7. THD cmparisn f amplifiers in different vltage swing. Figure 4. CMFB circuit fr bth amplifiers. Figure 8. Step respnse f amplifiers fr Vp-p = 500 mv. Figure 5. Clsed-lp cnfiguratin. utput vltage amplitudes. Hwever, in higher utput vltage amplitudes, bth amplifiers have acceptable linearity and eliminate undesirable harmnics. The accuracy f the amplifiers fr different input step vltage amplitudes in unity gain cnfiguratin was als tested. The result f the step respnse simulatin fr 500 mv amplitude is illustrated in Figure 8, which demnstrate that the accuracy f the prpsed amplifier is mre than 8 bit fr up t 500 mv utput vltage swing. Figure 9 illustrates the effective input transcnductance f amplifiers as a functin f the input CM vltage. It is bvius that bth designs functin crrectly fr rail-trail input CM vltage values with acceptable variatins. Finally, the simulated perfrmance f bth amplifiers and its cmparisn with previus structures are summarized in Table. In rder t cmpare the relative perfrmance f structures, a new figure f merit (FOM) is used as fllws: UGBW C A L V Vinp- p FOM 20 lg (8) Pdiss THD Cpyright 202 SciRes.

5 A. AHMADPOUR ET AL. 9 Table. Cmparisns f characteristics f prpsed amplifier with cnventinal and previus amplifiers. Parameters Cnventinal-BDFC Prpsed-BDFC [7] [8] [9] [0] [] Technlgy 0.8 µm 0.8 µm 0.5 µm 0.8 µm 0.8 µm 0.8 µm 0.8 µm Cnfiguratin/ Number f St. Gate-Driven Gate-Driven Gain-Bsting Tw-Stage Gate-Driven V DD (V) DC-Gain (db) UGBW (MHz) Phase-Margin( ) THD (db) (@200 mv) 42.2 (@200 mv) 58 (@26 mv) NA NA 57.7 (@500 mv) NA Pwer (µw) FOM (db) NA NA NA Figure 9. Effective bulk-transcnductance f amplifiers frm rail-t-rail. The unit f prpsed FOM is MHzpF mv mw, which this frm the benchmark fr the cmparisn with the results frm this wrk. 4. Cnclusins In this paper, a nvel apprach t increase the DC-Gain f cnventinal BDFC amplifier is presented. With the presented methd the DC-Gain f prpsed amplifier increased mre than db. All transistrs in bth amplifiers have same size and bth designs cnsume 375 µw with pf capacitive lad. Accuracy in the clsed-lp cnfiguratin f amplifier in higher utput vltage swings is the main advantage f the prpsed structure. Step respnse simulatins demnstrate that the accuracy f the prpsed amplifier is mre than 8 bit fr up t 500 mv utput vltages swing. Mrever, THD simulatins shw that prpsed amplifier achieves reasnable linearity in cmparisn with cnventinal structure in different vltage swings, especially in large input signal swing. REFERENCES [] S. Chatterjee, Y. Tsvidis and P. Kinget, Ultra-Lw Vltage Analg Integrated Circuits, IEICE Transactins n Electrnics, Vl. E89-C, N. 6, 2006, pp [2] S. Yan and E. Sanchez-Sinenci, Lw-Vltage Analg Circuit Design Techniques: A Tutrial, IEICE Transactins, Vl. E00-A, N. 2, 2000, pp [3] J. Ramirez-Angul, R. G Carvajal and A. Trralba, Lw Supply Vltage High Perfrmance CMOS Current Mirrr with Lw Input and Output Vltage Requirements, IEEE Transactins n Circuits and Systems-II Express Briefs, Vl. 5, N. 3, 2004, pp di:0.09/tii [4] ITRS, The Internatinal Technlgy Radmap fr Semcnductrs, [5] B. Razavi, Design f Analg CMOS Integrated Circuits, McGraw Hill, New Yrk, 200. [6] P. R. Gray, P. J. Hurst, S. H. Lewis and R. G. Meyer, Analysis and Design f Analg Integrated Circuits, 4th Editin, Jhn Wiley & Sns, New Yrk, 200. [7] S. M. R. Hasan and N. Ula, A Nvel Feed-Frward Cmpensatin Technique fr Fully-Differential CMOS Flded-Cascde Rail-t-Rail Amplifier, Electrical Engineering, Vl. 88, N. 6, 2006, pp di:0.007/s [8] B. Alizadeh and A. Dadashi, An Enhanced Flded-Cascde Op-Amp in 0.8 µm CMOS Prcess with 67 db DC-Gain, IEEE Internatinal Cnference, Faible Tensin Faible Cnsummatin, 30 May- June 20, pp [9] J. Rsenfeld, M. Kzak and E. G. Friedman A Bulk- Driven CMOS OTA with 68-dB DC-Gain, Prceedings f IEEE Internatinal Electrnics Circuits Systems, Tel- Aviv, 3-5 December 2004, pp [0] M. Trakimas and S. Snkusale, A 0.5 V Bulk-Input OTA with Imprved Cmmn-Mde Feedback fr Lw-Frequency Filtering Applicatins, Analg Integrated Circuits and Signal Prcessing, Vl. 59, N., 2009, pp di:0.007/s z [] R. Assaad and J. Silva-Martinez, Enhancing General Perfrmance f Flded-Cascde Amplifier by Recycling Current, Electrnics Letters, Vl. 43, N. 23, 2007, pp. Cpyright 202 SciRes.

6 92 A. AHMADPOUR ET AL di:0.049/el: Cpyright 202 SciRes.