ANALYSIS OF SINGLE EVENT TRANSIENT EFFECTS IN ANALOGUE TOPOLOGIES

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1 ANALYSIS OF SINGLE EVENT TRANSIENT EFFECTS IN ANALOGUE TOPOLOGIES F. Márquez (1), F. Muñz (1), F.R. Palm (1), M.A. Aguirre (1) and M. Ullán (2) (1) Grup de Ingeniería Electrónica, Departament de Ingeniería Electrónica, Escuela Superir de Ingeniers, University f Seville, 41092, Seville, Spain. fernand.marquez@gie.esi.us.es, fmunz@gte.esi.us.es, rgeli@zipi.us.es, aguirre@gte.esi.us.es (2) Centr Nacinal de Micrelectrónica, IMB-CNM (CSIC), 08913, Barcelna, Spain. miguel.ullan@imb-cnm.csic.es I. INTRODUCTION Nwadays, the study f the radiatin effects affecting mixed-mde circuits in space envirnment applicatins is a majr cncern fr designers. Frm this pint f view, the influence f high-energy particle impacts fr system perfrmance is becming crucial as technlgies shrink. Higher peratin frequencies and smaller transistr dimensins lead t a mre critical influence f Single Event Effects (SEE) n the designed circuits. In mdern technlgies, a wellknwn threat such as Single Event Transient (SET) errrs generated frm heavy-in strikes is becming even mre influential. On the ne hand, as higher peratin frequencies can be reached, the SET latching sensitivity f the digital parts f the systems is increased. A transient pulse generated at the input f a cmbinatinal path can be prpagated thrugh the transistr structures and even increase its width; as a cnsequence, it can prduce Single Event Upset (SEU) r Multiple Bit Upset (MBU)[1]. This effect has als been an bject f study in digital technlgies, and has been called Pulse Induced Prpagatin Bradening (PIPB) [2][3]. On the ther hand, analgue parts f the circuits are even mre critically affected by vltage transient perturbatins due t impact-generated electrn-hle pairs cllected by the ndes f devices in deep sub-micrn technlgies. In additin t this, analgue SETs strngly depend n the electrical system-level cnfiguratin f the devices and can seriusly affect the verall perfrmance f the circuits. Therefre, the study f SET influence n analgue circuits has becme an extremely interesting trend [4], as the analysis f SET sensitivity can prvide useful infrmatin in rder t ensure radiatin-hardened designs. Hwever, dealing with the analysis f analgue circuits with mre cmplex tplgies than basic lgic cells is a challenging tread as the number f transistrs increase. Tls like TCAD can extract exhaustive and accurate infrmatin f the effects n the prper design layut [5]. Elements like charge sharing r current distributins are clearly depicted, but spending a huge amunt f cmputing effrt. In this paper, a new tl, named as SESAN (SEE Electrical Sensitivity Analyzer), which can ffer a rapid diagnstic ver analgue designs with a large number f transistrs is presented. This tl will autmatically mdify the circuit netlist adding cnfigurable current surces based n Single Event Transient charge injectin mdels described n literature [6][7]. Additinally, it als implements designer s defined heuristics t autmatically extract the mst relevant results frm simulatins. Frm an initial set f cnfiguratin parameters defined by the user, it is pssible t rapidly find critical ndes n the selected architectures, allwing the pssibility f perfrming a SET sensitivity analysis in mre cmplex analgue designs. As a particular case f study, several cmmnly implemented analgue schemes (peratinal amplifiers -OpAmp) have been designed and analyzed in a 130 nm CMOS technlgy f ST Micrelectrnics using the presented tl. Besides, these tplgies are extensively used as building blcks fr analgue systems. II. AUTOMATION PROCESS In this wrk, the implementatin f the analysis tl has been dne thrugh OCEAN [8] autmatin scripts applied t Spectre netlists under Cadence envirnment. The whle analysis and simulatin prcess fllwed by the prpsed tl is described in Fig 1. The injectin f SETs is based n realistic induced charge mdels applied ver transistr-level versins f the circuits under test. The prpsed simulatin methd permits analyzing the perfrmance f the analgue circuits under emulated irradiatin cnditins. Cmbined with user defined criteria fr errr discriminatin, it is pssible t determine the mst vulnerable ndes that wuld require a radiatin-hardened design.

2 INPUT NETLIST Cadence sftware Simulatin parameters (ndes, Qc, impact times, precisin) Errr discriminatin criteria (defined by user) Ocean Scripts AutmaticTl Mdified Netlist Cadence sftware Cmparisn with nnirradiated perfrmance Output File (Extracted data) The applied simulatin methd is based n reprducing Single Event Transient effects by means f charge generatin mdels that emulate the current injectin prduced by particle impacts. The inizatin mdel applied in electrical simulatin is a current surce with duble expnential dynamics, as illustrated in the next equatin: where r is the rise time related t the plasma track dynamics, d is the dwn time related t charge drift and diffusin in the transistr, and Qc is the net charge assciated t the transient current thrugh the transistr nde. This is a well-knwn mdel widely described in literature [6] that can be implemented using an AHDL mdel. The current surce is injected n the transistr nde affected by the particle track. The rise time will be arund 1ps, and it is determined by the plasma track physics. The dwn time is essentially related t the linear energy transfer (LET) value [9] and marginally t the chsen technlgy, with typical values arund 200 ps. The main simulatin parameter is Qc, with a minimum value knwn as critical charge r the minimal amunt f net charge needed t prduce a SEE. The Qc maximum value can be estimated frm the LET thrugh the fllwing frmula: where is the silicn density, LET is the linear energy transfer, d is the device active depth (typically the well depth), q is the elementary charge, and 3.6 (ev) is the threshld energy fr electrn-hle pair prductin. Parametric simulatins can be set frm the maximum Qc dwn t the critical charge, based n experimental critical LET data in the selected technlgy. A first versin f the prpsed tl has been implemented, which prvides tw main features: an autmatic placement f current surces and the script-based analysis f injected SETs in every nde. The results are prcessed fllwing user defined criteria fr errr discriminatin. Initially, there are tw main pssibilities fr SET analysis ver analgue schemes depending n the purpse f the user. On the ne hand, glbal sensitivity evaluatins can be perfrmed t test the mst vulnerable ndes by injecting lts f SETs in different ndes f the circuit fr several impact times. On the ther hand, a mre selective strategy can be perfrmed by chsing nly cncrete ndes and times cnsidered t be critical by the designers f the circuits under test. In any case, the implemented methdlgy can be extended t the analysis f several emulated impacts in different ndes, even prviding infrmatin f multiple utputs selected by the user. 09/10/08 Fig. 1 Script generatin and analysis methd (1)

3 The evaluatin f the influence f SETs ver an analgue circuit at transistr level is perfrmed in tw steps: A. Step 1: instrumented netlist generatin. Fr the simulatin and analysis prcedure, the presented tl will require the Spectre netlist f the circuit testbench. This test-bench is generated by the circuit designer in rder t test the analgue perfrmance f the scheme. This step des nt represent extra wrk fr the designer. A new netlist will be autmatically generated adding an I rad current surce t the ndes f the analgue circuit that culd be affected by an inizatin transient. The SET injectin is implemented using cnfigurable AHDL mdels, as described befre. Simulatin parameters such as the critical charge (Qc) injected, the rise ( r ) and dwn ( d ) times and the instant in which the particle impact is generated must be defined as inputs by the user (these parameters are technlgy dependent). In this way, the main tasks f the designer at this stage are: T generate a test-bench fr analgue simulatin f the circuits under test. This test-bench will be generated using the CADENCE envirnment with Spectre simulatr, as it is useful fr analgue designers, with n need fr any special cnsideratin abut SET effects. T define the technlgy parameters t be used fr SET injectin by means f the cnfigurable I rad surces, r t lad these parameters frm a technlgy file prvided by the manufacturer. As a result f this prcess, the tl will generate a new Spectre netlist that will be used later by an OCEAN script t evaluate the influence f SETs ver the circuit. It shuld be nted that althugh an I rad can been added t every nde f the designed circuits, the user will be able t select the nes cnsidered fr the analysis allwing a cmputer efficient simulatin. This als helps t the pssibility f simulating cmplex circuits by partial analysis f sub-blcks instead f perfrming a cmplete analysis f all the designed schemes, which usually can invlve t many transistrs in analgue designs. B. Step 2: script generatin In this secnd step, an OCEAN based script fr the analysis f the selected circuits will be generated using the new netlist previusly described. Using Cadence OCEAN scripts, inizing particle impacts can be simulated in Spectre by injecting SETs t the circuits under test. The generated script allws perfrming a set f parametric transient simulatins dependent n the intensity f the particle impacts in ne (r several) ndes at different times chsen by the user. The extracted infrmatin will be determined by user-defined criteria based n a heuristic analysis f the expected errrs. The main tasks t be perfrmed in this phase by the designer are: The user shuld define the bjective impact nde r ndes frm the pssibilities prvided by the tl. It is pssible t cnsider all pssible ndes r t fcus the campaign in a specific part f the circuit. The user shuld define the time f impacts. It is pssible t generate SETs in a randm r a deterministic way, even in the same nde and different time f impact, s that the circuit is evaluated in all pssible wrking pints. The user shuld define the ndes cnsidered as utputs and the maximum deviatin frm a nnirradiated pattern admitted at these ndes. In this way, a set f heuristic criteria based n figures f merit assciated t inequatins fr errr discriminatin is implemented. Fr example, threshlds f utput s SET pulse duratin r vltage deviatins. Fr every simulatin, the utput signal affected by any current induced SET n a circuit nde is cmpared t the nn-irradiated utput respnse. Tw main parameters have been cnsidered fr SET sensitivity analysis: the time in which the transient peak generated by an emulated impact fades and the signal recvers it nrmal shape (recvery time) and the maximum vltage deviatin f the signal cmpared t its ideal (nn-irradiated) respnse. The required precisin t recver frm a transient errr is set t a value f amplitude defined by the user. By means f the implemented script, the effects f injected SETs simulatins in the selected ndes f the circuit are analyzed fr every simulatin and data are extracted and saved t a file t be prcessed. Fig. 2 shws an example f utput file generated by the tl. Frm the extracted results, a sensitivity map f the analgue schemes under study can be btained, determining the mst vulnerable ndes t SETs. It can be nted that all the analysis is perfrmed in a transparent way t the designer, prviding crucial infrmatin fr the next steps f the radiatin-hardened implementatin f the analgue circuits under test.

4 Output Impact nde Qc Timp Trec Vmax /I0/net32 I0_M11 5,00E-13 1,00E /Vut I0_M11 5,00E-13 1,00E /I0/net32 I0_M11 5,00E-13 2,00E /Vut I0_M11 5,00E-13 2,00E /I0/net32 I0_M10 5,00E e /Vut I0_M10 5,00E e /I0/net32 I0_M10 5,00E e /Vut I0_M10 5,00E e /I0/net32 I0_M13 5,00E-13 8,00E /Vut I0_M13 5,00E-13 8,00E /I0/net32 I0_M13 5,00E e /Vut I0_M13 5,00E e Fig. 2 Example f an utput file generated by SESAN III. APPLICATION TO ANALOGUE TOPOLOGIES T test the perfrmance f the develped tl, several amplifier schemes have been designed in a 130 nm CMOS technlgy and analyzed under simulated irradiatin cnditins fllwing the prpsed methdlgy. Fur classical tplgies have been tested: a tw stage OpAmp with Miller cmpensatin (Fig. 3a), a telescpic OpAmp (Fig. 3b), a fully cascded tw stage OpAmp (Fig. 3c) and a current mirrr OpAmp (Fig. 3d). These designs have been chsen t test their rbustness against SET as representative tplgies which include cmmn structures widely implemented in analgue schemes, such as current mirrrs, differential pairs r cascaded stages where vulnerabilities can be fund. M4 M5 M6 M4 M6 M5 V cp V ut M1 M2 V ut M8 M9 V cn M3 (a) M3 M1 M2 (b) M4 M6 M5 V cp M10 M11 M10 M11 M4 M5 M6 V ut M8 M9 V cn2 V ut M12 M1 M2 M8 M1 M2 V cn M12 M13 M3 M9 M3 (c) M13 Fig. 3(a) Tw stage OpAmp with Miller cmpensatin (b) Telescpic OpAmp (c) Fully cascaded tw stage OpAmp (d) Current mirrr OpAmp (OTA) (d)

5 As stated befre, ur tl emplys OCEAN scripts t perfrm the analysis in an autmatic way. The fllwing cnditins were cnsidered fr this case: Different simulatins have been carried ut varying the impact times alng the signal perid fr a given critical charge and nde. In this way, the respnse f the amplifier will be evaluated fr all the pssible bias cnditins f the transistrs. N simultaneus impacts n multiple ndes have been cnsidered, as the prbability f a multiple impact is nearly negligible. Yet, autmatic simulatin scripts allw the evaluatin f ne r mre emulated impacts in every pssible nde f the circuits. At this pint, the main task f the designer will be t generate a test-bench fr analgue simulatin f the circuits under test. In this case, all the schemes have been simulated using the test-bench shwn n Fig. 4a, with a sinusidal input f 400 mvpp amplitude at a frequency f 200 MHz. An example f simulatin fr a mdeled impact is shwn in Fig. 4b, t illustrate the transient respnse at the utput cmpared t the ideal (nn-irradiated) utput f the analgue circuit. Althugh simulatins are initially cnsidered fr islated particle impacts, the analysis can be extended t several ndes, impact times and even different utputs t be prcessed. As an example, a simulatin fr an impact n several instants alng the signal perid n a fixed nde (M12 n the current mirrr scheme f Fig. 3d) is shwn in Fig. 5. The SET injectin campaign perfrmed cnsists n injecting charge pulses n every nde f the selected schemes in different times alng the signal perid t evaluate their perfrmance at the utput fr different biasing cnditins. OpAmp Vin CA (a) (b) Fig. 4 (a) Simulated OpAmp test bench(b) Transient respnse t a SET Fig. 5 Transient respnse t SETs injected at a nde in different times alng the signal perid

6 TABLE I. MOST SIGNIFICANT RESULTS FOR INJECTED SETS Effect Transistr Recvery Vltage Circuit Tplgy time (ns) deviatin (mv) Largest deviatin M Miller OpAmp Lngest recvery M Largest deviatin M Telescpic OpAmp Lngest recvery M Largest deviatin M Current mirrr (OTA) Lngest recvery M Largest deviatin M Fully cascded Lngest recvery M OpAmp A cmprehensive descriptin f the influence f SET in the analgue designed schemes is prvided by the tl, analyzing the times and vltage extracted frm charge injectin simulatins in every nde f the circuit. The required precisin fr recvery times has been set t 4 mv in this wrk. A summary f the mst critical ndes in every scheme btained frm simulatins is included n table I. The infrmatin extracted frm the results shws recvery times f near than ne perid f the utput signals (r even mre in sme schemes) and maximum vltage variatins with similar values t the signal s amplitude. The critical ndes fund are cnsistent with the expected lcatins derived frm theretical design cnsideratins, shwing a crucial influence f injected SETs n biasing ndes and current cpies. IV. CONCLUSIONS A systematic tl fr autmatic analysis f analgue circuits affected by high energy particle impacts has been develped and tested. Thanks t the autmated placement and script generatin, massive injectin campaigns can be perfrmed ver schematic-level circuits t diagnse their SET sensitivity fllwing user-defined criteria. Additinally, the tl perfrmance is independent frm the chsen technlgy, as the infrmatin is prvided by the user as a separate technlgy file. T test the perfrmance f the tl, different tplgies f peratinal amplifiers have been simulated under irradiatin cnditins using current injected SETs, btaining cnsistent results with theretical predictins fr these schemes. These results shw the ptential f ur tl as a valid assessment t find the mst critical ndes in the analgue circuits under test. The implemented methdlgy allws the determinatin f pssible vulnerabilities under irradiatin cnditins fr multiple analgue tplgies and large number f transistrs in a transparent way t the user. Furthermre, the prpsed tl allws t perfrm the analysis f simultaneus impacts in different ndes r even t prcess their influence n several utputs chsen by the user. The wrk carried ut can be cnsidered as a first step f an autmatin prcess fr the design f radiatin-tlerant systems. REFERENCES [1] D.G. Mavis & P. H. Eatn SEU and SET mdelling and Mitigatin in Deep Submicrn Technlgies 45th Annual Internatinal Reliability Physics Sympsium, Phenix 2007 [2] B. Narasimhan, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, M. J. Galadge, O. A. Amusan, W.T. Hlman, A. F. Witulski, W. H. Rbinsn, J. D. Black, J. M. Benedett & P. H. Eatn Characterizatin f Digital Single Event Transient Pulse-Widths in 130-nm and 90-nm CMOS technlgies IEEE Transactins n Nuclear Science, vl. 54, N. 6, Dec [3] J. M. Benedett, P. H. Eatn, D. G. Mavis, M. Gadladge & T. Turflinger. Digital Single Event Transient Trends with Technlgy Nde Scaling. IEEE Transactins n Nuclear Science, vl. 53, N. 6, Dec [4] P. Jaulent, V. Puget, D. Lewis and P. Fuillat, Study f Single-Event Transients in High-Speed Operatinal Amplifiers. IEEE Transactins n nuclear science, vl.55, nº 4, Aug [5] J.M.Mglln, F.R. Palm, M.A. Aguirre, J. Naples, H. Guzman-Miranda and E. Garcia-Sanchez, TCAD Simulatins n CMOS Prpagatin Induced Pulse Bradening Effect: Dependence Analysis n the Threshld Vltage, IEEE Transactins n nuclear science, vl.57, nº 4, Aug [6] G. Messenger, Cllectin f Charge n junctin ndes frm in tracks, IEEE Transactins n nuclear science, vl.29, nº 6, Dec [7] G. I.Wirth, M.G. Vieira, and F.G. Lima-Kastensmidt, Accurate and cmputer efficient mdelling f Single Event Transients in CMOS circuits, IET Circuits, Devices and Systems, 1(2): , April 2007.

7 [8] OCEAN Reference, PV Prduct Dcumentatin. Cadence Design Systems, Inc., [9] P.Eatn, J. Benedett, D.Mavis, K.Avery, M.Sibley, M.Gadlage and T.Turflinger, Single Event Transient Pulse width Measurements Using a variable tempral latch technique. IEEE Transactins n nuclear science, vl.51, nº 6, Dec