INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET)

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1 INTERNATIONAL JOURNAL OF ELECTRICAL ENGINEERING & TECHNOLOGY (IJEET Internatinal Jurnal f Electrical Engineering and Technlgy (IJEET, ISSN 0976 ISSN (Print ISSN (Online Vlume 4, Issue 4, July-August (03, pp IAEME: wwwiaemecm/ijeetasp Jurnal Impact Factr (03: 5508 (Calculated by GISI wwwjifactrcm IJEET I A E M E POWER FACTOR IMPROVEMENT IN SWITCHED RELUCTANCE MOTOR DRIVE USING PWM CONVERTER Mahavir Singh Naruka, D S Chauhan, S N Singh 3 Uttarakhand Technical University, Uttrakhand, INDIA ABSTRACT This paper present the pwer factr imprvement technique in the midpint cnverter based Switched Reluctance Mtr (SRM drive using a AC-DC three level Pulse Width Mdulatin (PWM cnverter A cnventinal SRM drive prduces very high level f harmnics cntent and pr pwer factr at ac mains The prpsed cnverter with midpint cnverter fed SRM drive imprves the pwer factr at ac mains with lw current harmnics The SRM drive with cnverter is mdeled and its perfrmance is simulated in Matlab/Simulink envirnment Keywrds: Midpint cnverter, Pwer quality, THD, PFC, SRM, PWM cnverter I INTRODUCTION Switched Reluctance Mtr (SRM have a simple and rbust cnstructin; they eliminate permanent magnets, brushes, cmmutatrs and windings n the rtr side As a result f its inherent simplicity, SRM ffers advantages f reliable and lw cst variable speed drives [-] This mtr drive needs pwer cnverters fr its peratin Many type f pwer cnverters fr SRM drive is reprted in literature [3-4] These cnverters require stable DC supply as an input surce Fr this purpse if a cnventinal rectifier unit is used as frnt end cnverter, the supply current drawn is in pulse frm This supply current is f very lw pwer quality The blck diagram f cnventinal SRM drive is shwn in fig- It can be divided int supply utility, AC/DC cnverter, Capacitr netwrk, DC/DC machine cnverter and SRM The attractive features f these cnverters are cnstant DC bus vltage, lw harmnic distrtin f the utility current, bi-directinal pwer flw & cntrllable pwer factr It is very difficult t maintain the balanced vltage acrss each capacitr at DC bus Tw capacitr split the DC link vltage int tw equal vltages Phase vltage f SRM is prvided by each capacitr By varying the cnductin perid f a phase, we can balance the capacitr vltage Surce current drawn by the mtr is in pulse frm s it induces ripple vltage acrss the capacitrs 48

2 Trque ripples and THD (Ttal Harmnics Distrtin f supply current are increased due t the unbalancing f vltages acrss capacitrs T imprve the input pwer factr and DC capacitr vltage balancing, a pwer factr cntrller is needed at input side f the cnverter Fr this a three level PWM cnverter fed SRM drive is designed, mdeled and simulated in Matlab/Simulink Fig- Bridge rectifier as frnt end cnverter fed SRM drive The prpsed SRM drive system is capable f imprving the pwer factr clse t unity with lw THD f supply current The pwer quality is als within IEEE standard [5] II PROPOSED SYSTEM CONFIGURATION In this paper, a nn linear cntrl technique fr a PWM three level vltage surce AC-DC cnverter assciated with a mid pint IGBT based machine cnverter is prpsed T imprve the pwer factr at the input ac mains, a PWM cnverter is used as frnt end cnverter fr SRM drive Fig- shws the schematic diagram f the prpsed cnverter The prpsed system cnsists f a PWM cnverter which is an ac-dc bst cnverter and mid pint cnverter based SRM drive In this system the mid-pint cnverter will be used as a machine side cnverter & PWM will wrk as a frnt end cnverter AC Surce Dide bridge rectifier Frnt-end cnverter Machine cnverter Gate pulse (PWM generatr SRM Fig- prpsed PWM cnverter fed SRM drive The prpsed cnverter has resistr-inductr series circuit n each input line & tw capacitr n the DC link The cnverter has a three level bridge f selected frced-cmmutated pwer electrnics devices The series RC snubber circuits are cnnected in parallel with each switch device The IGBT bridge cnverter has a cmbinatin f universal bridge and discrete IGBT switches These pwer electrnic switches are cntrlled by gate pulses, which are given by PWM Gate pulse generatr system The PWM gate pulse generatr has a cmbinatin f vltage & current regulatr The utput f the cntrller is given t the discrete 3-phase PWM generatr, which prduces the cntrlled pulse as per requirement 49

3 III DESIGN & ANALYSIS OF CONVERTER Traditinally Dide Bridge Rectifier (DBR are used fr rectificatin This rectifier can nly prduce a cnstant DC vltage, which is a functin f system vltage A cntrl rectificatin system can be used t prduce variable dc utput vltage But bth these rectifier behave as a nn-linear lad A pulse width mdulated (PWM rectifier, shwn in Fig-3, draws near sinusidal current frm the supply mains Als the DC link vltage can be regulated & the supply pwer factr is adjustable By applying KVL n supply side and KCL n lad side gives dis L = vs SV dt ( dv C = Sis V dt R ( where S is the switching functin f the PWM cnverter & V s =V m sinωt is the input ac surce vltage with the amplitude f V m and angular frequency f ω Resistance n the ac side is neglected The main cntrl bjectives fr such PWM cnverter are t prduce an input ac current i s with lw harmnics cntent at a high pwer factr and t cntrl the average DC vltage V It is clear that unity pf can be achieved, if the ac input current tracks the fllwing reference current I s *=I m sinωt (3 By the cmbinatin f eq (, ( & (3, we can write S ( t = V ss ( v s * s di L dt Vss dvs S0 ( t = ( + C (4 * i R dt s where V ss =V +V hr is the steady state utput vltage with a DC reference vltage V and a harmnic ripple cntent V hr Nw let X =i s -i s *, X =V -V ss, S=S + S (5 Where x & x are the state variables and S is the perturbatin f the switching functin S By using the abve equatins the fllwing resulting equatins are btained L x = S x ss + x S( V (6 x C x = S x S( is * + x (7 R With the switching functin variable (6 & (7 are nn-linear & time varying 50

4 A Cntrl strategy Accrding t the Lyapunv stability thery, any linear r nn-linear system must eventually settle dwn t an equilibrium pint means every system is stable if there exists a psitive definite Lyapunv functin V(x, whse time derivative is negative definite[5] Then the equilibrium pint at the rigin (X =0,X =0 is glbally asympttically stable Nw cnsider the fllwing psitive definite Lyapunv functin fr the cnverter V ( x = Lx + Cx (8 Taking the derivative f eq(8 with respect t the time gives V ( x = x L x + x C x (9 If we put the value f Lx & Cx frm eq(6,(7 t eq (9 V ( x = ( x is * xv ss S x R (0 By the equatin (0, we can cnclude that derivative f V(x alng with any system trajectry becmes negative definite, if S is chsen t be S = β ( x is * xv ss, β< ( where β is an arbitrary real cnstant number In rder t generate the switching functin S (r cmpute in a digital implementatin, it is necessary t predict the time varying steady state utput vltage Vss=V+ Vhr(t fr the present perating pint f the cnverter In this methd there is a prblem fr calculatin f Vhr(t because the methds fr finding the ripple cmpnent Vhr is cmplex and less accurate s if we neglect this cmpnent, the calculatin will be simple S = β ( x is * xv, β< ( There are three criterin fr selectin f arbitrary real cnstant (β (i It gives a stability regin as large as pssible (ii Satisfactry dynamic respnse is btained ver the perating range f the cnverter (iiiripple cntent shuld be minimum A typical range f the β fr the cnverter in this study is fund t be -000 β B PWM gate pulse generatin Fr the purpse f triggering pulses the input supply vltage V abc, supply current I abc & generated DC link vltage V dc are filtered thrugh lw-pass filters The nrmalized supply vltage are fed t the Phase Lcked Lp (PLL system This PLL can be used t synchrnize n a set f variable frequency, three phase sinusidal signals The utput f this PLL system are fed t current & vltage regulatr incrprate with nrmalized supply currents & vltages The signal generated by the cmbinatin f these regulatrs is fed t the discrete 3-phase PWM generatr in series with delay functin The blck diagram are shwn in Fig-3 & Fig-4 5

5 V dc ref +_ PI Saturatin Cntrller I dref V dc Fig-3 Blck diagram f DC vltage regulatr V abc I abc d dc Anti-Aliasing Filters Zer Order Hld Cntrller /Z G Pulse Unit Delay Fig-4 Blck diagram f regulatr A discrete 3-phase PWM generatr blck generates the pulse fr carrier based pulse-width mdulatin cnverter The blck can be used t fire the frced-cmmutated devices (FET s, GTO s r IGBT s f -level r 3-level cnverters By using a single bridge r twin bridges cnnected in twin cnfiguratin vectrized utputs P & P which cntains either 6-pulses( -level r - pulses(3-level are used fr triggering C Cntrl f SRM The mdel used in this scheme is a current-cntrlled 60-kW 6/4 SRM drive using the SRM specific mdel based n measured magnetizatin curves The SRM is fed by a three-phase asymmetrical pwer cnverter having three legs, each f which cnsists f tw IGBTs and tw freewheeling dides During cnductin perids, the active IGBTs apply psitive surce vltage t the statr windings t drive psitive currents int the phase windings During free-wheeling perids, negative vltage is applied t the windings and the stred energy is returned t the pwer DC surce thrugh the dides The fall time f the currents in mtr windings can be thus reduced By using a psitin sensr attached t the rtr, the turn-n and turn-ff angles f the mtr phases can be accurately impsed This switching angle can be used t cntrl the develped trque wavefrms The phase currents are independently cntrlled by three hysteresis cntrllers which generate the IGBTs drive signals by cmparing the measured currents with the references The IGBTs switching frequency is mainly determined by the hysteresis band IV MATLAB SIMULATION The PWM cnverter alng with midpint cnverter based SRM drive is mdelled and it is simulated in Matlab/Simulink envirnment shwn in fig-5 Three phase 600V, 50Hz ac supply is given t the PFC cnverter & the DC link vltage is cntrlled t 60V The IGBT based midpint machine cnverter is cnsidered fr 60kW, 6/4 SRM in this simulatin Object f this paper t reduce the input current harmnics and give the almst unity pwer factr n supply side The cncerned wavefrms f simulatin are shwn in fig-6 & table-i 5

6 Fig-5: Matlab simulatin mdel Fig-6 Steady State Respnse Of Input Supplied Current, Vltage Wavefrm, Dc Link Output & Thd Of Supplied Current 53

7 TABLE I PERFORMANCE PARAMETERS OF PROPOSED PFC FOR SRM DRIVE Speed (rpm Trque (N-m V dc (Vlts THD (% Pwer factr V RESULT & DISCUSSION The perfrmance f the prpsed PWM cnverter fed SRM drive has been simulated in Matlab/Simulink envirnment The results are cmpared with the cnventinal cnverter fed SRM frm the bridge rectifier The current drawn by the cnventinal cnverter is nn-sinusidal, distrted & cntaining high level f harmnic distrtins The percentage THD f supply current is 665% with fundamental current 364(r m s AT 0% f rated lad, THD f supply current is 939% with fundamental current f 49 %(r m s As the lad trque reduced the THD f supply current is increased This shws that the cnventinal bridge rectifier fed SRM has a very high THD & lw pwer factr f supply current [6] Fig-6,Shw the results f Steady state & dynamic perfrmance f supply current, THD & dc link vltage fr the prpsed PWM cnverter based SRM VI CONCLUSION The PWM cnverter alng with midpint cnverter based SRM drive is designed & simulated in Matlab/Simulink envirnment Three phase 600V, 50Hz ac supply is given t the PFC cnverter & the DC link vltage is cntrlled t 60V The IGBT based midpint machine cnverter is cnsidered fr 60kW, 6/4 SRM in this simulatin The btained results have been cmpared with cnventinal rectifier Using this technique, the pwer quality has been imprved as cmpared t the cnventinal bridge cnverter It has been seen that this scheme can withstand under wide range f speed with almst unity pwer factr The THD f supply current and pwer factr are well within IEEE 59 standard limits [7] REFERENCES [] J W Ahn, Switched Reluctance Mtr (Krean, Osung Media, 004 [] R Krishnan, Switched Reluctance Mtr Drives: Mdeling, Simulatin, Analysis, Design and Applicatins CRC Press, 00 [3] S Vuksavic and V R Stefanvic, SRM Inverter Tplgies: A Cmparative evaluatin IEEE Trans On industry Applicatins, vl 7, n 6,pp , Nv/Dec99 [4] Pllck and B W Williams, Pwer cnverter circuits fr Switched Reluctance Mtrs with the minimum number f switches in Prc Inst Elect Eng, vl 37, pt B, n-6, 990, pp

8 [5] Hasan K C and Osman K, Cntrl strategy fr single phase PWM ac/dc vltage surce cnverters based n Lyapunv s direct methd, Internatinal Jurnal f electrnics, 000, Vl-87, N-, pp [6] M Rajesh, Bhim singh Pwer quality imprvement in Switched Reluctance mtr using Vienna Rectifier (0 The IEEE website [Online] Available: [7] M Shell (00 IEEEtran hmepage n CTAN [Online] Available: [8] Dr Hina Chandwani, Himanshu N Chaudhari and Dhaval Patel, Analysis and Simulatin f Multilevel Inverter using Multi Carrier Based PWM Cntrl Technique, Internatinal Jurnal f Electrical Engineering & Technlgy (IJEET, Vlume 4, Issue 3, 03, pp 00-08, ISSN Print : , ISSN Online: [9] Pradeep B Jyti, JAmarnath and DSubbarayudu, The Scheme f Three-Level Inverters Based n Svpwm Overmdulatin Technique fr Vectr Cntrlled Inductin Mtr Drives, Internatinal Jurnal f Electrical Engineering & Technlgy (IJEET, Vlume 4, Issue, 03, pp 45-60, ISSN Print : , ISSN Online: [0] KVijaya Bhaskar Reddy and GV Siva Krishna Ra, Mdeling and Simulatin f Mdified Sine PWM Vsi Fed Inductin Mtr Drive, Internatinal Jurnal f Electrical Engineering & Technlgy (IJEET, Vlume 3, Issue, 0, pp , ISSN Print : , ISSN Online: