Operation and Control Design of New Three-phase Inverters with Reduced Number of Switches

Transcription

1 6 Internatinal Sympsium n Pwer Electrnics, Electrical rives, Autmatin and Mtin Operatin and ntrl esign f New Threephase Inverters with educed Number f Switches Ahmed arwish*, Yacha Wang, errick Hlliday and Stephen Finney Electric and Electrnic Engineering University f Strathclyde, Glasgw, UK *ahmed.mhameddarwishbadawy@strath.ac.uk Abstract /A inverter tplgies having reduced numbers f switches t reduce csts, ttal inverter size and switching lsses have previusly been prpsed. In additin, these tplgies reduce the likelihd f semicnductr switch damage, and have lwer cmmnmde currents. This paper prpses new designs fr inverters with reduced switch numbers. Fr threephase systems, the prpsed inverters use fur switches instead f the six used in the traditinal threephase ltage Surce Inverter (SI). mpared t the traditinal FurSwitch ThreePhase (FSTP) inverter, the prpsed FSTP inverters imprve the vltage utilisatin factr f the input dc supply, withut the need fr triplen injectin. Slidingmde cntrl is used t demnstrate the dynamic respnse and rbustness f the inverters. Als the paper presents new singlephase inverters with tw switches instead f the fur used in the traditinal SI. The capability f suppressing the nd rder current harmnic frm the input dc side is discussed. The basic structures f the prpsed inverters and their peratin, switch ratings, cntrller design with supprting mathematical equatins, and MATAB/SIMUINK results are presented. Practical results, based n labratry prttype circuitry cntrlled using a Texas Instruments TMSF8335 SP, are presented t demnstrate the design flexibility and peratin f the prpsed tplgies. Keywrdscmpnent; dc/ac inverters; sliding mde cntrllers; Furswitch threephase inverter (FSTP) I. INTOUTION Gvernmental agencies insistence n reducing O generatin has created internatinal interest in pwer system and micrgrid research and develpment []. Numerus inverter tplgies t imprve the peratin f micrgrid systems have been presented. Traditinally, the cnventinal SixSwitch ThreePhase (SSTP) twlevel ltage Surce Inverter (SI) has been the mst cmmn cnverter tplgy fr many applicatins such as renewable energy cnversin systems, mtr drives, and wind turbine systems. Hwever, cnverter tplgies with reduced switch number are demanded by sme lwpwer applicatins, such as phtvltaic, fuel cells and electric vehicles, in rder t reduce cst and size, and t increase system efficiency. The nvel threephase twlevel SI with fur switches, shwn in Fig., was implemented []. In this FurSwitch ThreePhase (FSTP) inverter, tw f the utput lad vltages are fed frm the tw inverter legs, whilst the third phase is fed directly frm the dc side. In cmparisn with the cnventinal SI, the FSTP inverter has imprtant features such as lwer cst and higher efficiency, and reduced numbers f measurements, gate drives and realtime calculatins [3]. In additin, the FSTP inverter reduces the maximum cmmn mde vltage by 33% in cmparisn with the SSTP inverter [3, 4]. Because f the reduced interactin between switches in the FSTP inverter, switch reliability is increased. The main disadvantage f the FSTP is that the maximum utput vltage acrss the lad is limited t 8.8% f the input dc vltage []. Anther disadvantage is that the third phase f the utput lad is fed frm the dc side, which may generate dc current cmpnents in the utput threephase currents. These dc current cmpnents are hazardus and cntrl effrt shuld suppress them. IEEE 574 standards restrict the dc current cmpnents t <.5% f the rated MS current while IE 677 standards limit them t <%. In additin, the fluctuatin f dclink capacitr vltage at the fundamental frequency results in fluctuatins f the utput vltages and currents f the FSTP inverter [5]. The prblem f dclink vltage scillatin necessitates mdified pulsewidth mdulated (PWM) signals t cntrl and create the desired utput vltage during the switching perid [3]. Practically, the dclink split capacitrs will nt have equal capacitance, s vermdulatin f the switch PWM prcess is needed t maintain a cnstant dclink midpint vltage [5]. The peratin, cntrller design, and perfrmance f the FSTP have been discussed in the literature [3][]. An FSTP inverter based n the cnventinal SEPI cnverter has been implemented and cntrlled using the sliding mde apprach []. The achievable utput vltage frm the SEPIbased FSTP inverter has been shwn t be duble the vltage f the cnventinal FSTP inverter under the same cnditins. In additin, the inverter slved the prblem f circulating current in the dclink capacitrs. Hwever, like the cnventinal FSTP, the SEPIbased inverter is fed frm the input dc side directly, hence dc current cmpnents may be injected int the ac grid. Of the thirtythree basic dc/dc cnverters, there are fur bidirectinal cnverters capable f prviding utput vltage with psitive and negative plarities. These cnverters are shwn in Fig. as tw vltage buck and tw vltage bst cnverters. Based n these cnverters, new threephase inverters with fur switches can be generated. Unlike ther FSTP inverters, the prpsed inverters d nt have direct cnnectin between the ac phases and the dc side vltage. nsequently, the prblem f dc current injectin int the ac grid des nt arise. Because they d nt require direct cnnectin between the ac and dc sides, the prpsed /6/$3. 6 IEEE 78

2 cnverters can perate as dc/ac inverters and ac/dc rectifiers. In dc/ac inversin mde, the prpsed inverters duble the maximum utput threephase vltage in cmparisn with the cnventinal FSTP inverter. Unfrtunately, the prpsed cnverters are time variant systems where the transfer functin describing the relatinship between the input and utput vltages and currents depends n the switching perids f the switches. This results in a cmplex stable design because the cnverter ples and zers travel thrugh a lng trajectry. Mrever, the timevarying transfer functin leads t utput vltage and current distrtin [3, 4]. nverter stability and reliability decrease with increasing passive element values. Hwever, reducing the inductance and capacitance results in larger highfrequency ripple current and vltage, hence the ttal harmnic distrtin (TH) f the utput current and vltage will increase. Increasing the passive element values increases the stred energy within the inverter, prducing third rder harmnic cmpnents in the input dc current. This paper presents new inverter/rectifier tplgies with reduced switch numbers based n the bidirectinal dc/dc cnverters in Fig.. The paper explains their nrmal peratin, and cmpares and perfrmance evaluates the prpsed inverters. ntrller design fr the prpsed cnverters is presented based n sliding mde cntrl (SM) techniques. Practical results substantiate the design flexibility f the prpsed tplgies when cntrlled by a TMSF8335 SP. dc a S b S S 3 c S 4 Fig.. nventinal FurSwitch ThreePhase (FSTP) inverter II. / ONETES WITH POSITIE AN NEGATIE OUTPUT OTAGE The fur twswitch/dide pair dc/dc cnverters with psitive and negative utput vltages are shwn in Fig.. Tw f these cnverters (bg and bg) are vltage buck cnverters whilst the ther tw (BG and BG) are vltage bst cnverters. The relatin between utput vltage ( ) and input vltage ( in ) is defined by the vltage cnversin rati (M) as: M() is the cnverter duty rati, defined as: t n where t n is the nduratin f switch S and t s is the ttal switching perid. t s in N () () I S S c Is c. in S in I I S S in c (a) bg I I I S S. c (b) bg in (c) BG (d) BG Fig.. / cnverters with bidirectinal utput vltages: (a) and (b) vltagebuck cnverters, (c) and (d) vltagebst cnverters. The vltage cnversin ratis f the cnverters are: M ( ) fr bg and bg M ( ) fr BG and BG The vltage cnversin ratis in equatins (3) and (4) are pltted against duty rati as shwn in Fig.3 /in uty ati (a) bg and bg /in 5 5 S S I (3) (4) uty ati (b) BG and BG Fig.3. ltage cnversin rati (M) versus duty rati () BG and BG have a discntinuus vltage rati ver the full perating range and cannt generate zer utput vltage ( =). Hwever, bg and bg have cntinuus vltage ( / in ) versus duty rati. The MATAB simulatin results f Fig. 4 shw buck cnverter bg and bg perfrmance at different duty ratis. Output ltage () 5 5 =.4 = time (s) (a) bg Output ltage () 5 5 =.4 = time (s) (b) bg Fig. 4. Buck cnverter perfrmance ( in=, =μf, =μf, = =mh, t s=33μs, and lad =5Ω) 79

3 III. FOUSWITH THEEPHASE INETES Tw cnverters can be cnnected differentially acrss the threephase lad t frm an FSTP inverter. ircuit diagrams f these inverters, based n the bg and bg cnverters, are shwn in Fig. 5. v c in in S I a S 4 I b I a r r I b r v c r S S 3 v c v c (a) bg FSTP inverter r r I a S S S 4 v c I a r S 3 v c I b r I a vc v c (b) bg FSTP inverter Fig. 5. Prpsed FSTP inverters i a v ga i b v gb i c v gc i a v ga i b v gb i c v gc Each cnverter prduces sinusidal vltage with a peak m : vc () t m sin( t ) v () t sin( t ) c The utput threephase vltages are: m 3 v ga ( t) g sint v ( ) sin( gb t g t 3 ) v ( t) sin( t ) gc g where ω = πf is angular frequency. This causes threephase currents i a, i b and i c t flw in the lad: 3 (5) (6) where: ia ( t) I sint i ( ) sin( b t t 3 ) i ( t) I sin( t ) c I 3 sin 3 cs I 3 cs 3 sin 3 g tan I 3 3 cs sin I sin cs g I 3 3 cs sin I sin cs (9) g m cs nverter duty ratis and are calculated frm (3) and (5) as: in () t in v c () t () in () t in v c () t MATAB simulatins fr penlp peratin f the tw cnverters are shwn in Errr! eference surce nt fund. and Errr! eference surce nt fund., using the parameter values listed in TABE I. TABE I. SIMUATION PAAMETES Parameter alue f 5Hz t s 33μs μf (bg) and 5μF (bg) μf (bg) and μf (bg) mh mh mh.5ω r and r.5ω in T study the dynamics f the buck cnverters, each can be mdelled and represented by its state space average mdel as fllws: a) nverter bg The equivalent circuits fr cnverter bg during the different switching states are shwn in Fig. 8, and include inductr parasitic resistances (r and r ) and the utput inductance and resistance ( and ). The duratin t n defines the perid that either S r its antiparallel dide cnduct. The average mdel f bg is expressed in (), and its plezer map, presented in Fig. 9, shws that cnverter dynamics change with the smallsignal duty rati. 3 (7) (8) 8

4 T Time(s) T 3T T Time(s) T 3T (a) uty ratis and (a) uty ratis and v ga v gb v gc v ga v gb v gc T Time(s) T 3T (b) Output threephase vltages v ga, v gb, and v gc c () T Time(s) T 3T (b) Output threephase vltages v ga, v gb, and v gc 4 v c v c c &c () 3 T Time(s) T 3T (c) v c v c v c c &c () c &c () T Time(s) T 3T v c (c) v c and v c v c T Time(s) T 3T (d) nverters vltages v c and v c T Time(s) T 3T (d) nverters vltages v c and v c 6 i a i b i c 6 i a i b i c T Time(s) T 3T (e) Output threephase currents i a, i b, and i c Fig. 6. bg FSTP inverter utput vltages and currents T Time(s) T 3T (e) Output threephase currents i a, i b, and i c Fig. 7. bg FSTP inverter utput vltages and currents 8

5 in in r I c c g I r (a) t < t n r I c c g I r (b) t n t <t s Fig. 8. bg cnverter cnfiguratins specified trajectries, representing the nnlinear nature f these cnverters. in I c r r I c (a) t < t n r r I c in I c g g r I I ) ( c c r I I c c I I in g Imaginary Axis (secnds ) 3 x 4 PleZer Map eal Axis (secnds ) Fig. 9. bg cnverter plezer map () r (b) t n t <t s Fig.. bg cnverter cnfiguratins I I c c r I I c c I I in g Imaginary Axis (secnds ) x 4 PleZer Map () b) nverter bg The equivalent circuits fr cnverter bg are shwn in Fig., and the crrespnding average mdel is expressed in (). Based n the average mdel, the plezer map is shwn in Fig.. As with the bg cnverter, the ples mve alng eal Axis (secnds ) Fig.. bg cnverter plezer map Because the prpsed inverters are highrder systems, ariable Structure ntrl (S) [5] is an attractive slutin 8

6 fr cntrller design. Sliding Mde ntrl (SM) [5], which belngs t a family f S techniques, is therefre applied t the prpsed inverters. The integral sliding mde cntrller fr the prpsed inverters is shwn in Fig., where r and r are the parasitic resistances f and respectively, and K, K and K 3 are the cntrller gains. i * v v c in i in r i K K 3 K r S PWM (v c v K ) K u eq S Fig.. Sliding mde cntrller fr bg FSTP inverter I. EXPEIMENTA ESUTS The system cncept, presented mathematical analysis and simulatins are validated using an experimental bg FSTP inverter with the parameters listed in TABE I and cntrlled using a TMS3F8335 SP. The dc input vltage ( in ) is fed frm a Srensen SG A5XkW dc pwer supply. Fur IFPS4N6K MOSFET switches are emplyed fr switches S 4 with their freewheel dides 4. A lairtrnic M 8F3, 45, threephase auttransfrmer is used t match the ac grid vltage. Fig. 3 shws the vltages and the currents fr the prttype inverter. [5ms/div; /div] (a) nverters vltages v c and v c [5ms/div;.5A/div] (b) Threephase utput currents Fig. 3. bg FSTP experimental results. ONUSION New dc/ac threephase inverters with a reduced number f switches have been prpsed. educing the switch number imprves efficiency and reliability f dc/ac inverters. The prpsed threephase inverters have greater maximum utput peak vltage than the cnventinal FSTP tplgy. Unlike the cnventinal FSTP, the prpsed inverters d nt have a dc bias in the cnverter utput vltages. Hwever, the prpsed inverters are highrder systems where the ples f their transfer functins mve as the duty rati is varied. nsequently, classical cntrl strategies are nt readily implemented. Sliding mde cntrl is prpsed fr these inverters, in rder t generate pure sinusidal vltages and currents. The paper als presents new singlephase dc/ac inverter tplgies with the ability t decuple the nd rder harmnic cmpnents frm the input dc side. AKNOWEGEMENT The authrs wish t acknwledge the supprt f EPS grant EP/K3596/, Underpinning Pwer Electrnics : nverters Theme. EFEENES [] Y. Xue, J. eng, and S. Ma, Pwer flw cntrl f a distributed generatin unit in micrgrid, in Prc. IEEE Int. Pwer Electrn. Mtin ntrl nf., 9, pp. 5 [] H. Breck and J... Wyk, A cmparative investigatin f a threephase inductin machine drive with a cmpnent minimized vltagefed inverter under different cntrl ptins, IEEE Trans. Ind. [3] M. B. de. rrea,. B. Jacbina, E... da Silva, and A. M. N. ima, A general PWM strategy fr furswitch threephase inverters, IEEE Trans. Pwer Electrn., vl., n. 6, pp , Nv. 6. [4] El Badsi, B., Buzidi, B., and Masmudi, A., T scheme fr a furswitch inverterfed inductin mtr emulating the sixswitch inverter peratin, IEEE Trans. Pwer Electrn., l. 8, N. 7, pp , July 3. [5] S. asgupta, S. N. Mhan, S. K. Sah, and S. K. Panda, Applicatin f furswitchbased threephase gridcnnected inverter t cnnect renewable energy surce t a generalized unbalanced micrgrid system, IEEE Trans. Ind. Electrn., vl. 6, n. 3, pp. 4 5, Mar. 3. [6].T. in,.w. Hung, and.w. iu, Psitin sensrless cntrl fr furswitch threephase brushless mtr drives, IEEE Trans. Pwer Electrn., vl. 3, n., pp , Jan. 8. [7] M. K. Metwally, and H. Z. Azazi, Furswitch Threephase Inverter Perfrmance Fed Sensrless Speed ntrl Inductin Mtr rives Using Mdel eference Adaptive System, Electric Pwer mpnents and Systems, vl.4, n.7, 4 [8] X. Tan, Q. i, H. Wang,. a, and S. Han, ariable parameter pulse width mdulatinbased current tracking technlgy applied t furswitch threephase shunt active pwer filter, IET Pwer Electrn., vl. 6, n. 3, pp , Mar. 3. [9] S. B. Ozturk, W.. Alexander, and H. A. Tliyat, irect trque cntrl f furswitch brushless mtr with nnsinusidal back EMF, IEEE Trans. Pwer Electrn., vl. 5, n., pp. 63 7, Feb.. [] K.. Hang, Z. Q. Zhu, and M. P. Fster, Influence and cmpensatin f inverter vltage drp in direct trquecntrlled furswitch threephase PM brushless A drives, IEEE Trans. Pwer Electrn., vl. 6, n. 8, pp , Aug.. [] T.S. ee and J.H. iu, Mdeling and cntrl f a threephase furswitch PWM vltagesurce rectifier in dq synchrnus frame, IEEE Trans. Pwer Electrn., vl. 6, n. 9, pp , Sep.. [] M. S. iab, A. Elserugi, A. M. Massud, A. S. AbdelKhalik, and S. Ahmed, A FurSwitch ThreePhase SEPIBased Inverter, IEEE Trans. On Pwer Electrn., vl.3, n.9, pp , Sept 5 [3] A. arwish,. Hlliday, S. Ahmed, A. M. Massud, and B. W. Williams, "A SingleStage ThreePhase Inverter Based n uk nverters fr P Applicatins," IEEE Jurnal f Emerging and Selected Tpics in Pwer Electrnics, vl., pp , 4. [4] P.. Prasanna and A. K. athre, "Analysis, esign, and Experimental esults f a Nvel SftSwitching Snubberless urrentfed HalfBridge FrntEnd nverterbased P Inverter," IEEE Transactins n Pwer Electrnics, vl. 8, pp. 3933, 3. [5]. Utkin, J. Guldner, and J. X. Shi, Sliding Mde ntrl in Electrmechanical Systems. ndn, U.K.: Taylr and Francis,