Course Description. Learning Objectives. Part 1: Essential high-speed PCB design for signal integrity (3 days)

Transcription

1 TRAINING Bei dem hier beschriebenen Training handelt es sich um ein Cadence Standard Training. Sie erhalten eine Dkumentatin in englischer Sprache. Die Trainingssprache ist deutsch, falls nicht anders angekündigt. Curse Title Curse Categry Duratin Understanding High Frequency PCB Design High Speed, RF, and EMI System Intercnnect Design Allegr & OrCAD, Language and Methdlgy Curses fr Chip and SPB Design 5 Days Curse Descriptin Part 1 f this tw-part curse applies basic physical principles t develp an understanding f the key issues f high-speed design, t ensure a successful design fr signal integrity. These range frm cntrlling reflectins and crsstalk t the design f the pwer distributin system and the PCB layer structure. The curse is liberally illustrated with examples and what if scenaris shwing by simulatin the effects f varying different parameters, enabling participants t develp an understanding f their relative imprtance and magnitude. Helpful guidelines n assessing and implementing best practice are included. Practical issues are cnsidered thrughut. The basic techniques develped can be applied immediately t imprve PCB design, withut the use f EDA signal integrity tls, but the curse als prvides a much needed fundatin fr understanding hw t benefit frm the use f such tls. Part 2 f this tw-part curse builds seamlessly n the principles and practice established in Part 1, extending them t develp techniques fr design and test at frequencies abve 1 GHz fr Gb/s serial transmissin and fr cntrlling the generatin and prpagatin f EMI at the PCB level. Key tpics cver signal quality, material effects and EMC frm cmpnents t backplanes. Nte: This is an integrated curse where the cncepts and methds develped in Part 1 are applied directly t the tpics in part 2. Delegates t Part 2 f the curse are therefre strngly advised t attend Part 1 first. Learning Objectives Part 1: Essential high-speed PCB design fr signal integrity (3 days) Signal wavefrms, frequency cmpnents and risetime. Bandwidths f analg and digital signals. Hw capacitance and lp inductance n a PCB determine signal behaviur. Current paths n a PCB. Impedance cntrl f the pwer distributin system. Cntrlling induced nise - decupling netwrks, PCB planes, bandwidth requirements. Optimizing pwer delivery. Track impedance, reflectins, and line terminatins. Effects f PCB structure, materials, gemetry and fabricatin. Track impedance testing. Cupled lines. Odd and even mdes differential and cmmn mde currents. Differential transmissin, ruting and terminatin. Unwanted cupling crsstalk. Near end and far end crsstalk, effects f cupled length, multiple lines. ICs fr high-speed design - I/O characteristics, I/V curves, transitin timing. Behaviural device mdels, IBIS standards. PCB ruting tplgies. Branching and nn-branching tplgies. Cnstraints. Discntinuity effects cnnectrs, vias, stubs etc. Equalisatin, multiple capacitance lading, clck distributin.

2 Part 2: PCB design at RF - multi-gigabit transmissin, EMI cntrl, and PCB materials (2 days) High frequency measurement and test cmpnents and signal paths. Time dmain (scpe, TDR/TDT) and frequency dmain (VNA, spectrum analyser). Prbe bandwidth. S-parameters. Gb/s transmissin n PCBs - applicatin f transmissin engineering methds. PCB track effects n signal quality (BER, ISI, jitter). Technlgies (e.g LVDS, PCI Express). PCB requirements t meet system perfrmance. Frequency-dependent PCB transmissin lines. Wavefrm degradatin due t cnductr and dielectric lss. PCB material selectin frequency behaviur, manufacturing and cst tradeffs, and criteria fr acceptable signal perfrmance. EMC cntrl. EMI mechanisms what factrs can we cntrl? Wave prpagatin, near and far field impedance. RF field generatin n a PCB. Differential t cmmn mde cnversin and radiatin. Cntrlling EMI generatin n PCBs. Image planes, stackup, return currents. Grunding schemes, cmmn impedance cupling, partitining, split planes. EMI frm cmpnents t systems. IC package parasitics, grund bunce, cmpnent level effects. Filtering, islatin and bridging n PCBs. Intercnnectins, cables, backplanes, signal ruting. Audience Design engineers seeking in-depth knwledge f high-speed PCB design, signal integrity issues, high frequency effects and EMC. As the curse is built up frm basic electrical principles it is suitable fr engineers frm many areas f applicatin, and als fr new graduates. PCB designers wrking n digital r mixed signal bards with design rules gverning track impedance cntrl, line terminatins, ruting t minimise nise cupling etc. will als benefit frm this curse. Curse Agenda Part 1: Essential High-speed PCB Design fr Signal Integrity Mdule 1 - High-speed design verview Design issues fr the engineer and fr the PCB layut designer When is a design high speed? Industry drivers frce high speed Signal integrity and the high speed challenge Why we need t cnsider wave prpagatin and wave prperties The PCB cntributin High speed PCB design key requirements Mdule 2 - Fundamental electrical cncepts Time dmain and frequency dmain Signal bandwidth - analg signals and digital signals Digital wavefrms Clck speed versus edge speed - effect f signal risetime Effective perating frequency and knee frequency Current, vltage and resistance Electric fields, capacitance and dielectric cnstant Magnetic fields and inductance - self inductance n PCBs Effect f circuit cmpnents n signal wavefrm - transmissin lines Current paths n a PCB Attenuatin f signals n lines - skin effect and lss tangent Seite 2 vn 6

3 Mdule 3 - Pwer delivery Pwer requirements Cping with changing currents - induced nise Bard level and cmpnent level decupling Practical limitatins - bandwidth f capacitrs Three prblems with the traditinal apprach t decupling Expected versus actual respnse f decupling netwrks The alternative apprach t pwer delivery Flattening the impedance respnse Supplying charge - cmpnent current risetimes Pwer - grund plane resnance Summary - tw appraches t pwer delivery Mdule 4 - PCB transmissin lines Transmissin line velcity and delay Characteristic impedance Material and stackup effects Gemetry and fabricatin effects Prpagatin f a vltage step Transmissin line input impedance Reflectin frm a terminated line - different cases Impedance cntrl by line terminatin Series and parallel terminatin Mdule 5 - differential transmissin Why use differential transmissin? (1) Differential signaling Effects f equal and unequal transmissin line lengths Differential and cmmn mde currents Ruting differential tracks clse tgether Cupled lines - current, vltage and impedance (dd and even mde) Rules fr ruting differential transmissin lines Line terminatins D we need t terminate fr even mde? Why use differential transmissin? (2) Mdule 6 Crsstalk Capacitive and inductive crsstalk Dependence n edge rate Cupling factrs - slid grund plane Cupled lines and cupling mechanisms - frward and backward crsstalk Where d the cupled signals g? Near end and far end crsstalk Effect f cupled length Other cupling and grund plane effects Crsstalk frm multiple lines Crsstalk induced jitter Crsstalk cntrl in PCB design parts, planes, tracks, cnnectrs, terminatins Seite 3 vn 6

4 Mdule 7 Mdelling drivers and receivers IC device characteristics - drivers and lads, biplar and CMOS Simple equivalent circuits and mdels - device utput Real devices mdelling input, utput and I/O prts Behaviural device mdel IBIS - I/O Buffer Infrmatin Specificatin cntent and file structure Measuring and extracting I-V curves (in principle and in practice) Transient characteristics - transitin timing IBIS standards - evlutin and key pints Mdule 8 - PCB ruting tplgies Transmissin line types, nets and buses Track ruting effects -capacitive and inductive discntinuities Discntinuity effects frm crners, cnnectrs, vias and micrvias Serpentine tracks (delay equalisatin) Incident and reflected mde switching Oversht and ringing Tplgy types - branching and nn-branching, stubs, ruting cnstraints Multiple capacitance lading Clck distributin General principles fr ruting Mdule 9 - PCB structure, manufacture and measurement Layer stacking effects and principles pwer, grund and ruting layers Effects f PCB fabricatin prcess variables n high-speed designs The influence f key PCB materials parameters Measurement f transmissin line impedance TDR testing f PCB track impedance Part 2: High-speed PCB Design fr Gigabit Data Rates and EMI Cntrl Mdule 1 - What is high-speed? - Part II Trends in design and technlgy Hw d we measure and test? Time dmain scillscpe (measure signals) TDR/TDT (measure cmpnents/system path) Frequency dmain spectrum analyser (measure signals) VNA (measure cmpnents/system path) What d we measure (cmpnents/system path)? S-parameters! Cmparisn f TDR and VNA measurements Mdule 2 - Gb/s transmissin n PCBs Lessns n signal quality frm telecmmunicatins digital transmissin digital traffic multiplexing, cding and frequency translatin transmissin line cder and decder bit errr rate measurement eye diagrams signal skew and data jitter inter symbl interference Seite 4 vn 6

5 Serialiser/Deserialiser (SerDes) technlgy Gb/s technlgies Lw Vltage Differential Signalling (LVDS) Current Mde Lgic (CML) PCI Express an example f a standard (nt a technlgy) Mdule 3 - PCB materials fr high-speed design Material requirements fr high-speed PCBs Factrs: dielectric cnstant, dielectric lss, cnductr lss, surface rughness Transmissin line attenuatin due t dielectric and cnductr lss Intercnnect bandwidth limitatin due t line lss effect n signal quality PCB materials fr lwer lss enhanced epxy cmpared t FR-4 high perfrmance materials fr > 5 GHz bandwidth Embedded capacitrs and resistrs Mdule 4 - EMC Cntrl EMC cncerns Why EMC has becme a majr issue Definitins EMI mechanism, cupling paths and methds The five factrs in EMI analysis What we can cntrl in digital systems EMC guidelines Regulatry requirements Mdule 5 - Principles f EMI generatin Electrmagnetic wave prpagatin Near field and far field Time varying currents and vltages - radiatin generatin RF fields generated n a PCB Differential mde and cmmn mde currents and radiatin Mdule 6 PCB structure Pwer and grund planes - layer stacking effects 20H rule Image planes Grunding cncepts and methds t reduce cmmn mde current lps Electrical lengths -λ/20 rule System partitining - split planes Islatin and bridging techniques Mdule 7 EMC frm cmpnents t systems IC package parasitics grund bunce, mutual capacitance cupling EMI frm large heatsinks Lcalised grund planes Impact f IC technlgy drivers n EMC cntrl at cmpnent level I/O cnnectins t/frm PCB mdules Backplanes and plug-in bards RF cupling - PCB t PCB and PCB t chassis Indirect multipint grunding Backplane cnnectrs and signal ruting ESD prtectin Seite 5 vn 6

6 Summary - designing PCBs fr EMC View curse descriptin 1 (PDF) View curse descriptin 2 (PDF) Seite 6 vn 6