integrated circuits design, which are widely utilized in portable-system applications [1-3].

Transcription

1 CHAPTER 1 LOW POWER VLSI DESIGN A REVIEW Intrductry aspects and need f Lw Pwer design are discussed, VM, CM and ther circuit methds are reviewed in the perspective f Lw Pwer design. Sme imprtant cnsideratins are als discussed fr the Device Technlgy adptin in this wrk 1

2 Reducing Pwer is a phenmenal develpment which has gained imprtance with develpments f deep submicrn and nanmeter technlgies. This CHAPTER briefly intrduces the imprtance f the Analg and Current Mde design methds in a pwer cnscius envirnment. 1.1 INTRODUCTION Latest develpments in the field f VLSI Technlgy shw an increasing interest in analg circuit design. The main aim f analg integrated circuits (ICs) is t satisfy circuit specificatins thrugh circuit architectures with the required perfrmance. They can be used either as stand-alne tplgies r cnnected t the digital part t implement mixed analg-digital functins, utilized in a wide field f applicatins. Thugh numerus researchers predicted a reduced utilizatin f analg architectures and an increased develpment f the digital cunterpart, analg circuitry cntinues t be a necessary part f the technlgy. In fact, analg circuits are needed in many VLSI systems such as filters, D/A and A/D cnverters, vltage cmparatrs, current and vltage amplifiers, Neurmrphic and artificial systems by develping chips and systems that prcess infrmatin cllectively using predminantly analg circuits, t emulate natural signal prcessing, neural cmputatinal systems and bilgically inspired prcessing systems etc, [29]. Mrever, the recent trend twards miniaturizatin has given a strng and decisive bst t the design f lw-vltage lw-pwer (LV LP) analg 2

3 integrated circuits design, which are widely utilized in prtable-system applicatins [1-3]. During the last decades lw-vltage/lw-pwer applicatins are becming mre and mre imprtant because f the increasing prtable electrnics market. The emerging rush t the mbile cmmunicatins including vice, picture, and data transfer and the need f mbile cmputers which have almst the same perfrmance as their immbile cunterparts are advancing the cntinuus imprvement f lw-pwer high-perfrmance integrated circuits. A subscriber unit f a mbile phne, fr example, spends typically mst f its time in the stand-by mde, s that its stand-by pwer must be kept belw a specified value t maximize the battery lifetime. On the ther hand, when a cmmunicatin takes place, the unit must perfrm high speed cmputatins; it will de-cmpress the incming signal and cmpress the utging signal. Due t the fact that the energy density f cmmnly used batteries is limited, they have becme a bttleneck in reducing the weight f prtable devices. Therefre, saving weight can nly be achieved by reducing the ttal pwer cnsumptin. This is cntrary t the fast grwing number f devices n a chip due t the increasing system cmplexity. Therefre, the pwer prblem has t be slved n the transistr and circuit levels. Ultra Large Scale Integratin (ULSI) CMOS technlgy is perfectly suitable fr the requirements f prtable electrnics due t its scalability and lw pwer cnsumptin. Varius new MOS device architectures have been recently reprted with channel lengths dwn t the nanmeter range, but n general investigatin 3

4 has prven that ne f these structures is ptimal t meet a certain perfrmance gal. System requirements fr prtable electrnics are best met by MOS circuits featuring a restricted drain-surce leakage current f the single transistrs and highest pssible switching speed. T accmplish this, the devices have t be ptimized fr these specificatins, s that the prttypes and building blcks are ptimum in perfrmance. This has led t the implementatin f new design circuit strategies in lw-cst CMOS technlgy. Infrmatin prcessing can be dne n nde vltages (VM r vltage mde prcessing) r in terms f branch currents (CM r current mde prcessing). VM techniques received much wider attentin whereas, attentin t the CM techniques started just a few decades earlier [4,5]. 1.2 VOLTAGE MODE TECHNOLOGY : A REVIEW There were a few reasns why VM dminated [13] (i) (ii) A nde vltage is easy t measure withut mdifying the tplgy and peratin whereas the measurement f the branch current is less cnvenient t measure and requires a change f circuit cnfiguratin r additinal circuitry. The infinite impedance lking int the gate f MOS transistrs makes these devices an ideal chice fr VM circuits, especially in cascade cnfiguratins 4

5 (iii) (iv) (v) (vi) Easy t btain a high vltage gain f VM circuits using techniques such as cascde and regulated cascde. Higher biasing vltages were nt s critical as f tday. Switching nise was nt a critical issue with the presence f a high supply vltage. Lw speed peratins did nt cncern the charge and discharge f ndal capacitrs ver a lng perid f time. (vii) VM is a bit histric. It tk ff first and nw psses a huge knwledge bank. CM is the latest develpment. (viii) Feedback is easy t handle in VM. The utput signal can be used fr lad and feedback simultaneusly. (ix) In VM systems, Gain and bandwidth are at dds. S a trade ff is necessary. (x) (xi) In VM, the design cmpnents are ften required t be linear because they cntrl vltage and current at varius ndes f the circuit. Parasitic capacitances sme times turn ut treacherus. The clck feed thrugh and charge sharing between intermediate ndes are cmmn prblems f the VM dynamic circuits. (xii) Design matrices are Lw Vltage, Lw Pwer and bandwidth. It is extremely difficult t achieve all three in VM systems. A cmprmise is a slutin. Similar situatin d ccur in CM systems, but there the cmprmise is nt s tight as is in VM systems. The CMRR is ne f the majr achievements f the VM systems. OPAMP emerged as a main design blck in the VM analg circuit applicatins and dminated the market. The situatin is nwadays changing. The aggressive device 5

6 scaling has serius cncerns regarding the perfrmance f VM circuits rather than the CM circuits. 1.3 CURRENT MODE - AN EMERGING WAY OF THINKING Sme f the reasns t chse CM technique may be as fllwing: 1. Device scaling als scales biasing and threshld vltages dwn, causing a reductin in signal swing and increased delay. But the CM circuits are practically immune t such effects. 2. Their ability t vercme the limitatin f a cnstant gain-bandwidth prduct [13] 3. The trade-ff between speed and bandwidth, t imprve perfrmance in terms f a. Lw-vltage characteristics b. Slew-rate and bandwidth. [6,10,11] 4. CM des nt need High Vltage Gain, s high perfrmance amplifiers are nt needed. 5. CM circuits d nt need high precisin passive cmpnents, therefre they can be designed almst entirely with MOSFETs. This makes the CM circuits quite cmpatible with typical digital wrld. 6. The current-mde apprach is equally a pwerful technique. All the analg IC functins, which were traditinally been designed in VM can als be implemented in CM. 6

7 7. The CM technique has the capability t imprve Bandwidth. This imprvement is different frm the imprvement f a vltage amplifier as in the VM case, BW imprves n the cst f Gain, whereas in case f CM, the imprvement is a bit mre general, i.e. the BW imprves withut much gain lss. This pint can be demnstrated as belw. 8. CM technique is fully cmpatible with the existing VM. 1.4 CM/VM : AN OVERVIEW Design peple try t define the Vltage Mde (VM) and Current Mde (CM) as tw fulfledged design methdlgies, but till tday, it is hard t demarcate ne frm the ther. Hwever, this way f thinking has generated sme very imprtant design building blcks [127], and has refrmed the analg design a lt. In this sectin the VM and CM amplifiers are cnsidered. The mde f the amplifier can be defined n the basis f the principal signals n the way they cntrl it s peratin. Generally I-V characteristic is nt always linear, therefre cnsidering the mde is als imprtant while designing the amplifier. A VM amplifier may nt wrk satisfactrily under CM scheme OPAMP BASED VM AMPLIFIER - Vin + Vut R 2 R 1 FIGURE 1.1: OPAMP based VM Amplifier 7

8 Analysis f the circuit f Fig.1.1 is presented belw. Assume A pen lp gain f the OPAMP, A pen lp dc gain, A(s) single dminant ple mdel f the OPAMP, β vltage signal feedback factr, s = jω and ω the dminant ple frequency [19]. s Laplace dmain representatin, V V ut in A = (1.1) 1 + βa R = R + R 1 β (1.2) A s 1 2 A s 1+ ω ( ) = (1.3) V V ut in 1+ βa = (1.4) s 1+ ω (1 + βa ) A OPAMP BASED CM AMPLIFIER + I ut I in R 2 R 1 FIGURE 1.2: OPAMP based CM Amplifier 8

9 With same assumptins as cnsidered in the abve VM amplifier, circuit analysis cncludes the fllwing results [19]: I I in R2 = K = (1 ) (1.5) R ut + 1 A A s 1+ ω ( s) = (1.6) R2 R1 K 1 + s 1 + ω (1 + A ) (1.7) Equatins 1.4 and 1.7 shw that the gain f the abve VM and CM amplifiers mdify the system frequency ω 1+ βa ) ; β < 1 and ω 1+ A ). Clearly the secnd ( ( case shws an imprvement in bth system frequency and gain magnitude. The frequency respnses f the VM and CM amplifiers are given in Figure 1.3. The feedback netwrk is used same fr the purpse f direct cmparisn f their characteristics FREQUENCY RESPONSE PLOTS OF VM/CM AMPLIFIERS It is evident frm figure 1.3 that the feedback in VM amplifier enhances dminant ple frequency by the feedback factr but with gain reductin by the same feedback factr. In CM amplifier, the gain is nt large, but whatever the gain, it stays almst same, hwever, the dminant ple frequency is enhanced by the feedback factr. A well-knwn current-mde circuit is the Current-Feedback Operatinal Amplifier (CFOA) [23]. The CFOA shws a cnstant bandwidth with respect t 9

10 the clsed-lp gain and a very high slew-rate cmpared t the traditinal OPAMP. This high slew rate makes the CFOA, a circuit f primary imprtance in the design f mdern LV LP ICs [23]. The first stage f CFOA is the currentcnveyr (CC). Therefre the CC can be cnsidered the basic CM building blck. Open Lp Gain Ch. CM Amplifier VM Amplifier FIGURE 1.3: Frequency Respnse f VM/CM Amplifier [19]. The quest fr active device, actually starts with the prpsitin by Tellegin, and was later frmalized by Carlin with the intrductin f the Nullr - Nratr cncept. OPAMP and the CCII are the basic active devices. Nullr - Nratr apprach realizes undefined impedance levels, therefre, realizatin fr sensible transfer characteristics, feedback is needed depending upn the type f functin realized between the input and utput variables. Analg amplifiers are classified as vltage cntrlled vltage surce (VCVS), vltage cntrlled current surce (VCCS), current cntrlled vltage surce (CCVS) and current cntrlled current surce (CCCS) as they realize the gains in terms f vltage rati, trans-cnductance, trans-resistance and current rati respectively. Thus OPAMP is a vltage amplifier and the OTA is the trans- 10

11 cnductance amplifier. Again as usual, the feedback circuit can sample vltage utput r current utput and feeds back vltage r current signal input, therefre, ttal sixteen pssibilities arise, ut f which, we can cnsider fur pssibilities f enhanced impedance. By the term enhanced it is meant that the impedance decreases fr vltage utput and increases fr a current utput, and like that [19]. Frm Figure 1.3, it is als wrth nting that the GBW prduct is n mre a cnstant, in fact the GBW enhances as shwn in the sparsely dashed line. Fr LV- LP design cnstraints, trans-resistance feedback cnfiguratin is fund mre suitable than thers [12,19,24]. Since the transresistance feedback has the effect t decrease the input and the utput impedance levels at the ends f the resistr f Fig.1.5, it is pssible t define, fr the blck depicted in Fig.1.5, a high impedance (vltage) input terminal (1), a lw impedance (current) input terminal (2), a high impedance (current) utput terminal (3) and a lw impedance (vltage) utput terminal (4). This slutin presents all the pssible cmbinatins f lw and high impedances fr bth input and utput terminals, s this is really a generic blck. V + in + g m I ut V + in + g m Iut I = g ut m V in FIGURE 1.4: Transcnductance Amplifier (Ideal Z i and Z are ) It is als knwn as an OFC with all nde vltages and nde currents defined [19]. FIGURE 1.5: A CCII derived frm an OFC with a designated feedback. Als it is similar t a Transcnductance Amplifier with Transresistance feedback [19]. This circuit f Fig.1.5 is the current cnveyr, and if the utput impedance is adjusted thrugh a vltage buffer, this circuit results int a CFOA. It is a hybrid 11

12 amplifier because it has different impedance levels fr different types f signals. It is als referred in literature as flating cnveyr r peratinal flating cnveyr [24]. The OFC is a versatile and is a quite useful device and can be a part f the CFOA r can be transfrmed int a CCII. In fact a CCII can be natural sequel f OFC f the applied feedback [19]. This apparently is the reasn why the design f CCCII is cnsidered ver here in this wrk. The usefulness f CMOS current-mde circuits in cmbating the difficulties arising frm the reductin f the supply vltage and the increase in the peratin speed has received an increasing attentin bth frm industry and academia recently Therefre, the CM techniques have started taking a lead [6-9] in the design. 1.5 TECHNOLOGY ADOPTED IN THIS WORK There are varius fabricatin technlgies prevailing fr the fabricatin f CMOS. These are in general the Bulk Silicn, Gallium Arsanide Ga X As y and Silicn n Insulatr SOI etc. Ga X As y is a specific cmpsitin which is used fr sme specialized high speed applicatins nly. This can nt be cnsidered as a general purpse material. Bulk silicn and SOI are rivals. Bulk devices psses varius advantages like easy t design, fabricatin and implement, lwest pwer delay prduct, lw cst, general purpse, adaptable t any further imprvement and have practically favred scaling up t the deep submicrn and nanmater scales [131]. SOI devices need sme extra masks, therefre are cstlier and have sme serius disadvantages. SOI devices have their bulk flating and a parasitic BJT, which 12

13 substantially distrts the perfrmance [108,110]. The Flating Bdy Effect can be relieved by using a fully depleted SOI, but this SOI d nt supprt scaling. Furthermre, due t the presence f insulating xide layer, drain field lines interact with the surce leaving the surce influenced by the drain [110]. Advanced SOI can supprt aggressive scaling, but this requires specialized materials and prcesses and pens new challenges [96]. Therefre Bulk Silicn is still cnsidered a standard in IC fabricatin and is cnsidered here as the base technlgy thrugh ut this wrk. 1.6 LOW POWER DESIGN The need fr lw pwer design is an age ld necessity. Develpment f the slid state transistr itself is an enthusiastic step twards lw pwer. Biasing supplies fr slid-state circuits, fr crude transistrs f thse days, were reduced t few tens f vlts frm hundreds f vlts required fr similar tube based circuits. With the advancement f the technlgy the necessity fr reducing pwer grew greater. The pwer cnsideratin grew s great that it acquired a psitin as a design parameter alng with the ther tw parameters the speed and chip area, each ne having a bearing n the thers [62]. FIGURE 1.6: Triangle f Design Parameters Reductin f pwer is tackled at every pssible level, right frm the device level up t the system level. Advancement f technlgy brings in smaller devices that wuld need lwer biasing. Further, a smaller device has lwer parasites, 13

14 especially capacitance, which usually charge and discharge with every circuit transitin and dissipate a reduced energy per cycle. In literature, ne can see the terms like lw pwer design and pwer aware design. lw pwer design refers t reducing pwer f the design withut an emphasis n perfrmance, whereas pwer aware design refers t reducing the verall pwer with due cnsideratin t the perfrmance as well [93] DEVICE LEVEL SOLUTIONS Use f advanced devices, pwer and speed usually imprve but prblems like leakage aggravate with each new technlgy. The use f SOI CMOS is prpsed as a slutin fr perfrmance, but SOI devices have sme inherent prblems which mar their general purpse usage as a standard technlgy. Refer sectin 1.5. Nan devices like Carbn Nan Tubes (CNT) are prpsed in fabricatin f FETs, called CNTFETs [105]. These CNTFETs are expected t achieve extreme perfrmance, but their fabricatin is still a prblem in itself. Use f Devices like multigate FETs(FinFETs) and Flating Gate FETs [106]. These devices address sme f the prblems f the advanced technlgies very well, but invke sme reliability cncerns [105] CIRCUIT LEVEL SOLUTIONS In Digital Technlgy, a wide spectrum f methds is available fr alleviating the prblems in deep submicrn and nanmeter technlgies, but Analg is an establishing field and therefre LV and LP are develping techniques. 14

15 Large biasing is usually needed fr large swing, but deeply scaled devices may nt affrd it. A thicker gate xide is required t suppress gate leakage, but it increases V TH and is expected t slw dwn the speed [105]. Scaled V DD needs scaled V TH, t maintain high channel current, but needs extra fabricatin steps, hence mre cst and lnger turn arund time [107]. Techniques based n the Devices like multigate FETs(FinFETs) and Flating Gate FETs (FGFET) are quite prmising. FGFETs can be prgrammed by charge string, t perate at variable V TH. Reliability is a majr prblem [105]. Ultra LV circuits can be achieved by using switched capacitance (SC) technique. This technique is hard t implement in deep submicrn as it needs clck bsting in SC circuits t achieve accurate sampling [105]. Current mde circuits are fund mre suitable as they are usually lesser vltage dependent, and shw n such limitatins. Pwer can be drastically reduced withut any perfrmance deteriratin [6,7,19]. Pwer reductin mechanism in analg circuits is entirely different frm what required in digital circuits. Varius LV and LP techniques are develping that can suite the needs f analg integrated circuits. MOS current is quadratic with vltage, therefre it appears mre apprpriate t handle circuits in terms f current signals than the crrespnding vltage signals. CM techniques are thus expected t supprt pwer aware designing f the Analg VLSI. 15