EE 311: Electrical Engineering Junior Lab Phase Locked Loop

Transcription

1 Backgrund Thery EE 311: Electrical Engineering Junir Lab Phase Lcked Lp A phase lcked lp is a cntrlled scillatr whse instantaneus frequency is dynamically adjusted thrugh multiplicative feedback and lw pass filtering. The simplified PLL cnfiguratin that will be used fr analysis purpses is shwn in Figure 1. There are three fundamental cmpnents: the vltagecntrlled scillatr (VCO), the phase detectr (PD), and the lp filter with amplifier. ω (t The vltage-cntrlled scillatr (VCO) is an scillatr whse instantaneus frequency ) is varied by the cntrl vltage v c (t) accrding t the fllwing relatin ω () t = ω + K v (t) c c c (1) The wavefrm prduced by the VCO can be a square wave, a sine wave, r ne f many ther peridic signals. Fr the NE565 PLL chip, it is a square wave. The cnstant ω c is called the center frequency f the VCO. Frm (1), this is simply the free running frequency f the VCO when the cntrl vltage, v c, is zer. The cnstant Kc is called the VCO gain. It is a measure f the sensitivity f the VCO frequency t variatins in the cntrl vltage. Fr the NE565 PLL chip, the VCO center frequency can be "tuned" thrugh the selectin f the external discrete cmpnents R 1 and C 1 cnnected t pins 8 and 9 respectively. In this case, 0.6π ω c = (2) R C 1 1 The phase detectr (PD) is a tw input/ne utput circuit having the fllwing prperty: if the tw inputs are peridic and have the same perid, then the dc cmpnent f the PD utput shuld be apprximately prprtinal t the phase angle between the tw peridic inputs. A fur quadrant analg multiplier functins as the PD. Indeed, if the input v i is a sine wave and the VCO utput v is any peridic wavefrm, then: x dc K d sin( θ θ ) = (3) i

2 where x dc dentes the average value r dc cmpnent f the PD utput, x (t). Similarly, i v i (t and VCO utput signal v (t) θ and represent the phase angles f the input signal ), respectively. Finally, the "cnstant" K d is called the PD gain. It is a measure f the sensitivity f the PD utput t variatins in the phase angle between the inputs. In general, the PD gain will depend upn the amplitude and shape f the tw peridic inputs t the PD. The amplitude and the shape f v (t) is typically fixed, while the amplitude f v i (t) may vary. If the amplitude f v i (t) is sufficiently large that saturatin takes place, then the PD gain K d is cnstant. Fr the NE565 PLL chip, when the amplitude f v i (t) is 200 mv peak-t-peak r greater, K d is cnstant and equal t abut 1.4 / π vlts/rad. θ

3 When the phase angle between the PD inputs is small, x dc is a linear functin f the phase angle since sin( θi θ ) is apprximately equal t ( θi θ ) under these cnditins. There are additinal circuits that can als be used as phase detectrs and nt all f them yield a sinusidal phase angle characteristic as described in (3). Fr example, if bth v i (t) and v (t) are rectangular wavefrms scillating between tw lgic levels, then an exclusive-or circuit can be used as a phase detectr. In this case, a triangular phase angle characteristic results. Alternatively, if the VCO utput is a rectangular wavefrm, then a "multiplier" type PD can be realized with a switching circuit which turns ff when the VCO utput is lw and turns n when it is high. The lp filter including the amplifier is the third fundamental cmpnent f the PLL. The filter is usually realized with external discrete cmpnents. In this way, the PLL circuit can be readily tuned. The lp filter is typically a passive lw pass filter such as a RC lag filter, as shwn in Figure 2. In this case, the vltage rati transfer functin G(s) is given by: Vc() s A Gs () = = X() s ( 1+ τs) where τ = R C (4) 2 2 The purpse f the lp filter is t extract the dc cmpnent f the PD utput x(t). Since the PD is a mixer, it's utput will typically be peridic, and will cntain frequencies crrespnding t the sums and differences f the frequencies present in v i (t) and v (t). During nrmal peratin, the lwest frequency present, excluding dc, in the PD utput will be 2ω i, where ω i is the frequency f v i (t). Thus, the 3-db cutff frequency f the lw-pass filter shuld be cnsiderably belw 2ω i s that the filter utput has lw ripple when in phase lck. f equals the utput frequency f and the filter v c (t), is cnstant. If the input frequency increases slightly, the phase angle difference When the circuit is in phase lck, the input frequency i utput vltage, θi θ will increase with time. Frm (3), the dc utput f the phase detectr will then increase, causing the dc utput vltage f the filter t increase. This crrespnds t an increase in the vltage input t the VCO, increasing the VCO utput frequency, i.e., bringing it up t meet the input frequency. The phase angle stabilizes at a new equilibrium, and phase lck is maintained. The new value f θi θ yields a larger cnstant utput frm the phase detectr, which in turn drives the VCO at a higher frequency, i.e., further frm the center frequency. A similar adjustment takes place when the input frequency is slightly belw the VCO frequency. In phase lck, the cntrl circuit, i.e., the PD, amplifier, and filter, is cntinuusly adjusting the VCO frequency t equal the input frequency. The ability t maintain phase lck is gverned by (3). T maintain stability, the VCO frequency must increase when θi θ increases. Frm (3), hwever, this will happen nly when θi θ is less than 90, r cnversely, θi θ decreases nly when the difference is less than 90. By mnitring the cntrl vltage fed back t the VCO, we can explit this serving feature t demdulate FM signals. Suppse the input signal, v i (t), is a pure sinusid f the frm: vi( t) Vm sin( ωit) = (5) V m is sufficiently large such that the PD gain K d is cnstant. where it is assumed that the amplitude Next, suppse that the lw-pass filter is an ideal filter with cutff frequency belw 2ω i. Finally, suppse

4 the PLL is already in the lcked cnditin. This is tantamunt t saying that ω = ω θ ( t ) i θ ( t) = β, where β is the stable phase angle between v i (t) and v (t) i and that. In this case, we can use (1), (3) and (4) t shw that the general relatin fr the lcked PLL reduces t: ω (t) ω + K K AG(0)sin( β ) i = (6) c c d In rder t simplify the ntatin, let K v dente the dc gain, r lp gain, f the PLL, and let ωi dente the frequency variatin between ω i and the VCO center frequency ω c, as shwn: K v = KcKdA (7a) ωi = ωi ωc (7b) Several useful characteristics f the PLL can nw be specified in terms f the parameters Rewriting (6) in terms f K v and ωi, we btain: K v and ωi. ωi ( t) = K vg( 0)sin( β ) (8) The PLL can achieve the lcked cnditin if and nly if there is a phase angle β that satisfies (8). Since sin(β ) is restricted t be between -1 and +1, (8) puts a bund n the allwable frequency variatin ωi. In particular, ω i K v G(0) is needed fr (8) t have a slutin. This specifies the lck range f the PLL, i.e., the range f frequencies ver which a PLL will remain lcked. T determine the lck range experimentally, ne culd first apply a peridic input f sufficient amplitude and f frequency ω i = ωc t attain a phase lck. Then the input frequency ω i can be slwly increased/decreased until the lcked cnditin is lst. In this way, the lck limits can be measured. Frm (7) and (8), the lck range in terms f ω c and K v is given by: () ω lck = ω c ± K v G 0 (9) Fr the NE565 PLL chip, the lp gain K v depends n bth the center frequency ω c and the differential supply vltage V cc, i.e., the 20 vlts applied between pins 10 and 1 f the NE565. The fllwing apprximatin is applicable t the NE565 assuming a passive lp filter: 8 ω lck ωc 1 ± (10) Vcc The lck range specifies the frequency limits beynd which a lcked lp will becme unlcked. Of mre practical interest is the ppsite cnditin, the phase lcking f an initially unlcked lp. The range f frequencies ver which an initially unlcked lp will always becme lcked is called the capture range f the PLL. Derivatin f an expressin fr the capture range is quite invlved since it requires the slutin f an implicit algebraic expressin which depends n the frequency respnse f the lp filter. Hwever, a simple apprximatin can be used under certain cnditins. If the time cnstant τ assciated with the ple f the lp filter satisfies the inequality 2τ ωlck ωc >> 1, then the apprximate capture range is

5 1 ωlck ωc 2 cap c ω ω ± (11) τ Thus by varying the ple lcatin f the lp filter subject t the cnstraint 2τ ωlck ωc >> 1, ne can exercise sme cntrl ver the size f the capture range. Hwever, the capture range can never exceed the lck range (this fllws directly frm it's definitin). In rder t determine the capture range experimentally, ne must start ut with an unlcked lp and very slwly increase r decrease the input in such a way that it appraches the center frequency f the VCO. The instant the lp becmes lcked, the bundary f the capture range has been crssed. Nte: The PLL may als capture harmnic frequencies f the input wavefrm. As the VCO utput f this particular IC is rich in harmnics, additinal lck ranges can be expected. Preliminary Lab Questins: In Figure 2, assume R1=4.3khm, R2=3.6khm, R3=6.2khm, R4=R5=620hms, and C3=0.001ufd. Nte that R2 is within the NE PLL circuits are used in a wide variety f industrial applicatins. Describe three r mre practical applicatins f PLL circuits. Use blck diagrams/schematics as apprpriate t illustrate the particulars f each applicatin. 2. Prepare a circuit diagram that shws the physical layut yu will use n the prt-bard. Label all cmpnents and number all pins. Indicate hw the functin generatr, scillscpe, and pwer supply will be cnnected. 3. With the input signal n scillscpe channel 1, and the VCO signal n scillscpe channel 2, describe the expected traces when (a) the PLL is in lcked mde and (b) the PLL is in the unlcked mde. Assume that the scillscpe is triggered frm the channel 1 signal. 4. Cmpute a value fr C1 that yields a VCO center frequency f determine the center frequency experimentally. f c = 50khz. Indicate hw yu will 5. Cmpute the theretical lck range f the PLL given a supply vltage f +10 vlts and a center frequency f 50 khz. Indicate precisely hw yu will determine the lck range experimentally. C that shuld yield a capture range f f c ± 5khz 6. Cmpute a value fr 2 will determine the capture range experimentally.. Indicate precisely hw yu v is a square wave with frequency f and angle f =. Repeat the calculatin fr f i = 3f 7. *Cmpute the dc utput f the PD when input signal is a sine wave f frequency i f. (Hint: cnsider the Furier series f a square wave. What is the dc value f the prduct f tw different frequencies?) *This part f the pre-lab is ptinal, fr extra credit. θ, and the

6 Lab Prcedure: 1. Cnstruct the circuit shwn in Figure 2. D nt apply pwer until yu have verified that the pwer supply is adjusted t +10 vlts. It is easy t burn ut this chip! Since stray capacitance and inductance can als ruin this experiment, use shrt leads and a simple physical layut f cmpnents n the prt-bard. Twist lng pairs f leads tgether if yu need them t reach instruments. 2. Using the frequency cunter, adjust the decade capacitr 1 What is C 1? C until the center frequency c f is 50khz. 3. Adjust the functin generatr until v i (the utput f the vltage divider) is a 200 mv peak-t-peak sine wave. Display v i n channel 1 f the scillscpe, and display the VCO utput n channel 2. Trigger frm channel 1 fr the mment. This shuld result in a 90 degree phase angle between the tw displayed wavefrms when the functin generatr is adjusted t 50 khz. Measure the lck range assciated with the 200 mv input. Reduce the amplitude f the sine wave v i t 20 mv peak-t-peak. Repeat the lck range measurement. If the lck range is different, indicate why. Explain, in detail, the prcedure yu use t measure the lck range. Describe what yu see n the scillscpe when yu lse phase lck, and explain hw this relates t what is actually happening in the circuit. Describe what happens t the phase angle between v i and v as yu apprach the edges f the lck range. Explain why this happens.

7 4. Reset the amplitude f the sine wave v i t 200 mv peak-t-peak. Nw measure the capture range f the PLL. Nte hw the capture range is smaller than the lck range. Hw des yur prcedure fr determining the capture range differ frm the prcedure yu used t measure the lck range? 5. This part f the experiment investigates the use f a PLL as a frequency divider. Use a 200 mv peakt-peak sine wave fr v i. Measure the lck ranges when the input frequency is three times and five times the VCO frequency. Why are there n (significant) lck ranges when the input frequency is an even multiple f the VCO frequency? (Hint: Think abut the Furier series f a square wave) 6. This part f the experiment investigates the use f a PLL as a frequency multiplier. The key here is t divide the VCO frequency with a mdul-n cunter. The VCO will then have t run N times as fast as v i in rder t maintain the phase lcked cnditin. The simplest example invlves a flip-flp cnfigured as a mdul 2 cunter, as shwn in Figure 3. Wire this cunter and insert it between the VCO utput (pin 4) and the PD input (pin 5) f the PLL. Use a 200 mv peak-t-peak sine wave fr v i. Measure the lck range when the input frequency is ne half the VCO center frequency. 7. This part f the experiment investigates the use f a PLL as a general frequency changer. With the circuit hked up as in step 6, measure the lck range when the input frequency is 3.2 the VCO center frequency. What relatinship exists between the surce frequency and the VCO frequency in this case? References: 1. F.M. Gardner, Phaselck techniques (2 nd ed.), Wiley (1979) 2. NE565 (LM565) Spec sheet. Available n the curse website r frm ne f the manufacturers ( fr example). Equipment: Item Number Size/type Oscillscpe 1 bench functin generatr 1 bench DC pwer supply 1 +10v Prt-bard 1 Resistrs hm, 6.2K, 4.3K IC's 2 NE565, 7474 decade capacitr Capacitrs uf, calculated Bx 2 wires, leads Last revisin: /jjc