A biphase shift keying (BPSK), direct sequence, spread spectrum modem for Petite Amateur Navy Satellite (PANSAT).

Transcription

1 Calhun: The NPS Institutinal Archive Theses and Dissertatins Thesis Cllectin A biphase shift keying (BPSK), direct sequence, spread spectrum mdem fr Petite Amateur Navy Satellite (PANSAT). Fritz, Thmas M. Mnterey, Califrnia. Naval Pstgraduate Schl

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3 DUDLEY KNOX LIBRARY NAVAL POSTGRADUATE SCHOOI MONTEREY CA

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8 UNCLASSIFIED SECURITY CLASSIFICATION OF THIS PAGE 1a REPORT SECURITY CLASSIFICATION UNCLASSIFIED 2a 2b SECURITY CLASSIFICATION AUTHORITY DECLASSIFICATION /DOWNGRADING SCHEDULE REPORT DOCUMENTATION PAGE lb RESTRICTIVE MARKINGS 3 DISTRIBUTION/ AVAILABILITY OF REPORT Apprved fr public release; distributin is unlimited 4 PERFORMING ORGANIZATION REPORT NUMBER(S) 5 MONITORING ORGANIZATION REPORT NUMBER(S) Frm Apprved OMB N a NAME OF PERFORMING ORGANIZATION Naval Pstgraduate Schl 6c ADDRESS (City, State, and ZIP Cde) 6b OFFICE SYMBOL (If applicable) EC la NAME OF MONITORING ORGANIZATION Naval Pstgraduate Schl 7b ADDRESS (City, State, and ZIP Cde) Mnterey, CA a. NAME OF FUNDING / SPONSORING ORGANIZATION ib OFFICE SYMBOL (If applicable) Mnterey, CA PROCUREMENT INSTRUMENT IDENTIFICATION NUMBER 8c. ADDRESS (City, State, and ZIP Cde) 10 SOURCE OF FUNDING NUMBERS PROGRAM PROJECT TASK ELEMENT NO NO NO WORK UNIT ACCESSION NO 11 TITLE (Include Security Classificatin) A BIPHASE SHIFT KEYING ( BPSK ), DIRECT SEQUENCE, SPREAD SPECTRUM MODEM FOR PETITE AMATEUR NAVY SATELLITE (PANSAT) 12 PERSONAL AUTHOR(S) FRITZ, 13a TYPE OF REPORT Thmas M 13b TIME COVERED FROM TO 14 DATE OF REPORT (Year, Mnth, Day) 15 PAGE COUN1 80 Master's Thesis 1992 December 16 supplementary ntatin The views expressed in this thesis are thse f the authr and d nt reflect the fficial plicy r psitin f the Department f Defense r the US Gvernment. 17 COSATI CODES FIELD GROUP SUB-GROUP 18 SUBJECT TERMS (Cntinue n reverse if necessary and identify by blck number) Direct Sequence; Spread Spectrum; Biphase Shift Keying (BPSK) fr Petite Amateur Navy Satellite ( PANSAT ) 19 ABSTRACT (Cntinue n reverse if necessary and identify by blck number) The develpment f a biphase shift keying (BPSK), direct sequence, spread spectrum mdem is cnducted fr the purpse f develping a prttype design t be implemented in Petite Amateur navy Satellite (PANSAT). The design discussin includes the hardware used in the functinal realizatin f a wrking design. The design itself, encmpasses selectin f cmpnents, and demnstrates thrugh circuit diagrams and wavefrms prduced that the preliminary peratinal characteristics f a spread spectrum BPSK mdulatin scheme fr PANSAT have been achieved. Limited perfrmance analysis is cnducted thrugh IF lp-back testing and analyzes the demdulatr utput wavefrms prviding the prf f cncept fr the design. The develpment f the final versin perating at the specified radi frequency (RF) is nt cnducted. 20 DISTRIBUTION /AVAILABILITY OF ABSTRACT UNCLASSIFIED/UNLIMITED SAME AS RPT D DTIC USERS NAME OF RESPONSIBLE INDIVIDUAL 21 ABSTRACT SECURITY CLASSIFICATION UNCLASSIFIED 22a 22b TELEPHONE (Include Area Cde) HA, Tri T DDFrm JUN 86 Previus editins are bslete S/N 0102-LF c OFFICE SYMBOL EC /Ha SECURITY CLASSIFICATION OF THIS PAGE UNCLASSIFIED TPAHA7Q

9 Apprved fr public release; distributin is unlimited A BIPHASE SHIFT KEYING (BSPK), DIRECT SEQUENCE, SPREAD SPECTRUM MODEM FOR PETITE AMATEUR NAVY SATELLITE (PANSAT) by Thmas M. Fritz Lieutenant, United States Navy B.S., United States Naval Academy, 1985 Submitted in partial fulfillment f the requirements fr the degree f MASTER OF SCIENCE IN ELECTRICAL ENGINEERING frm the NAVAL POSTGRADUATE SCHOOL- December 1992 // A /O _ /

10 ABSTRACT The develpment f a bi-phase shift keying (BPSK), direct sequence, spread spectrum mdem is cnducted fr the purpse f creating a prttype design t be implemented in the Petite Amateur Navy Satellite (PANSAT). The design discussin includes the hardware used in the functinal realizatin f a wrking design. The design itself encmpasses selectin f cmpnents and demnstrates (thrugh circuit diagrams and wavefrms prduced) that the preliminary peratinal characteristics f a spread spectrum BPSK mdulatin scheme fr PANSAT have been achieved. Limited perfrmance analysis is cnducted thrugh IF lp-back testing and prvides the intermediate and utput demdulatr wavefrms. The develpment f the final versin perating at the specified radi frequency (RF) is nt cnducted, but the discussin prvides prf f cncept. 111

11 cl TABLE OF CONTENTS I. INTRODUCTION 1 A. GENERAL 1 B. TECHNICAL BACKGROUND 1 H. MODEM DESIGN AND OPERATION 3 A. SYSTEM OVERVIEW 3 1. Mdulatin 3 2. Demdulatin 4 B. DIVISION CHAIN 8 1. Mdulatr 8 2. Demdulatr 9 C. PN GENERATOR General Technical 11 a. Mdulatin PN Sequence Generatin 11 b. Demdulatin PN Sequence Generatin 16 D. FUNCTION GENERATOR General Technical 18 E. MIXERS General Technical 22 a. Mdulatin 22 b. Demdulatin 28 F. BAND-PASS FILTERS General Technical 35 G. VCO FEEDBACK CONTROL General Technical 36 H. DATA CONDITIONING 41 IV

12 DUDLEY KNOX LIBRARY NAVAL POSTGRADUATE SCHOOI MONTEREY CA HI. CONCLUSIONS 45 A. GENERAL 45 B. TECHNICAL Circuit Sensitivity VCO Cntrl Pwer Cnsumptin 46 APPENDIX A. FUNCTIONAL BLOCK DIAGRAMS 48 APPENDIX B. CIRCUIT DIAGRAMS 51 MODEM BILL OF MATERIALS 62 APPENDIX C. FOURTH ORDER BAND PASS FILTER CONSTRUCTION AND PERFORMANCE 65 LIST OF REFERENCES 70 DISTRIBUTION LIST 71

13 :. LIST OF FIGURES Figure 2. 1 Figure 2.3: Figure 2.4: Figure 2.5: Figure 2.6: Figure 2.7: Figure 2.8a: Figure 2.8b: Figure 2.9a: Figure 2.9b: Figure 2.10a: Figure 2.10b: Figure 2.11: Figure 2.12: Figure 2.13a: Figure 2.13b: Figure 2.14a: Figure 2.14b: Figure 2.15: Mdulatr functinal blck diagram 3 Crystal scillatr utput 12 Tp: PN generatr clck. Bttm: Functin generatr clck...14 Tp: PN generatr clck (153.6 khz), 2 v/div. Bttm: PN sequence used fr spreading, 5 v/div 15 Tp: Early PN sequence. Bttm: Late PN sequence 17 Tp: khz Square wave; LM31 IP utput. Bttm: Triangle wave utput f LM318N integratr 19 Tp: Triangle wave fllwing vltage divider. Bttm: khz Sinusidal utput 20 Tp: Sinusid frm functin generatr sectin. Middle: PN encded data utput frm cmparatr. Bttm: Spread spectrum BPSK utput at khz 24 Frequency spectrum fr the sinusidal carrier(unmdulated) taken frm the utput f the functin generatr sectin 25 Spectrum fr 1200 bps BPSK mdulated carrier. A square wave at 600 Hz is used as the data stream 26 Spectrum fr the PN encded BPSK 27 Main lbe frequency spectrum f the transmitted signal with (sin(x)/ x) 2 nise distributin 29 Tp: PN sequence used in mdulatin. Middle: Punctual PN sequence frm demdulatr. Bttm: Output f the narrw band, band-pass filter 30 Tp: PN sequence used in mdulatin. Middle: Punctual PN sequence frm demdulatr. Bttm: Crrelated utput frm narrw band, band-pass filter 31 Uncrrected spectrum utput f the punctual channel band-pass filter 32 Crrelated spectrum utput f the punctual channel band-pass filter 33 Ideal crrelatin triangle 36 Punctual channel crrelatin triangle 37 Ideal Early minus Late crrelatin signal 38 VI

14 Figure 2.16: Figure 2.17: Figure 2.18: Tp: Transmitted data. Middle: Uncrrelated received wavefrm. Bttm: Uncnditined uncrrelated data wavefrm utput frm the uncrrelated punctual channel(nise) 41 Tp: Transmitted data (600 Hz square- wave). Middle: Crrelated BPSK wave frm (data mdulated PN sequence stripped). Bttm: Demdulated uncnditined data 42 Tp: Demdulated data signal, partially cnditined (amplifier Gain = 50) DC ffset = 7.3 vlts. Bttm: Fully cnditined data restred t 600 Hz TTL cmpatible vltage level 43 Figure A.l: Mdulatr functinal blck diagram 49 Figure A.2: Demdulatr functinal blck diagram 50 Figure B.l: Oscillatr and divisin chain (mdulatr) 52 Figure B.2: PN generatr and TTL/analg interface (mdulatr) 53 Figure B.3: Functin generatr and mixer (mdulatr) 54 Figure B.4: Mdulatr schematic 55 Figure B.5: Oscillatr and divisin chain (demdulatr) 56 Figure B.6: PN generatr and delay with TTL/analg interface (demdulatr) 57 Figure B.7: Demdulatr mixer cnfiguratin 58 Figure B.8: 4th rder band pass filter (punctual channel depicted) 59 Figure B.9: Early minus late envelpe detectrs and tracking signal 60 Figure B.10: Data cnditining circuit 61 Figure C.l: Cascaded 2nd rder band pass filters, Q=50 68 Figure C.2: 4th rder band pass filter, f = 245.7kHz, Q=50 69 vn

15 ACKNOWLEDGMENTS I wuld like t thank my wife Marilu, fr her patience and the supprt that she prvided during the research f this prject; withut her help and encuragement this thesis wuld nt have been pssible. I wuld als like t thank Prfessr Tri T. Ha and Prfessr Rudlf Panhlzer fr their insight, encuragement and trust t cnduct this research. vui

16 I. INTRODUCTION A. GENERAL Spread spectrum cmmunicatins systems have becme an increasingly imprtant area fr research and develpment. Due t the ever-increasing demands n the available electrmagnetic spectrum, there is a grwing need fr higher data rate, digital cmmunicatins systems. In sme situatins it is als desirable t reduce the prbability f interference thrugh jamming envirnments r ver crwded radi frequency cmmunicatins channels. Additinally, thers may require a reduced prbability f intercept t.prvide a secure means f transmitting data. Clearly, advances in the area f digital cmmunicatins are bund by these requirements t prduce mdulatin schemes but, f particular interest in the military, is the creatin f cmmunicatin systems that are rbust enugh t prvide a reliable link in jamming envirnments. This, cupled with the rapid rise in the number f ptential users and the need fr systems that can be established rapidly in remte lcatins, require mre sphisticated systems. Such systems can be designed such that their susceptibility t interference is lw and their verall perfrmance characteristics are desirable. Spread spectrum cmmunicatins systems lend themselves t be uniquely suited t meet these demands [Ref.3:p.539]. B. TECHNICAL BACKGROUND Spread spectrum utilizes a high bit-rate cding sequence t mdulate and demdulate the data which is sent ver the transmissin channel. The use f this cding sequence changes the spectral bandwidth f the mdulatin scheme and is usually ne r tw rders f magnitude wider than that f its standard (nn-

17 spread) cunterpart. This uncnventinal treatment f channel bandwidth appears flagrantly irrespnsible with regard t bandwidth cnservatin. Hwever, the ptential interference created n adjacent channel frequencies by the resulting signal, in many instances, is negligible since the resulting signal is at r belw the channel nise level. Additinally, the transmitted signal is nly detectable by a receiver cnfigured with the identical cding sequence. An added benefit is realized during demdulatin whereby, narrw band nise intrduced n the channel (jamming) will nt interfere with demdulatin since the principle f spreading (applied t a narrw band signal nce) reduces its signal strength significantly [Ref.13]. The Naval Pstgraduate Schl (NPS) has develped a satellite cmmunicatins prject that will investigate sme f the peratinal characteristics f a spread spectrum cmmunicatins link. This prject, entitled "Petite Amateur Navy Satellite" (PANSAT), is prpsed t emply a binary phaseshift keying cmmunicatins package which will aid in develping insight int the develpment, successful delivery, peratin, and management f an peratinal satellite cmmunicatins system. As a majr part f its missin it will prvide a small peratinal test platfrm fr a spread spectrum cmmunicatins package. The prject is scheduled fr launch late in 1995 and will be fully peratinal by This thesis examines a hardware slutin fr the develpment f a binary phase-shift keying (BPSK), direct sequence, spread spectrum mdem t be implemented as ne f the main cmmunicatins channels t be used by PANSAT. The design develped in this thesis prpses a preliminary hardware design. The design described here is the first cmpact, peratinal prttype f a BPSK spread spectrum mdem develped fr the PANSAT prject and will eventually be refined int a viable small satellite cmmunicatins link.

18 I N _ II. MODEM DESIGN AND OPERATION A. SYSTEM OVERVIEW 1. Mdulatin The mdulatin sectin f the mdem design cnsists mainly f three significant functinal blcks. These are the divisin chain, the functin generatr and the pseud-randm nise (PN) generatr. Each f these blcks takes a specified input and creates a wavefrm used in the generatin f the BPSK spread spectrum signal. The mdulatr functinal blck is shwn belw as Figure 2.1 and is als shwn in smewhat greater detail in Appendix A as Figure A.l. VCG mm OATA r U i SPREAD SPECTRUM BPSK: n DIVIDE BY 20 DIVIDE BY 32 fit) MIXER FUNCTION GENERATOR PN GENERATOR Figure 2.1: Mdulatr functinal blck diagram. In the case f the divisin chain, the input cmes frm the crystal scillatr in a standard CMOS inverter cnfiguratin. In this design the scillatr acts as the master clck. Tw reduced frequency wavefrms are prduced frm

19 the master clck prviding the inputs t the remaining functinal blcks. The utputs f the divisin chain are even multiple divisins f the crystal scillatr and are square-waves fr reasns that will becme clear as the peratin f the circuit is discussed later in the chapter. The functin generatr receives the higher frequency signal f the tw square-wave utputs frm the divisin chain. By the use f cmparatrs, peratinal amplifiers and a precisin sine-wave generatr, the functin generatr utputs a sinusidal carrier used in an intermediate frequency (IF) applicatin. In the present stage f develpment fr this design it acts as the carrier frequency. Up-cnversin t the final radi frequency (RF) is a matter fr further develpment implemented in the final PANSAT mdem design. This thesis explres the ptential fr an experimental design in the implementatin f a spread spectrum mdem and investigates wavefrms, relative signal strengths and acquisitin and tracking cntrl fr the preliminary design using an IF lp-back frm fr testing the design. Hence, the develpment f the system is carried ut thrugh the IF stage. As mre expensive precisin cmpnents are used in the future, the design will be mdified but, its functinality will remain the same. Thus, this thesis prvides prf f cncept fr the mdem design. Additinally, the final design must perate with significantly lwer pwer cnsumptin since pwer is limited in PANSAT. 2. Demdulatin The demdulatin functinal blck diagram is clearly mre cmplicated than that f the mdulatr. Hwever, upn review, it demnstrates sme f the elegance f as well as the cmplicatins invlved in the develpment f a spread spectrum cmmunicatins design. The functinal blck diagram itself cnsists f a divisin chain, PN generatr and functin generatr. These have identical characteristics t thse discussed previusly in the mdulatin sectin. In

20 1I additin t these sectins the demdulatin prcess als requires a PN delay sectin, filtering and level detectin, scillatr feedback cntrl and utput signal cnditining sectins. The demdulatr functinal blck diagram is shwn in Figure 2.2 as well as in Appendix A as Figure A.2. As mentined abve, the PN generatr, divisin chain, and functin generatr sectins are the same as thse in the mdulatr and cnsequently, their utputs are identical t thse emplyed by the mdulatr. Received Signal BPF Envelpe Detectr -J BPF Envelpe Detectr r PN Punctual 1/2 Chi L*tt Delay* 1/2 Del Chip Early BPF Envelpe Detectr Generatr Functin Generatr Cmparatr Div ide by I 30 xiz_a2_j Divide by 20 Envelpe Detectr (Italic c.atr.l VHlQ* Et.Hr - lau Cmparatr Demdulated -> 1200 BPS DATA A«ul»ltl»n»lan«l Figure 2.2: Demdulatr functinal blck diagram. The PN delay sectin prvides the early and late PN sequences required fr tracking the incming signal. The phase relatinship between the PN sequence used in mdulatin t spread the signal, and the PN sequence f the punctual

21 channel f the demdulatr must be cntrlled in rder t ensure that demdulatin ccurs [Ref.l:p.l54]. During the acquisitin phase f peratin, the PN generatr in the demdulatr is driven at a higher clck rate ( khz) and the incming signal is crrelated with the utput f the punctual PN sequence sectin. This pint needs t be fully understd in rder t appreciate the peratin f the demdulatr. Acquisitin time is critical in a system that emplys spread spectrum techniques since data that passes withut being crrelated is bviusly lst. Additinally, if the signal is lst, regaining acquisitin as quickly as pssible minimizes the verall data lss. This design uses a digital prgrammable divider t prvide the apprpriate frequency clck t the PN generatrs. By digitally changing the divisin factr (in the demdulatr nly) frm a lw value t a high value at the instant crrelatin ccurs, the acquisitin time is reduced drastically. In the perspective f the infrmatin bit rate, this design achieves a maximum acquisitin time f 12 millisecnds. This crrespnds t apprximately 14.7 data bits and reflects the maximum number f bits lst frm the cmmencement f acquiring the signal. Hwever, it may be adjusted further t achieve a faster acquisitin time. This is accmplished by changing the wiring cnnectin at the prgrammable inputs t the divider and is discussed later. Anther key element f demdulatin that ccurs at the instant f acquisitin is the shift f cntrl vltage t the VCO. The VCO is shifted frm static t dynamic feedback cntrl utilizing the same punctual acquisitin signal used t implement the change in the divisin f the PN clck. Dynamic feedback cntrl is emplyed t cntrl the frequency f the VCO in rder t crrect fr ptential drift f the transmitted PN sequence. Any significant drift wuld clearly degrade the ability f the demdulatr t crrelate cntinuusly and prevent the 6

22 demdulatr frm prviding a reliable cmmunicatins link. These changes in PN clck frequency and VCO cntrl crrespnd t the change frm an acquisitin mde f peratin t that f a tracking mde f peratin and vice versa. While in the tracking mde f peratin, the tw parallel channels f early and late crrelatin prvide a summed vltage feedback t the VCO via their respective band-pass filters, crrespnding signal level detectrs, and an inverting and summing set f amplifiers. Utilizing this feedback vltage the frequency f the VCO tracks the frequency f the incming signal and maintains an in-phase r cherent phase state fr the demdulatr. The signal, as it appears frm the utput f the punctual channel during tracking, is n lnger spread spectrum since the PN sequence has been stripped frm the carrier by a mixing peratin with the utput f the punctual PN generatr. This in turn, implies that the signal utput frm the mixer is a BPSK mdulated wave whse frequency is that f the EF frequency. All phase shifts that nw ccur are merely the result f the transmitted data. While the master clck is maintained in track mde, cherent demdulatin f the data takes place. By nature f the fact that the functin generatr (prducing the sinusidal IF carrier) is als cntrlled by the master clck, the phase relatinship f the carrier wavefrm is als maintained cnstant. While in the track mde f peratin, the utput f the punctual channel is cmbined with the utput f the functin generatr t prduce a signal representative f the riginal transmitted data. An AD534JD is cnfigured t simply add the signals. Its utput signal is passed thrugh a cnditining circuit t prduce the recvered data at vltages representative f TTL data (0 and +5 vlts) and is discussed later in this chapter.

23 B. DIVISION CHAIN 1. Mdulatr The clcking and functin generatr wavefrms required fr the mdulatr cnsist f tw square-waves. These are generated by prgrammable divisin f the MHz crystal scillatr which acts as a master clck. Since the same timing sequences are required fr bth mdulatin and demdulatin, the cnfiguratin fr the divisin chain hardware is identical except during preacquisitin mde as mentined next in the demdulatr discussin. In the mdulatr, the PN sequence square-wave (153.6 khz) and the square-wave used in the functin generatr sectin (245.7 khz) are whle multiple, cumulative divisins f the master clck by factrs f 32 and 20 respectively. T achieve these divisin multiples, tw fur-bit, synchrnus, binary up/dwn cunters (54193) are used in parallel channels in cnjunctin with a J-K flip/flp ( fr the PN sequence clck) and tw J-K flip/flps (74109 fr the functin generatr). The flip/flps in each case cntribute a factr f tw t the verall divisin f signals at their respective inputs. Fr this reasn the cunter divisin multiple fr the PN clck is set t 16. Since tw flip/flps are utilized in the derivatin f the functin generatr square-wave, their cntributin t the verall divisin factr f the master clck is a factr f fur. Cnsequently, the divisin multiple in the functin generatr divisin chain is set t five. The utput f each terminal flip/flp is by design the square-wave representatin f the desired clck at the desired frequency. The circuit diagram fr the mdulatr divisin chain is shwn in Figure B.l and is lcated in Appendix B. A representative set f wavefrms fr the crystal scillatr and the khz and khz square-waves appear as Figures 2.3 and 2.4 later in this chapter.

24 The is a fur-bit, prgrammable, binary cunter which when driven by the master clck utputs a reduced frequency pulse train. The divisin value is set by its fur data input pins. These prgrammable cunters are emplyed t aid in the future design flexibility fr adaptatins t the divisin chain. This is in anticipatin f their use with a higher frequency (and mre precise) vltage-cntrlled scillatr (VCO) serving as the master clck. This als supprts the pssibility f digital feedback cntrl f the VCO. Additinal cunters emplyed as dividers can easily be arranged in series with the existing design when needed fr adaptatin t a final space ready mdem adding greater flexibility t the divisin chain. 2. Demdulatr As mentined abve, the hardware cnfiguratin f the demdulatr divisin chain differs nly slightly frm that f the mdulatr. The PN generatr clck is designed t perate in tw distinct mdes (acquisitin and track) and, depending n the mde, utputs ne f tw clck frequencies. While in the acquisitin mde, the prgrammable cunter is set t divide by 15 vice 16 creating a ttal divisin (including the flip/flp) f 30 vice 32. The resulting clck drives the PN generatr in the acquisitin mde at a frequency f khz vice khz. This creates a rapid cnvergence f the PN sequence t its relative synchrnized crrelatin with the PN sequence f the received signal. It als serves as a small demnstratin f the verall design flexibility that may be explited if a micr-cntrller is used fr digital frequency cntrl in future designs. Once the PN sequence is at the apprpriate psitin relative t that f the incming signal, the crrelatin signal frm the punctual channel triggers an analg switch (PWI SW06) t change the divisin perfrmed by the prgrammable divider frm 15 t a value f 16. Subsequent refinement f the

25 frequency is then assumed by the VCO feedback circuitry. The circuit diagram fr the demdulatr divisin chain is lcated in Appendix B and is Figure B.5. C. PN GENERATOR 1. General The pseud-randm nise (PN) generatr used in bth the mdulatin and demdulatin sectins f the BPSK cmmunicatins package is driven by the clck generated frm the crystal scillatr via the divisin chain as described in sectin 2.B. The crystal frequency was chsen arbitrarily t be a MHz fundamental frequency frm readily available cmpnents. This frequency, when divided by a factr f 32, creates the khz clck frequency which then crrespnds t the chip rate fr the system. Fr cmpliance with Federal Cmmunicatins Cmmissin (FCC) rules gverning the implementatin f SS cmmunicatins systems in the amateur radi frequency bands, a seven-bit sequence (ne f three allwed) is used n PANSAT [Ref.6:p ]. BY design, each data bit will cntain 127 chips (an entire sequence) f the PN sequence. A final space-ready design f PANSAT (supprting a data rate f 1200 bits per secnd) must have a clck frequency and crrespnding chip rate f khz. This arises frm the FCC cnstraint f cntaining an entire epch (127 chips) f the spreading PN sequence within exactly ne data bit f the digital infrmatin t be transmitted. Since the design develped in this thesis is intended t shw prf f cncept fr the develpment f the SS mdem, the mdified chip rate was chsen s that it might clsely simulate that f the final design while frging the expense f a custmized scillatr. The fundamental peratin f the system will nt change appreciably when altered t the final chip rate f khz. 10

26 2. Technical a. Mdulatin PN Sequence Generatin Fr the hardware design f the mdem the chip rate is established thrugh the prgrammable divider and a J-K flip/flp (refer t circuit diagram B.2 in Appendix B). The scillatr utput is pictured in Figure 2.3. Use f a flip/flp in this applicatin is essential t create the symmetric square-clck wavefrms. The square-waves are necessary t establish bth the early and late tracking PN sequence relatinships fr synchrnizatin feedback used in the delay-lck lp. Additinally, a synchrnus square-wave is needed in the generatin f the sinusidal carrier fr this design. In the mdulatin sectin a square-wave clck is nt required fr generatin f the PN sequence since n cmpanin PN sequences (either early r late) are used. The identical cnfiguratin fr the clck generatin is emplyed nnetheless in bth the mdulatin and demdulatin sectins in rder t prvide cntinuity f design. Since synchrnizatin PN sequences are clearly neither generated nr used in the mdulatr, a final design cntaining bth a mdulatr and demdulatr as a unit may likely share the same PN generatr but nly fr cnservatin f limited spacecraft pwer. Fr this additinal reasn, square clck wavefrms are used thrughut this design and can be implemented in just this way fr the final space ready design. The divisin chain hardware in the mdulatr is nt as cmplex as that f the demdulatr since synchrnizatin and tracking are accmplished nly in the demdulatr. Each f these divisin chain implementatins was discussed in detail in sectin 2.B f this chapter. Only tw key clcking wavefrms are generated in the mdulatin sectin. These are the PN clck (153.6 khz) and the square- wave used in sinusidal carrier generatin (245.7 khz). 11

27 The PN generatr itself cnsists f an eight-bit shift register (74LS164), tw exclusive-r (XOR) gates (7486) and a synchrnus binary cunter (74161). The elementary design was taken frm Reference 6, p , althugh many variatins are available frm ther literature surces. This design features simplicity as well as a desirable zers-catching functin preventing the shift register frm becming lcked in an all-zers state. Figure 2.3: Crystal scillatr utput. Oscillscpe settings: X = 0.2 usec/div., Y = 2.0 v/div.. The design is mdified t include a synchrnus binary cunter fr the additin f a nes-catching capability since peratin f the design withut it is unreliable and ccasinally lcks the shift register in an all-nes state. An alternate nescatching circuit utilizes an eight input NAND gate vice a cunter. Implementatin f nes-catching by a NAND gate was cnsidered fr this design and wuld wrk equally well. Hwever, the synchrnus binary cunter was used t minimize the number f wiring cnnectins. 12

28 The shift register itself creates the PN sequence thrugh mdul-2 additin f the utputs f tw stages f the shift register (refer t Figure B.2 in Appendix B). In this design the first and seventh stages f the shift register are mdul-2 added by way f an XOR gate (the eighth register is nt used). The resultant lgic level is fed back t the input f the first stage f the shift register via a secnd XOR gate n which the cmpanin input terminal is tied t +5 vlts ("high"). This secnd XOR acts as an invertr but functins as the zers-catching lgic gate. Withut this secnd XOR gate, initial pwer- up f the PN generatr will leave all values in the shift register as well as the input t the first stage register at vlts ("lw"). They will remain lw as feedback cannt reach a high lgic level withut artificially lading a high level int ne f the first seven stages. The clck sequences fr PN generatin as well as the square- wave used fr sinusidal carrier generatin are shwn in Figure 2.4. Als essential t the reliable peratin f the PN generatr is the nes-catching prperty f the synchrnus binary cunter. Simply stated, the is driven at the chip rate by cnnecting its clck input t the same clck that drives the shift register. The PN sequence utput f the shift register is cnnected t the clear pin n the cunter which is active-lw. Every time a zer is prduced during PN sequence generatin the cunter is cleared. The maximum number f cnsecutive nes in the sequence is seven. This prevents the cunter frm reaching a cunt f 16 while mnitring the activity f the shift register during the generatin f the PN sequence. If all stages f the shift register simultaneusly reach a high lgic level, the binary cunter will cntinue t cunt withut being asynchrnusly cleared since the PN sequence is lcked in an allnes state by the zers-catching XOR gate. The ripple carry utput f the cunter is tied t ne input terminal f an XOR gate n which the cmpanin input terminal is tied high. The XOR utput is cnnected t the clear pin f the 13

29 .'.. 1 i : - - 1,, shift register. In this way, the detectin f an all-nes state will be crrected by an asynchrnus clear f the shift register. ' 1 1 ' ' s '! i j j j : ) '.' j 5 ; m mm > i m m m -*-- -- mm mm mm ha '*«a*> ** it's ( j i j i \. t Figure 2.4: Tp: PN generatr clck. Bttm: Functin generatr clck. Oscillscpe settings: X = 10 jisec/div., Y = 5 v/div.. The XOR gates emplyed in the PN generatr fr zers- and nescatching merely act as inverters. The XOR gates are used here vice inverters simply because f the availability f the unused XOR gates n the 7486 chip used fr mdul-2 additin in the PN generatr sectin. Once the shift register is cleared, the binary cunter is als cleared allwing the sequence t resume generating nrmally. The cunter itself is actually cleared after a cunt f seven frm the resumptin f nrmal PN sequence generatin since the clear pin n the cunter is tied directly t the utput f the zers-catching XOR gate. The seven shifts are required t create the necessary active-lw cnditin appear at the clear pin f the cunter. Thus, 14

30 1. the cunter is still prevented frm reaching a cunt f 16 and nrmal PN generatin cntinues. Figure 2.5: Tp: PN generatr clck (153.6 khz), 2 v/div. Bttm: PN sequence used fr spreading, 5 v/div.. The resultant PN sequence, assuming nrmal uninterrupted peratin, is a maximal length sequence cnsisting f series f high and lw lgic levels (nes and zers) in pseud-randm rder. This binary sequence is repeated every 127 clck cycles and each sequential pattern is identical. The peridicity f the sequence results frm the relatinship in Equatin (2.1) which relates the number f stages in the shift register emplyed (m) t the length f the sequence (L), up t the pint f repetitin [Ref. l:p.58]. L = 2 m - (2.1) A representative sample f the actual maximal length PN sequence used in bth the mdulatin and demdulatin sectins is shwn in Figure

31 alng with the khz clck. In actuality there are nly apprximately 100 f the 127 chips represented in Figure 2.5. This is due t the triggering f the wavefrm n the scillscpe and the settings used t prduce an illustrative phtgraph f the PN sequence. Three identically cnfigured PN sequences are emplyed in the demdulatin sectin and are used in the acquisitin and tracking f the incming signal. VCO feedback cntrl is required in rder t maintain synchrnizatin and enable the demdulatr t cntinuusly track the incming signal. Fr this reasn, tw additinal PN sequences f the identical maximal length (127 chips) are generated at a 1/2 chip timing ffset relative t the PN sequence used t acquire and demdulate the received signal. The demdulatin PN sequences are discussed next. b. Demdulatin PN Sequence Generatin As will becme evident in the fllwing sectins, three PN sequences (identical t that f the mdulatr) are required fr acquisitin, tracking, and cnsequently demdulatin f the received spread spectrum signal. These sequences are termed "punctual", "early" and "late." Generatin f the punctual sequence in the demdulatr is identical t that f the mdulatr described earlier and the hardware remains the same. The early and late PN sequences are generated by delaying the utputs frm the sixth and seventh stages f the shift register by 1/2 chip respectively. Fr the early sequence, the utput f the sixth stage f the shift register is sent t an inverter fr buffering. This inverted sequence is sent t a secnd inverter. These inversins prduce tw PN sequences that remain ne chip early but are lgical cmpliments f each ther. The cmplimentary sequences are then tied t the J and K inputs f a J-K flip/flp t prduce the delay. 16

32 The same clck used fr the shift register is cnnected t the The utilizes a falling clck transitin and, in the cnfiguratin shwn in Appendix B, acts as a single bit shift register. Since the J and K inputs are always cmpliments f each ther they are shifted t their respective Q and Q utputs when the flip/flp is clcked. Since the clck transitins fr the shift register and the flip-flp psses ppsite transitin states (rising fr 74LS164 and falling fr ), the arrival f the cmplimentary PN sequences at the input f the is guaranteed t be 1/2 chip prir t the falling edge f its clck. The resultant utput frm the is a PN sequence identical t that f the punctual ne but whse timing appears advanced by 1/2 chip relative t the punctual sequence. Figure 2.6: Tp: Early PN sequence. Bttm: Late PN sequence. Nte: One chip differential. The late PN sequence is created in the same fashin differing nly in that the parent sequence taken frm the shift register is the punctual sequence itself and results in a PN sequence whse timing is delayed by 1/2 chip relative t 17

33 the punctual sequence. Cnsequently, the same hardware discussin applies as well. The relative psitins f the early and late sequences are shwn in Figure 2.6 and the circuit diagram fr the demdulatin PN generatr appears as Figure B.5 in Appendix B. D. FUNCTION GENERATOR 1. General The functin generatr creates the sinusidal carrier used in the transmissin f the spread spectrum signal at the IF frequency. The generatin f a sinusidal carrier can be accmplished in many different ways but the particular slutin depicted in this design is the mst practical ne given its minimal cst. Althugh minimized cst is nt a requirement fr a prttype design, in this case readily available cmpnents are used due t the intent f this design being mainly prf f cncept. All cncepts used in this as well as ther sectins f the mdem design are fully adaptable when mre sphisticated cmpnents are used. Additinally, the basic functinality f the design will nt appreciably change. Since bth the mdulatin and demdulatin sectins create their sinusidal wavefrms in the same manner, the technical descriptin as well as the hardware design applies t bth. 2. Technical A circuit diagram fr the functin generatr is shwn in Figure B.3 and is lcated in Appendix B. The functin generatr sectin receives a square- wave at the frequency f khz frm the divisin chain. The square-wave is cnverted frm TTL vltages and their assciated lw driving currents t the apprpriate values required by the analg cmpnents used in the generatin f the sinusid. This is accmplished by interfacing the utput f the divisin chain thrugh a cmparatr. 18

34 ' > The utput f the divisin chain is fed t the negative input pin n a vltage cmparatr (LM311P) which is cnfigured t prduce an utput t supply a grund referenced lad [Ref.7:p.2-54]. Tw 1KQ ptentimeters are used t establish the psitive and negative peak values f the resultant squarewave at +2.5 and -2.5 vlts. These are derived frm the +15 and -15 vlt pwer supplies used thrughut the analg prtin f this design. Lj *! : i.... \ I 1 - a *», ; * i i.-., f % i i i 1 11 ^A K^'ijf V! *-, V i V l V 1 i V Figure 2.7: Tp: khz Square wave; LM311P utput. Bttm: Triangle wave utput f LM318N integratr. Oscillscpe setting: X = 2 jis/div., Y = 5 v/div.. The threshld vltage is clearly a psitive value since the input square wave is a TTL signal. The threshld vltage is established thrugh the center tap f a 10KQ ptentimeter cnnected t the +15 vlt supply and is adjusted t ensure a balanced square-wave utput. The vltage value fr the reference vltage threshld in this design is measured frm the cmpleted circuit bard at pin 2 f the LM31 IP. This vltage is vlts as expected given a cnsistent standard TTL input. 19

35 The use f bth 0.1 f ceramic and l.ojif tantalum capacitrs as pwer supply bypass capacitrs is abslutely essential t prduce a nise free utput frm the LM318N [Ref. 8:p.42]. In additin, a 30pf capacitr is used between pins 1 and 8 n the LM318N t stabilize the utput wavefrm. The design withut the additin f the previusly mentined capacitrs des nt functin. Figure 2.8a: Tp: Triangle wave fllwing vltage divider. Bttm: khz Sinusidal utput. Oscillscpe settings: X = 2 jis/div., Y = 1 v/div.. Fr the transitin frm a square-wave t a suitable wavefrm fr sinusidal generatin, the khz square- wave is sent frm pin 1 f the LM31 IP t the inverting input pin f an peratinal amplifier (LM318N) which is cnfigured as an integrating amplifier [Ref. 5:pp.l64 & 268]. The capacitance value used in the feedback lp is 68pf and is in parallel with a 240KQ resistr. Supply vltages V+ and V- are taken directly frm the +15 and -15 vlt pwer supplies. The utput f the LM311P as well as the utput f the integrating LM318N is shwn in Figure

36 The resulting triangle wave is cnnected t pin 1 f a universal trignmetric functin generatr (AD639AD) via a resistance vltage divider. The vltage divider serves t limit the input vltage t the AD639AD t a designed maximum peak vltage f 1.8 vlts and thereby minimizes distrtin in the generated sine wave. These resistance values (R19 and R20) are fixed as shwn in Figure B.3 lcated in Appendix B. Since the amplitude f the triangle wave is dictated by the amplificatin set by the integratr (cmpnent U13 in Figure B.3), the use f a ptentimeter fr vltage reductin is nt required. Cnsequently, fr adaptatins f future designs using this cnfiguratin, replacement f the ptentimeters in the cmparatr circuit preceding the functin generatr sectin may require nly a slight adjustment. In additin, ptentimeters are nt expected t be utilized in a space flight mdel due t the ptential fr drift when expsed t vibratin. In any case, the peak input vltage f 1.8 vlts t the AD639AD is easily realizable utilizing fixed resistrs. The AD639AD is cnfigured fr sine-wave utput [Ref. 5:p. 162], A representative sample f the sinusidal utput f the functin generatr sectin is depicted alng with its input triangle wave in Figure 2.8a. The sinusidal wavefrm underges n additinal amplificatin prir t the mixing peratin emplyed t prduce the spread spectrum signal in this design. There is hwever rm fr amplificatin since the maximum input vltages fr the mixer (discussed in the next sectin) are nt apprached here. Further amplificatin is expected t be accmplished in a final design where up-cnversin will be required and attenuatin induced by pwer cnserving, passive elements will be encuntered. 21

37 E. MIXERS 1. General The BPSK mdulated signal utput f the mixer in the mdulatin sectin is the result f the cmbinatin f the PN encded data stream with the sinusidal carrier. Mixing peratins fr the BPSK spread spectrum mdem in this design, r in general where digital SS BPSK is used, ccur in tw places. The 1200 bps data stream is mdul-2 added t the PN sequence in the mdulatin sectin creating the PN encded data stream. An XOR gate is used fr this prcess and since the inputs t the XOR gate are TTL vltages with a biplar characteristic, the functin perfrmed by the XOR is essentially a mixing peratin. This fact may seem trivial but creates an imprtant dual as cncerns the treatment f the signal in mdulatin and its subsequent demdulatin. The TTL vltages are cnverted t plus and minus vltages fr interfacing with the analg cmpnents in this design. The mixing f the data, PN sequence and sinusidal carrier can be accmplished in any rder while still prducing the same BPSK spread spectrum result. As will be discussed in the demdulatr discussin, the PN sequence is remved frm the spread signal first. 2. Technical a. Mdulatin i The mixers emplyed fr mdulatin cnsist f an XOR gate and an internally trimmed, precisin IC multiplier (AD534JD). The AD534JD is als cmmnly knwn as an analg vltage multiplier. The inputs t the XOR gate are the TTL data stream (at 1200 bps) and the PN sequence generated by the PN generatr sectin f the mdulatr. The utput f the XOR gate can be thught f as essentially a bi-phase shifted PN sequence. Cnsidering the length f the sequence (127 chips) as ne perid, each data transitin (which cntains 127 chips) causes the PN sequence t invert. 22

38 The PN sequence phase relatinship is then similar in fashin t that f a bi-phase shifted sinusid since the PN sequence is als a peridic wavefrm. The design in this case nly clsely apprximates the chip rate f the final design and instead f cntaining exactly ne entire PN sequence (127 chips) within ne data bit there are nly chips per bit. This f curse was discussed in the PN generatr sectin and will need t be altered t cmply with FCC rules. The fundamental peratin f this BPSK spread spectrum design is independent f the number f chips per bit and any alteratins t meet this specificatin fr use in PANSAT will have n effect n the perfrmance f the design. The maximum peridicity by which the PN sequence chips will be inverted is the reciprcal f the data rate (r fisec). The assciated phase change f the PN encded sequence ccurs in intervals f less than r equal t the perid f ne data bit. An alternating data sequence (square-wave) creates the maximum peridicity f inversins t the PN sequence. Fr testing purpses a 600 Hz TTL square-wave is used t simulate the 1200 bps data stream. The resulting PN encded data stream is interfaced with the AD534JD by means f a vltage cmparatr (LM311P) which is cnfigured fr an utput supply t a grund referenced lad (a cmplete discussin f this cmparatr cnfiguratin is given earlier in part D f this chapter). The reference ptentimeter supplies a vltage f vlts t the minus input f the LM311P. The V+ and V- ptentimeters are set t supply and vlts. Each f the ptentimeters can clearly be replaced by a set f precisin resistance vltage dividers. The resultant utput is a balanced PN encded sequence with biplar vltages f +10 and -10 vlts. This signal is cnnected directly t pin 6 f the AD534JD which crrespnds t its Yl input. The sinusidal carrier frm the functin generatr sectin is als cnnected directly t the AD534JD n pin 1 23

39 which crrespnds t the XI input. The AD534JD accmplishes multiplicatin accrding t the frmula labeled Equatin 2.2 [Ref.9]. (X1-X2)(Y1-Y2) 10 + Z2 (2.2) The wiring cnfiguratin fr the mixers shwn in Appendix B as Figure B.3 and is taken frm Reference 9. This reflects a standard multiplicatin cnfiguratin and functins equally well as a mixer. This cmpnent can be easily replaced thrughut the design by passive dubly-balanced mixers and will be required fr this design eventually t minimize pwer cnsumptin as well as accmmdate a higher EF. Figure 2.8b: Tp: Sinusid frm functin generatr sectin. Middle: PN encded data utput frm cmparatr. Bttm: Spread spectrum BPSK utput at khz. An SRA-8 dubly-balanced mixer was used early in this design but the AD534JD is favred here fr adaptability t the verall breadbard design. The input and utput wavefrms f the AD534JD are shwn as Figure 2.8b and are 24

40 representative f apprximately five chips f PN encded data r l/25m f ne data bit at the prpsed data rate f 1200 bits per secnd. Frm the scillscpe trace it is clear that the utput f the mdulatr is a BPSK signal with a pseudrandm phase change. The relatinship between the unmdulated carrier, BPSK mdulated carrier (1200 bps data mdulatin nly), and spread spectrum BPSK mdulatin (PN encded data mdulatin) is seen clearly upn examinatin f their respective frequency spectrum utputs. Figure 2.9a: Frequency spectrum fr the sinusidal carrier(unmdulated) taken frm the utput f the functin generatr sectin. The frequency spectrum fr the unmdulated carrier is taken directly frm the utput f the AD639 functin generatr. In the case f the tw mdulated wavefrms, their spectral utputs are created by cnnecting the assciated mdulating square-waves t the Yl input f the AD534JD and maintaining the khz carrier cnnected t the XI input. The utput is taken frm the OUT and Zl pins which are tied tgether. The AD534JD des nt perate prperly when the inputs XI and Yl are swapped and therefre Equatin 25

41 2.2 nly applies t the cnfiguratin shwn in Appendix B fr mixing with the sinusidal carrier. The Z2 pin is grunded and therefre cntributes nthing t the ffset value depicted in Equatin 2.2. Figure 2.9b: Spectrum fr 1200 bps BPSK mdulated carrier. at 600 Hz is used as the data stream. A square wave The Spectrum utputs are shwn fr each f these three cases as Figures 2.9a thrugh 2.10b and are taken frm a spectrum analyzer set t a bandwidth f 500 khz and centered at the carrier frequency. The spectrum seen in Figure 2.9b as cmpared t that f the unmdulated carrier demnstrates that the bandwidth f the spectral main lbe and assciated side lbes widens. The bandwidth f cncern is that f the main lbe since it is the nly prtin f the spectrum transmitted in mst BPSK mdulatin schemes. In fact, n significant gain results frm the transmissin f the side lbes since an verwhelming fractin f the spectral energy is cntained within the main lbe [Ref. 6:pp.21-12,21-13]. This well knwn characteristic remains true in the applicatin f this spread spectrum design. 26

42 The frequency spread f the BPSK spread spectrum signal is twice that f the chip rate. This is clear when the characteristics f the PN sequence encded data stream are examined. Since the chip rate is several times greater than the data rate, the mdul-2 added sequence assumes the frequency characteristics f the PN sequence. Mrever, since the chip rate is khz the crrespnding main lbe bandwidth is apprximately twice this value r khz as seen in Figure 2.10b. The actual main lbe bandwidth, as determined frm the spectrum analyzer, is smewhat difficult t measure exactly since the spectrum takes n a nise spectrum with a (sin(x)/x)2 characteristic as is depicted in Figure 2.10b [Ref. I:p.l6]. The main lbe bandwidth fr this design is hwever cnsistently apprximated frm the spectrum analyzer utput at a value f 310 khz and is the EF bandwidth fr the demdulatr [Ref.4:p.50]. At l t.m 1 ISP^N I 500,0 khz I * *sma us 1.1 1!Jp*^ -s. s ft* n«fin 2*11.7 *Mt VftK 1 UN* Figure 2.10a: Spectrum fr the PN encded BPSK (spread spectrum) mdulatin. The max. hld setting is enabled n the analyzer. 27

43 The spread spectrum signal is transmitted frm the mdulatin sectin f the mdem design in an IF lp-back testing cnfiguratin and is cnnected directly t the demdulatin sectin. This prvides fr testing the prf f cncept fr this design as the majrity f the cmplicatins assciated with spread spectrum cmmunicatins design arise frm the inability t acquire and track the spread spectrum signal. There is n utput filtering cnducted within the mdulatin sectin f this design and hence all spectral cmpnents are received by the demdulatr in the IF lp-back channel. Output filtering at the mdulatr wuld have n significant effect n the perfrmance f this design and it is expected that adaptatins f the mdem described here will emply wide band filtering f the transmitted signal at the apprpriate RF frequencies centered at MHz. b. Demdulatin The demdulatin prcess reverses the rder in which the PN sequence and the data are cmbined with the IF carrier. This is pssible since the prcesses f mixing are rder-independent as discussed earlier. thing t be remved frm the incming signal is the PN sequence. Thus, the first As discussed earlier in this sectin the sequential rder f cmbining f data, PN sequence and carrier des nt matter. This fact is explited in the demdulatin sectin t the advantage f this design. The incming signal is applied t the XI input f an AD534JD while the punctual PN sequence is applied t the Yl input. The identical wiring cnfiguratins (as discussed fr the mdulatin sectin) fr bth the interfacing f the PN sequence and the applicatin f the AD534JD are used in the demdulatr. Hwever, the incming signal is applied t the AD534JD as 28

44 .,., 1 ppsed t using the khz IF carrier generated in the demdulatr. The mixer cnfiguratin fr the demdulatr is lcated as Figure B.7 in Appendix B. SPAN m Htm ***.* ***** m* 9m to».«2 V»W 10 *K* «P*N t>mj 5**» SO «#«Figure 2.10b: Main lbe frequency spectrum f the transmitted signal with (sin(x)/ x) 2 nise distributin. At the mment that the channel is cnnected and a signal is present the instantaneus utput f the mixer is ne f tw things. Either the punctual PN sequence immediately lines up chip fr chip with that f the PN sequence used in the mdulatin prcess r it des nt. In the first case, the utput frm the AD534JD is a BPSK mdulated signal where the phase changes are the result f data transitins nly ( e.g. a phase change at a maximum f nce every fisec). The secnd case is a BPSK mdulated signal in which the phase changes are the result f tw identical but ut f phase PN sequences (phase changes ccur at a minimum f each ccurrence f a chip perid r at least every fisec). The tw cases can be said t be divergent. That is t say that in the first case, where the phase changes are due slely t the mdulating data, the signal is appraching cherent demdulatin with ne less degree f 29

45 randmness. In the secnd case, the signal is appraching nise with ne mre degree f randmness and, as a result f the misalignment f the PN sequences, causes further spreading f the already widened frequency spectrum. The difference between the abve tw cases is what the demdulatin sectin in this design is cnstructed t explit. Figure 2.11: Tp: PN sequence used in mdulatin. Middle: Punctual PN sequence frm demdulatr. Bttm: Output f the narrw band, band-pass filter. Nte: The PN sequences are apprximately 1 chip ut f phase yielding a diminutive and varying envelpe. By cnnecting the utput f the AD534JD t a narrw band, bandpass filter (with a high Q), the utput f the filter is seen as a small envelpe when cmpared t the utput f the filter when crrelatin f the punctual PN sequences ccurs. These utputs are depicted in the Figures 2.11 and The resulting signal wavefrm in Figure 2.11 is representative f each lcatin alng the punctual PN sequence in which the alignment difference is greater than 1/2 chip. There is therefre a band f relative crrelatin that exists that is within 1/2 30

46 '» ;. hi :.. : chip either early r late relative t the punctual sequence. Alignment f the mdulatin and demdulatin PN sequences can be shwn t ccur in this regin. This is demnstrated in Figure *««* i i *. «*«««««* * mm mmmm mmmm «*...., (,, 1 I :ij '! Ul * 'mimm mm. t i»i»*m> «* * *, - 1 t - ;..:..;: ' I j 1. f : 1. 1» _. v ' B -v ;. 1» : :. J 1 I f : 1 ; i ' j 1 ^ 1 [ : j., -? j I j 1 j J- ill, >..: - i 1 I'll *»*» * mm* mm m mm** mummm mmmm mmmm m mrnrnlis. 1 '! 1 I ; j f ] [ j [ ; [ J 1 Figure 2.12: Tp: PN sequence used in mdulatin. Middle: Punctual PN sequence frm demdulatr. Bttm: Crrelated utput frm narrw band, band-pass filter. Nte: PN sequences are in phase yielding a cnstant envelpe. The utput f the mixer is sent thrugh an envelpe detectr and when the incming signal is nt crrelated the utput is rather lw (apprximately 0.1 vlts). The utput frm the envelpe detectr is ntably greater when encuntering a crrelated signal and cnsequently, utputs a higher vltage (apprximately 0.65 vlts) when the incming signal and the punctual PN sequence are crrelated. This higher utput is used as the indicatin f acquisitin f the incming signal and serves t trigger the change frm acquisitin t track mde. A difference in crrelated versus uncrrelated signals can als be seen in the analysis f the spectral utputs f the band-pass filter fr 31

47 each case. Figures 2.13a and 2.13b shw the uncrrelated and crrelated spectra as they appear n a spectrum analyzer frm the utput f the band-pass filter f the punctual channel. Ntably, the side lbes f the spread spectrum signal are missing in the uncrrelated utput f the band-pass filter since they are attenuated by the high Q f the filter [Ref.2:p.245]. They ccur at frequencies centered apprximately 1 and 1/2 times the chip rate abve and belw the center frequency f khz. -*w.w s- *; rfc*-* «a ess Of* t y.. p [] I l" i» L... I m Figure 2.13a: Uncrrelated spectrum utput f the punctual' channel band -pass filter. In the uncrrelated signal, the side lbes appear at frequencies abut 228 khz abve and belw the center frequency f the main lbe. Hence they d nt appear at the utput f the band-pass filter. Cnversely, when crrelatin ccurs the utput spectrum f the band-pass filter changes significantly. The side lbes that appear in the utput during crrelatin are representative f the data-nly, BPSK mdulated carrier. In fact, the spectral distance between the center frequency f the main lbe and the side lbes in the 32

48 crrelated case is apprximately 1 and 1/2 times the data rate vice the chip rate which, f curse, crrespnds t a factr f 127 times less. Thus, the data may be recvered frm the crrelated signal since the indicatin that the sequence is crrelated cmes directly frm the utput f the band-pass filter. Figure 2.13b: Crrelated spectrum utput f the punctual channel band-pass filter. Nte: Side lbes appear at apprximately 12 db higher than the remaining nise passing thrugh the band-pass filter. The mixers emplyed in the early and late prtin f the demdulatr sectin functin in the same way as that f the punctual channel. They are cnsequently cnfigured in exactly the same manner with cmparatrs interfacing the early and late PN sequences and aligned as discussed earlier in the mdulatin sectin. Likewise the sinusidal input is applied exclusively t the XI inputs and the PN sequences are cnnected t the Y2 inputs t ensure prper peratin. Their respective utputs are als fed thrugh band-pass filters f identical cnfiguratins t that which is used in the punctual channel. The early 33

49 and late channel filter utputs are each cnnected t envelpe detectrs. The envelpe detectr utputs are used in the tracking f the incming signal and maintain crrelatin fr the punctual channel by cntrlling the frequency f scillatin f the crystal scillatr. Clearly, the emplyment f suitable filters in this applicatin is key t the success f the verall perfrmance. The discussin f feedback cntrl f the VCO is cntained in sectin G f this chapter and fllws the discussin f the cnstructin f the band-pass filters. F. BAND-PASS FILTERS 1. General The purpse f the filters in the demdulatin sectin f this design is tw-fld. They need t prvide sufficient filtering t help eliminate nise that may interfere with the prper demdulatin f the incming signal in spite f the relative nise immunity characteristic f SS systems in general. As a by-prduct f the narrw band filtering characteristic they prvide the indicatin that signal has been acquired as well as an indicatin f relative phase cherence t the incming signal. Cst and cmpnent availability are als cncerns. T this end the design f the filters here dictates an active filter realizatin using peratinal amplifiers. Althugh a majrity f the pwer cnsumed in this design is attributed t the peratinal amplifiers that make up the band-pass filters, aspects f this slutin may be viable fr grund statin applicatins where the pwer cnsumptin f the mdem is nt a cncern. Clearly, passive elements such as crystal filters will be used in a final design due t limited spacecraft pwer. Nnetheless, the characteristics f the design remain the same and, as a matter f practicality, the use f peratinal amplifiers here allws fr prf f cncept in this design. 34

50 2. Technical The basis fr the design f the band-pass filters is taken frm References 11 and 12. The circuit diagram is lcated in Appendix B as Figure B.8. The peratinal amplifiers emplyed t cnstruct the filters are LM318N peratinal amplifiers. The identical pwer supply bypass capacitance requirements as mentined in sectin D.2 f this chapter are applied here and are essential fr prper peratin f the filters. Appendix C cntains a cmputer prgram and set f MATLAB generated, filter respnse curves shwing nearly actual characteristic pass bands fr the filters in this design [Refs.l 1 & 12]. G. VCO FEEDBACK CONTROL 1. General The primary cncern in an peratinal spread spectrum system is t ensure that the demdulatr can cnvert the incming signal frm the brad spectrum f frequencies ver which the spread signal cvers t signal frm which the riginal transmitted data may be recvered. a narrw band T accmplish this a demdulatin design must pssess tw critical features. First, the same PN sequence must be used in the demdulatin prcess as was used t riginally encde the data in the mdulatin prcess. Secnd, the frequency at which the demdulatin PN generatr is clcked must be cntrlled and cmpensated fr differences between it and the PN sequence imbedded within the incming signal. Additinally, the frequency cntrl must be agile enugh t cmpensate fr changes in the incming frequency t include the ptential Dppler shifts assciated with lw earth rbiting satellite cmmunicatins. Upn clse examinatin, the ability f the design cntained here bviusly des nt psses the VCO frequency agility required fr an peratinal satellite. The type f system emplyed here, hwever, realizes the fundamental perating principles 35

51 necessary t achieve the desired final design bjectives. This design prpses a means f frequency cntrl which takes the frm f a delay lck lp [Ref. 1 :p. 253]. 2. Technical The utput f the AD534JD mixers fr the early and late crrelatin channels take the same frm as the utput f the punctual channel as discussed in the previus sectin. These early and late crrelatin signals can clearly be seen as maximum when each f the respective PN sequences is in crrelatin with the incming signal. MAXIMUM CORRELATION Figure 2.14a: Ideal crrelatin triangle. As any ne f the PN sequences begins t cme int within ne chip f crrelating with the incming signal, the utput f the assciated envelpe detectr begins t rise linearly frm the uncrrected utput value t the maximum value achieved when the PN sequences are exactly crrelated. Beynd the maximum value, as the PN sequences pass ne anther, the envelpe detectr utput falls t the value crrespnding t that f an uncrrected signal. These crrelatin signals are represented as triangular pulses which ccur at a frequency 36

52 representative f difference between the incming signal and the demdulatr PN sequence. This triangular pulse is knwn as the crrelatin triangle [Ref. l:p.254]. A representatin f an ideal crrelatin triangle fr the punctual channel is shwn in Figure 2.14a. Figure 2.14b: Punctual channel crrelatin triangle. Oscillscpe settings: X = 0.1 msec/div., Y = 5 v/div. The width f the triangle at its base is simply related t the verlap distance f tw like PN sequences and is therefre tw chips wide. This is the ideal case. The actual crrelatin triangle fr this design is slightly narrwer due t the respnse f the system and the purity f the signals emplyed. It is als slightly runded due t the bandwidth restrictin f the demdulatr band-pass filter [Ref.l:p.21]. Even thugh the utput taken frm this design is clearly nt an ideal case, the crrelatin triangle remains useful in bth the acquisitin and tracking applicatins carried ut in the demdulatr. The actual crrelatin triangle fr the 37

53 punctual channel is shwn in Figure 2.14b. The early and late crrelatin triangles are identical in appearance but are nt shwn in the figure. There are als secndary crrelatins assciated with the prtins f the sequence that match fr several bits f the tw PN sequences. These secndary crrelatins create crrelatin triangles f lesser magnitude than that f the truly crrelated psitin in the PN sequence [Ref.l:p.76]. Hence, when a strng secndary crrelatin ccurs the ptential fr the circuit switching frm acquisitin t track mde exists. Hwever, sn after track mde has been established the PN sequences will n lnger be crrelated and the system will return t the pre- acquisitin r search mde until the next crrelatin is reached. The threshld vltage in this design is set sufficiently high t prevent secndary crrelatins frm intrducing any ntable degradatin in perfrmance. EARLY CORRELATION LATE CORRELATION Figure 2.15: Ideal Early minus Late crrelatin signal. Nte: The cntrl band is ne chip wide. 38

54 . The timing delays used t establish the early and late PN sequences allw fr the creatin f a linear vltage cntrl zne fr use in feedback cntrl. The vltage generated by the early minus late (E-L) circuitry during peratin in the track mde is applied t the varactr dide. This in turn adjusts the scillatr frequency by changing the cupling capacitance seen by the crystal. The utputs f the early and late envelpe detectrs are amplified using standard nninverting amplifier cnfiguratins emplying LM3 1 8N peratinal amplifiers [Ref 5:p.59]. The utput f the late crrelatin signal is then inverted and added t the early crrelatin signal thus creating an E-L crrelatin triangle pair. ideal E-L crrelatin signal is shwn as Figure The In rder fr this feedback vltage t be useful in any spread spectrum design the punctual signal must be within 1/2 chip f maximum crrelatin. And fr what may nw be bvius reasns, any frequency adjustments made by this crrectin vltage will be entirely errneus unless the punctual channel has first acquired the incming signal. When there is n incming signal the demdulatr is in the search mde. The VCO perates at a cnstant frequency based n the static cntrl vltage supplied t the varactr dide via the 100KQ ptentimeter. The divisin chain is cnfigured t utput the PN generatr clck at a frequency f khz. Frm the pint at which transmissin f a signal cmmences, the utput f the punctual crrelatin channel is mnitred by means f its assciated envelpe detectr and an amplifier. The acquisitin phase f signal demdulatin utilizes a sliding crrelatr [Ref. 10:p.240]. The cncept nted in this reference is emplyed here but the circuit is drastically different. As the PN sequence slides thrugh the incming signal variatins in the demdulated envelpe are sent t a cmparatr. When crrelatin ccurs the envelpe detectr utput vltage rises. The threshld vltage n the LM311P emplyed t mark the pint f punctual 39

55 crrelatin is set t change the cmparatr utput frm lw t high when the utput f the punctual channel envelpe detectr ges sufficiently high. The difference in frequency f the PN sequence assciated with the incming signal and the PN sequence f the demdulatr in the acquisitin mde is khz. If the arrival f the incming signal cincides exactly ne chip past the ptential synchrnizatin pint, a maximum f 126 chips must be traversed by the demdulatr in rder t acquire the signal. Fr this design the resulting theretical maximum time t acquisitin is 12.3 msec which crrespnds t infrmatin bits. Once the punctual crrelatin signal is detected the cntrl vltage input t the VCO is switched. This is accmplished by using an analg switch (PWI SW06) triggered by the punctual crrelatin signal itself via the LM311P cmparatr. The incming signal is then acquired. The circuit diagram fr the feedback cntrl sectin is shwn in Appendix B as part f Figure B. 5. The threshld vltage fr switching is set t minimize secndary crrelatins. It must be lw enugh thugh t accunt fr reduced crrelatin triangle peak magnitude induced by the khz frequency differential when the device is in the search mde f peratin. Once the SW06 is activated the static cntrl vltage is replaced by a sum f the riginal cntrl vltage and the input frm the E-L amplificatin stage. When a frequency difference exists the punctual PN sequence will attempt t drift (early r late) ut f crrelatin if a crrecting vltage is nt applied t the VCO. Upn drifting frm the maximum crrelatin value the early r late crrelatin signal (depending upn the directin f drift) will crrespndingly add t r subtract frm the cntrl vltage sensed by the VCO. The VCO will then adjust the frequency f scillatin until the frequency that matches the maximum pint f punctual crrelatin is reached. This feedback cntinues thrughut the receipt f the incming signal and the 40

56 demdulatr is thus maintained in a tracking mde and may further translate the incming signal back int the data bits that were transmitted. H. DATA CONDITIONING Once the received signal has been acquired, the PN sequence imbedded in it has been stripped frm the carrier by nature f the acquisitin prcess described earlier. Cnsequently, the simple additin f the functin generatr carrier (generated in the demdulatr) with the BPSK signal prduces an additive (high vltage value) resultant utput fr data that was transmitted as a lgic " 1 " and a cancellatin f wavefrms ccurs fr data that was transmitted as a lgic "0". Wf 1 f a <1 "BliPPftffl fiifff *?-* ffypp " %lf& ' Wgxmi : JSl:^.2:'P ;.' k-.<t- <,'-,.at.-.., f/lt-^-^i^m&iiskwsmmi S Figure 2.16: Tp: Transmitted data. Middle: Uncrrelated received wavefrm. Bttm: Uncnditined uncrrelated data wavefrm utput frm the uncrrelated punctual channel(nise). The resulting wavefrm is a BPSK mdulated signal that cntains the transmitted infrmatin and is ready fr further demdulatin. 41

57 Since the PN generatr and functin generatr clcks are derived frm the same surce, the phase cherence f the sine-wave generated in the demdulatr is already established relative t the incming signal phase. This f curse hlds true nly if the tracking feedback vltage maintains an in-phase relatinship with respect t the punctual PN sequence. When the signals are nt crrelated the utput f the demdulatr is essentially nise since n frm f data is distinguishable frm the utput. The wavefrms assciated with an uncrrelated cnditin are shwn in Figure Cnversely, when crrelatin ccurs, the utput clearly depicts the presence f data. The BPSK mdulated signal prduced during track mde and the uncnditined recvered data signal are shwn in Figure Figure 2.17: Tp: Transmitted data (600 Hz square-wave). Middle: Crrelated BPSK wave frm (data mdulated PN sequence stripped). Bttm: Demdulated uncnditined data. 42

58 The carrier generated in the demdulatr is added t the BPSK demdulated signal and the result is amplified and passed thrugh an envelpe detectr. The partially cnditined data stream is then sent t a cmparatr which brings the vltage levels back t their riginal TTL values. The resultant fully cnditined data is depicted in figure 2.19 and the circuit diagram is lcated in Appendix B as Figure B. 10. Figure 2.19: Tp: Demdulated data signal, partially cnditined (amplifier Gain = 50) DC ffset = 7.3 vlts. Bttm: Fully cnditined data restred t 600 Hz TTL cmpatible vltage level. Oscillscpe settings: X = 0.1 msec/div., Y= 5 vlts/div.. Dppler shifts supprted by this design are minimal (apprximately 5 Hz at the chip rate f khz). This is f curse due t the nature f the VCO (inherently stable) and the minimal effect f the small range f capacitance ver which the varactr dide changes during feedback cntrl. A mre sphisticated VCO is clearly called fr in future design wrk cnsidering the ttal Dppler shift expected fr PANSAT. Hwever, the design described here remains cnsistent in 43

59 peratin and can be imprved using mre sphisticated cmpnents in the same applicatins as are develped here. Additinally, any significant Dppler shift encuntered in future applicatins f this design will require the additin f a buffer in rder t reestablish the 1200 bps data rate int the any interfacing device. 44

60 III. CONCLUSIONS A. GENERAL The basis fr this design cmes frm a brad spectrum f literature that fr the mst part deal with the theretical aspects f cmmunicatins systems. A large part f the develpment f the mdem design cntained here is the result f trial and errr using available cmpnents fr functinal realizatin f the design. The mdem perfrms extremely well in labratry EF lp-back testing. The nly bit errr rate testing perfrmed cnsists f the measurement f utput data cmpared t input data using the EF channel signal alne with n additive nise. This is nt a substantially rigrus testing prcedure and as expected the bit errr rate is significantly lwer than the perfrmance requirement dictated by the PANSAT design specificatins. The requirement fr PANSAT dictates a bit errr prbability f 10"6 r less. Tests under varius levels f additive nise will be needed t validate the final design but are nt cnducted fr this design. The final design will be mdified fr peratin ver an RF channel and will require greater frequency agility than demnstrated here. Therefre, any additinal bit errr rate testing will clearly be mre meaningful when implemented n the RF design. Additinally, a fading channel shuld be simulated t evaluate the verall perfrmance f the final mdem design. B. TECHNICAL 1. Circuit Sensitivity The feedback vltage t the scillatr cannt be measured during peratin if tracking is expected t be maintained. Any device cnnected t the center tap f the ptentimeter used t establish the dwell pint fr E-L feedback 45

61 will add stray capacitance t the circuit and thereby change the frequency f scillatin. This is due t the small range f the varactr capacitance. Since the varactr dide capacitance range is 22 t 440pf using the full range vltage cntrl f the device it is significant t nte that the vltage cntrl band changes apprximately 2 vlts yielding an verall change in the capacitance seen by the scillatr f abut 100 pic-farads. This small cntrl range aids in the tracking prcess and in this applicatin creates a mildly respnsive but sensitive tracking characteristic. 2. VCO Cntrl The plarity f the cntrlling vltage used in feedback must be maintained at a level such that the static cntrl-vltage/feedback-vltage sum used in the tracking mde f peratin remains a psitive quantity. This prtects the inverter used in the scillatr cnfiguratin. Additinally, the frequency is nly cntrllable if the center tap f the ptentimeter is cnnected t the utput terminal f the inverter used in parallel with the MHz crystal. Specifically, if vltage feedback cntrl as discussed here is used in the future design, any difficulties that arise relating t inability t maintain track r cmplete lack f feedback cntrl are undubtedly related t a large negative feeback vltage r an imprperly wired scillatr circuit (due t an imprperly biased varactr). Since it is expected that the VCO used in this design will be replaced in whle these particular prblems will be avided entirely. 3. Pwer Cnsumptin Clearly the design as stated is extrardinarily pwer inefficient and, by tday's standards, cnsidering the use f the integrated circuits emplyed here culd be imprved significantly. Several mdificatins t the existing design may be implemented immediately. The bvius nes are the use f CMOS vice standard TTL devices in all digital applicatins. It is significant t nte that in 46

62 many cases in this design the TTL cmpnents used are f the least pwer efficient variety and were chsen based n availability alne. At the very least a pwer savings culd be achieved by cnverting all 7400 series cmpnents t their 74LS00 equivalent cmpnents. Additinally, the threshld vltages established in the analg sectin are lwer than the +5 vlt pwer supply available and since resistance vltage dividers are emplyed t set these vltages mre pwer is lst by using the +15 vlt supply. This can be changed but as mentined in the design develpment, many f the analg cmpnents used here will be replaced in their entirety by either passive cmpnents (crystal filters and mixers) r pwer efficient amplifiers. These pints are nt imprtant as cncerns the functinality f the design r in the evaluatin f its peratinal characteristics (pwer cnsumptin aside). This design, as it is intended, prvides a particular slutin that is meant t lay the grundwrk leading t the final design. Clearly, substantial pwer savings can be achieved but, fr this design the imprtance lies in the realizatin f a functinal prttype and t this end the design is a success. 47

63 APPENDIX A. Functinal Blck Diagrms 48

64 E 03 D) 03 O "05 DC LU g(+hx)! c 4-* D "D O CVJ CO in Q. 0) c i- CM Q 9 z> < en * LU _ CO c Q a. Q- LU CD CO Q. CO Figure A.l 49

65 2 * w. + c CO Q_ 3CQj< "O < Q E 03 i_ D) 03 O C w CD»- O CD > C HI 0) CD Q r*(h CD >- CD Uj CD Q CD»- a CD > C + ' CD HI c k. O +-> CO +-> k_ CD c c U_ 3 CD Envelpe Detectr CD *~ Q +< CO k_ CO a E O "D OE Q Figure A. 50

66 APPENDIX B. Circuit Diagrams and Bill f Materials 51

67 '^- > CD (U c <D N > _c c_ ^ UD CO *-" LT> Ji «- CJ 8 a > Ifff iiitti IS 18 3SSs AA 1 t La»J 5 lull iiiffl IS 3SS! 5B M <S> CN 0) > < X CJ z > O z: < I < tn i < CD SAf «A 1 1^ 4= 5/\igaa 55-1! SCO 52

68 ' CD T3 O T3 OO c =h I * CL \ 54 s. 5 m «{** 6 sai?a 6 S8883SS8S Z ID 3 Q. -Q c CM «Q «H OOOl isss 5 5 < cc ^ LU ^ < Q UJ O 2^ Z -J LxJ <C CM QQ ' rsi 5c: -* u CD O m 53

69 ~ -) Q w_ U w (O CL I/) 3 CL CO > "1 i +1 l <J c 0) CL Q i > "I J n. ; : 5!*«" " 'I * " n ID - Q -1 <, 1^ a sisiai 8 * = 2 5 % i 5 1 Ol S > =i rn q^^qr S 5 s 1 vw Ft 1 UJ X Q < CC < 01 O h- t <_J Q O z> Li_ 0Q -> s r CJ c > CT 54

70 at < ( -z. I < X 00 Z> O cn 00 Ml 13' 55

71 ) I in c (0 V <u _3 f l c cr n (1> u > < t ^ z: ISI N 0- rr - _ i ^ *"' ^r s> -* m r^ < n K) f) < in u «CD i ^3 5 < X 2 I" < H- X) -Q <L) 0) > > b b <U "D E 0> 'J J ^- n O u Vt q; > n D u (d c i_ <D a c 3 3 CL c en D 2 a -i > ^u ^ UJ 0) a> la->attlq U I I 3 am ' *8 AA sai as II V / \ I CM( l(n D / \ jr x< Im ii ^^AL»ai iiiii 18 IS S3S 2 X C\J 0) > b in > Q cr Q 5 z: ~> < Q rr O 2 i LJ < Q _i _i 00 m QQ a

72 57 CL O C cr CD N &

73 a; > ^_/ i/i v. <i> <l> CL ±; LO M q> u *-' O a w T> 3 c r a. _Q i >> u k. a; UJ u c h c t _J c m H D U c Q_ c H i * s C LU X 5 n p < 1 [V ULA IGU Q ^- ^ :> UJ CJ Q P^ QQ a. "5 D U c J a. CL C (/) (St 58

74 59

75 i_ u 3 Q. 13 V D»m ui X01 6^a c: > w c J2 a; ^_ j>> \_ 60

76 61

77 , MODEM BILL OF MATERIALS. SCHEMATIC REPORT Quantity Type Value Ref. Designatrs 4 54HC04 U4,U7,U19,U HC109 U11,U HC112 U9,U U3,U U1,U U8,U10,U45,U U2,U5,U LS112 U21 4 AD534JD U15,U24,U25,U26 2 CAP O.lu C35,C38 3 CAP lu C30,C32,C40 18 CAP 30p C3,C5,C8,C9,C12,C13,C16, C17,C20,C21,C24,C25,C28, C29,C31,C33,C34,C39 4 CAP 47p C1,C2,C36,C37 1 CAP 60p C4 12 CAP 630p C6,C7,C10,C11,C14,C15,C18, C19,C22,C23,C26,C27 2 CRYSTAL MHz XI,X2 3 DIODE 1N914R D2,D3,D4 7 LM311P U6,U12,U20,U22,U23,U49, U51 18 LM318N Ul 3,U27,U28,U29,U30,U3 1 62

78 MODEM BILL OF MATERIALS (CONTINUED). SCHEMATIC REPORT Quantity Type Value Ref. Designatrs LM318N U32,U33,U34,U35,U36,U37, U38,U39,U40,U41,U42,U50 2 POT 100k R11,R84 7 POT 10k R5,R13,R25,R30,R35,R88, R95 12 POT Ik R6,R7,R12,R14,R26,R27,R31, R32,R36,R37,R86,R87 8 RES 100k R16,R75,R90,R9,R29,R34, R39,R97 13 RES 10k R71,R72,R73,R76,R77,R78, R79,R80,R8 1,R92,R93,R94, R74 1 RES 130k R70 35 RES Ik R1,R2,R3,R5,R15,R19,R21, R22,R23,R24,R40,R41,R42, R43,R45,R46,R47,R48,R50, R5 1,R52,R53,R55,R56,R57, R58,R60,R61,R62,R63,R65, R66,R67,R68,R89R8,R28, R33,R38,R96 2 RES 1M R10,R83 1 RES 240 R20 1 RES 240k R18 2 RES 30k R82,R85 1 RES 5.6k R17 6 RES 50k R44,R49,R54,R59,R64,R69 63

79 MODEM BILL OF MATERIALS (CONTINUED). SCHEMATIC REPORT Quantity Type Value Ref. Designatrs 1 RES 550K R91 1 SW-06 U43 2 VARACTOR pf Q1,Q2 Ttal Parts:

80 APPENDIX C. Furth Order Band-Pass Filter Cnstructin and Perfrmance 65

81 MATLAB PROGRAM FOR THE DEVELOPMENT OF BAND-PASS FILTERS DEPICTED IN THIS DESIGN. del thol la.met del thol lb.met els clear % Meta file t cntain utput. % Meta file t cntain utput. clg w = 2*pi*200e3:500:2*pi*300e3; s = j*w; wtl = 2*pi*15e6; %Set the value f Unity Gain BW fr the Op-amp wt2 = 2*pi*15e6; wol = 2*pi*251760; %w0 = (2*pi*254.6e3); % enter wo Q = 50; % enter Q R = 1000; C = (R*w01) A (-l); G = R A (-1); Al =wtl./s; A2 = wt2./s; Yl = G; Y2 = G; Y3 = C*s; Y4 = G; Y5 = 0; Y6 = G; Y8 = C*s; Y7 = G/Q; J =Y4+Y7+Y8; % enter resistance K =Y1+Y3; L =Y2+Y5+Y6; % NUM = ((K.*L.*Y7)./A1)+((Y2+Y6).*Y3.*Y7)+(Y1.*Y4.*Y5)... -(Y3.*Y5.*Y8); DEN = ((J.*K.*L)./(A1.*A2))+((J.*L.*Y1)./A1)+((J.*L.*Y3)./A2)... +((Y7+Y8).*Y2.*Y3)+((Y5+Y6).*Y1.*Y4); Tl = (NUM./DEN); Tla = sqrt((real(tl)). A 2+(imag(Tl)). A 2); % R = 1000; w02 = 2*pi*255760; C = (R*w02) A (-l); G = R A (-1); % enter resistance 66

82 Al = wtl./s; A2 = wt2./s; Y1=G; Y2 = G; Y3 = C*s; Y4 = G; Y5 = 0; Y6 = G; Y8 = C*s; Y7 = G/Q; J =Y4+Y7+Y8; K =Y1+Y3; L =Y2+Y5+Y6; % NUM = ((K.*L.*Y7)./A1)+((Y2+Y6).*Y3.*Y7)+(Y1.*Y4.*Y5)... -(Y3.*Y5.*Y8); DEN = ((J.*K.*L)./(A1.*A2))+((J.*L.*Y1)./A1)+((J.*L.*Y3)./A2) +((Y7+Y8).*Y2.*Y3)+((Y5+Y6).*Y1.*Y4); T2 = (NUM./DEN); T2a = sqrt((real(t2)). A 2+(imag(T2)). A 2); x = [242.6e e e e3]; y = [ ]; plt(w/(2*pi),20*lglo(tla),w/(2*pi),20*lglo(t2a),x,y); title('cascaded 2nd ORDER BP filters, Q=50'); xlabel('freq HZ'); ylabel('magnitude db'); grid metatholla T12 = T1.*T2; T12a = sqrt((real(t12)). A 2+(imag(T12)). A 2); plt(w/(2*pi),20*lg 1 0(T1 2a),x,y); title('4th ORDER BPF, f0=245.76khz, Q=50'); xlabel('freq HZ'); ylabek'magnitude db'); grid metathollb 67

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85 LIST OF REFERENCES 1. R.C. Dixn, Spread Spectrum Systems, Wiley, New Yrk, L.W. Cuch II, Digital and Analg Cmmunicatin Systems, Macmillan, New Yrk, T.T. Ha, Digital Satellite Cmmunicatins, McGraw- Hill, New Yrk, R.L. Freeman, Radi System Design fr Telecmmunicatins, Wiley, New Yrk, R.F. Cughlin, and F.F. Driscll, Operatinal Amplifiers and Linear Integrated Circuits, Prentice Hall, Englewd Cliffs, New Jersey, C.L. Hutchinsn and J. P. Kleinman, Eds., "The ARRL Handbk fr Radi Amateurs," American Radi Relay League, Newingtn, Cnnecticut, "Mtrla Linear and Interface Integrated Circuits, Series G, Mtrla, Inc., P. Hrwitz and W. Hill, The Art f Electrnics, 2ed, Cambridge University Press, Cambridge, Massachusetts, Internally Trimmed Precisin IC Multiplier AD534 Data Sheet, Analg Devices, Nrwd, Massachusetts, undated. 10. H.B. Killen, Digital Cmmunicatins and Fiber Optics and Satellite Applicatins, Prentice Hall, Englewd Cliffs, New Jersey, S. Michael and P. Andresakis, "Digitally Cntrlled Prgrammable Active Filters," 19th Annual Asilmar Cnference n Circuits, Systems and Cmputers Prceedings, Pacific Grve, Califrnia, S. Michael, Advanced Netwrk Thery, EC 4100 class ntes, Naval Pstgraduate Schl, Mnterey, Califrnia, B. Sklar, ntes frm "A Primer n Digital Cmmunicatins Signal Prcessing," The Aerspace Crpratin, Ls Angeles, Califrnia, unpublished. 70

86 INITIAL DISTRIBUTION LIST Defense Technical Infrmatin Center Camern Statin Alexandria, Virginia Library, Cde 52 Naval Pstgraduate Schl Mnterey, Califrnia Chairman, Cde EC Department f Electrical and Cmputer Engineering Naval Pstgraduate Schl Mnterey, Califrnia Prf. T. Ha, Cde EC/Ha Department f Electrical and Cmputer Engineering Naval Pstgraduate Schl Mnterey, Califrnia Prf. R. Panhlzer, Cde SP Department f Electrical and Cmputer Engineering Naval Pstgraduate Schl Mnterey, Califrnia LT Thmas Fritz Irngate 500 Essex Drive Summerville, SC LCDR Steve Paluszek Naval Security Grup Supprt Activity Nebraska Ave. N.W. Washingtn, DC

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