US B2. (12) United States Patent Baker. (10) Patent No.: US 9,081,042 B2 (51) Int. Cl. G11C G01R G11C G11C U.S. Cl.

Transcription

1 US B2 (12) United States Patent (10) Patent.: (45) Date f Patent: *Jul. 14,2015 (54) RESISTIVE MEMORY ELEMET SESIG USIG AVERAGIG (71) Applicant: MICRO TECHOLOGY, IC., Bise, ID (US) (72) Inventr: R. Jacb, Meridian, ID (US) (73) Assignee: MICRO TECHOLOGY, IC., Bise, ID (US) ( *) tice: Subject t any disclaimer, the term f this patent is extended r adjusted under 35 U.S.c. 154(b) by 0 days. (21) Appl..: ,719 (22) Filed: Mar. 21, 2014 This patent is subject t a terminal disclaimer. (65) Prir Publicatin Data US 2014/ Al lui. 17,2014 Related U.S. Applicatin Data (60) Divisin f applicatin. 13/868,544, filed n Apr. 23,2013, nw Pat.. 8,711,605, which is a divisin f applicatin. 12/504,851, filed n lui. 17,2009, nw Pat.. 8,441,834, which is a divisin f applicatin. 12/049,426, filed n Mar. 17, 2008, nw Pat.. 7,577,044, which is a cntinuatin f applicatin. 11/115,281, filed n Apr. 27, 2005, nw Pat.. 7,372,717, which is a divisin f applicatin. 10/674,550, filed n Oct. 1,2003, nw Pat.. 7,133,307, which is a cntinuatin f applicatin. 10/290,297, filed n v. 8, 2002, nw Pat.. 6,822,892, which is a cntinuatin f applicatin ,617, filed n Aug. 27, 2001, nw Pat.. 6,504,750. (51) (52) (58) (56) Int. Cl. G11C G01R G11C G11C U.S. Cl. ( ) ( ) ( ) ( ) CPC G01R ( ); G11C ( ); G11C ( ); G11C ( ); GllC ( ) Field f Classificatin Search CPC. GIIC 13/002; GIIC 13/004; GllC 13/0061 USPC ,189.07,189.09,233.17, 365/233.1,236 See applicatin file fr cmplete search histry. 4,190,823 A 4,718,036 A References Cited U.S. PATET DOCUMETS 2/1980 Leichle Halbert et al. (Cntinued) Andrew Q Tran Primary Examiner - (74) Attrney, Agent, r Firm - Dickstein Shapir LLP (57) ABSTRACT A system fr determining the lgic state f a resistive memry cell element, fr example an MRAM resistive cell element. The system includes a cntrlled vltage supply, an electrnic charge reservir, a current surce, and a pulse cunter. The cntrlled vltage supply is cnnected t the resistive memry cell element t maintain a cnstant vltage acrss the resistive element. The charge reservir is cnnected t the vltage supply t prvide a current thrugh the resistive element. The current surce is cnnected t the charge reservir t repeatedly supply a pulse f current t recharge the reservir upn depletin f electrnic charge frm the reservir, and the pulse cunter prvides a cnnt f the number f pulses supplied by the current surce ver a predetermined time. The cunt represents a lgic state f the memry cell element. 12 Claims, 6 Drawing Sheets 2.5 v

2 Page 2 (56) References Cited 5,329,480 A 5,754,470 A 5,805,871 A 5,999,454 A 6,038,166 A 6,128,239 A 6,188,615 Bl 6,259,644 Bl 6,317,375 Bl u.s. PATET DOCUMETS Wu et al Engh et al Baxter Smith 3/2000 Wng Pemer Pemer et al. 7/2001 Tran et al Pemer 6,317,376 Bl 6,385,111 B2 6,462,979 B2 6,504,750 Bl 6,778,430 B2 6,822,892 B2 6,914,839 B2 7,133,307 B2 7,372,717 B2 7,577,044 B2 8,441,834 B2 8,711,605 B2 * * cited by examiner / / /2008 8/2009 5/2013 4/2014 Tran et al. Tran et al. Schlsser et al. Hidaka Chw et al /148

3 FIG. 1 (PRIOR ART) 11 0 COLUM LIES ;90 7Jl = tf\ -t I 2- : Ul 100,,- ROW LIES rfj ('D = ('D. 0\ I I \V 120 d rjl \C -= QO """'" -= =

4 FIG Jl = 2- :-... Ul rfj ('D = ('D. 0\ ;215 d rjl \C -= QO """'" -= =

5 u.s. Patent Jul. 14,2015 Sheet 3 f 6 r> 0 (V') <!> r.c l. ")..- "-f l..- C"-.I r> 0 l. ")..-- "-f l 0 <:) tr) 0 r "-f LO "-f

6 Cal 565 ri-r FIG. 4 F--- -7RO /500 7Jl = 2- :-... Ul rfj = ('D ('D.... 0\ d rjl \C -= QO """'" -= =

7 u.s. Patent Jul. 14,2015 Sheet 5 f 6 FIG. 5 v Vut A time ns B C «u w ::c I- if) if) a:: u «w ;::; -.J v FIG. 6 Vut I I I I I I I I I I I t i t I I ttl t t t t I I t t t tit I t I -t t tit t t t,t, I, t t l i I I, Itt t I I t I t ttl O 60. O.O----t I l-00: i5().O cKl. A Be

8 u.s. Patent Jul. 14,2015 Sheet 6 f 6 FIG CPU DISK STORAGE DIGITAL MEMORY I/ 1230 USER 1260 ITERFACE 1240

9 1 RESISTIVE MEMORY ELEMET SESIG USIG AVERAGIG The present applicatin is a divisinal f U.S. patent applicatin Ser.. 13/868,544, filed Apr. 23, 2013, which is a divisinal f u.s. patent applicatin Ser.. 12/504,851, filed lui. 17,2009, nw U.S. Pat.. 8,441,834, which is a divisinal f u.s. patent applicatin Ser.. 12,049,426, filed n Mar. 17,2008, nw U.S. Pat.. 7,577,044, which is a cntinuatin f U.S. patent applicatin Ser ,281, filed n Apr. 27, 2005, nw U.S. Patent. 7,372,717, which is a divisinal f U.S. patent applicatin Ser.. 10/674,550, filed n Oct. 1,2003, nw U.S. Pat.. 7,133,307, which is a cntinuatin f U.S. patent applicatin Ser.. 10/290,297, filed n v. 8, 2002, nw U.S. Pat.. 6,822,892, which is a divisinal f U.S. patent applicatin Ser ,617, filed n Aug. 27, 2001, nw U.S. Pat.. 6,504,750, the entire disclsures f each f which are incrprated herein by reference. BACKGROUD OF THE IVETIO 1. Field f the Inventin The present inventin relates t the field f resistr-based memry circuits. Mre particularly, it relates t a methd fr precisely sensing the resistance value f a resistr-based 25 memry cell, fr example, an MRAM magnetic memry cell. 2. Descriptin f the Related Art FIG. 1 shws ne example f a resistr based memry. The memry includes a memry cell array 90 having a plurality f rw lines 100 arranged in nrmal rientatin t a plurality f clunm lines 110. Each rw line is cnnected t each f the 30 clunm lines by a respective f resistr 120. A magnetic randm access memry (MRAM) is ne apprach t implementing a resistr based memry. In an MRAM, each resistive memry cell includes a magnetizable film. The resistance f the cell varies, depending n the magnetizatin state f the film. Lgical data can be stred by magnetizing the film f particular cells s as t represent the lgic states f the data. The stred data can be read by measuring the resistance f the cells, and interpreting the resistance values measured as lgic states. Making the required 40 resistance measurements, hwever, is prblematic. In a resistance memry, ne resistance value, e.g., a higher value, may be used t signify a lgic "HIGH" while anther resistance value, e.g., a lwer value, may be used t signify a lgic "LOW." The stred lgic state can be detected by mea- 45 suring the memry cell resistance using Ohm's law. Fr example, resistance is determined by hlding vltage cnstant acrss a resistr and measuring, directly r indirectly, the current that flws thrugh the resistr. te that, fr MRAM sensing purpses, the abslute magnitude f resistance need nt be knwn; nly whether the resistance is abve 50 r belw a value that is intermediate t the lgic high and lgic lw values. Sensing the lgic state f an MRAM memry element is difficult because the technlgy f the MRAM device impses multiple cnstraints. In a typical MRAM device an 55 element in a high resistance state has a resistance f abut 1 MQ. An element in a lw resistance state has a resistance f abut 950 KQ. The differential resistance between a lgic ne and a lgic zer is thus abut 50 KQ, r 5% f scale. Accrdingly, there is a need fr a simplified resistance 60 measuring circuit able t repeatably and rapidly distinguish resistance values varying by less than 5% n a ne MQ scale. BRIEF SUMMARY OF THE IVETIO The inventin prvides a methd and apparatus fr measuring the resistance f a resistive memry element. The 2 resistance is measured by charging a capacitr, allwing the capacitr t discharge thrugh a selected resistive memry element while maintaining a substantially cnstant vltage acrss the resistive memry element, sensing the charge remaining n the capacitr, repeatedly recharging the capacitr with a pulse f definite charge each time the capacitr vltage drps t a predetermined value, and determining a time average current int the capacitr based n a duty cycle f the recharging pulses. Knwledge f the time average 10 current int the capacitr, yields the current flwing int the resistr since the current flwing int the capacitr must equal the current flwing ut f the capacitr and int the resistr. One can measure r set the vltage acrss the resistive memry element and determine the resistance f the element 15 frm the current thrugh the element and the vltage acrss it. In varius aspects f the inventin, the actual resistance f the memry element is nt calculated. Instead, the number f capacitr charging pulses is cunted, and the numerical cunt thus acquired is cmpared t a reference cunt value. The 20 reference value is chsen t lie between cunt values representing lgical ne and lgical zer. Therefre a cunt value greater than the reference indicates ne lgical state, and a cunt value less than the reference value indicates anther. In a further aspect f the inventin, mre than ne reference value is established, and a memry element capable f exhibiting mre than tw resistance values is used. Cnsequently the memry element may stre mre than tw lgical values. The lgical values are determined based n the relatinship between the cunt value cunted and the standard values used t establish threshlds between lgical values. In a further aspect, the apparatus and methd f the inventin may be used t measure the resistance r impedance f any resistive r impedance device. These and ther aspects and features f the inventin will 35 be mre clearly understd frm the fllwing detailed descriptin which is prvided in cnjunctin with the accmpanying drawings. BRIEF DESCRIPTIO OF THE DRAWIGS FIG. 1 shws a cnventinal magnetic randm access memry array in schematic frm; FIG. 2 shws a magnetic randm access memry device accrding t ne aspect f the present inventin in schematic frm, including resistance sensing circuits; FIG. 3 shws a prtin f a magnetic randm access memry device accrding t ne aspect f the inventin including a sensing circuit and sneak resistance; FIG. 4 shws a circuit fr sensing resistance using averaging accrding t ne aspect f the present inventin; FIG. 5 shws a graphical representatin f sensing circuit digital utput ver time accrding t ne aspect f the present inventin; FIG. 6 shws a graphical representatin f vltage acrss a capacitr ver time accrding t ne aspect f the present inventin; FIG. 7 shws a cmputer system incrprating a digital memry accrding t ne aspect f the present inventin. DETAILED DESCRIPTIO OF THE IVETIO FIG. 2 shws a prtin f a resistive memry device accrding t the inventin. The device includes an array 200 f Magnetic Randm Access Memry (MRAM) elements, a 65 plurality f electrically cnductive rw lines 210, and a plurality f electrically cnductive clunm lines 220. Each rw line is cnnected t each f the plurality f clunm lines by a

10 3 4 respective MRAM resistive element 230. A plurality f switches 240, typically implemented as transistrs, are each switchingly cnnected between ne f the rw lines and a first surce f cnstant ptential (grund) 250. A plurality f sensing circuits 260, are respectively cnnected t the plurality f clunm lines 220. Each sensing circuit 260 includes a surce f cnstant electrical ptential (V A) which is applied t the respective clumn line. A plurality f pull-up vltage surces 215, supplying vltage VA' are respectively cnnected t each f the plurality f rw lines 210. In peratin, an exemplary switch 240, such as switch 270 assciated with a particular rw line 280, is clsed s as t bring that rw line t grund ptential and a particular clunm line, e.g., 320 is sensed t read the resistance value f a particular resistr 310. FI G. 3, shws the resulting electrical circuit fr the relevant prtin 300 f the memry array when rw 280 is grunded. As shwn, memry element 310 t be sensed is cnnected between a grunded rw line 280 and a particular clunm line 320. Als cnnected t the clunm line 320 are a plurality f ther resistive memry elements (e.g. elements 330, 340, 350,360,370) each f which is cnnected at its ppsite end t a pull-up vltage surce VA 215 thrugh a respective rw line 210. In additin, a respective sensing circuit 400 is cn- 25 nected t the clunm line 320. The sensing circuit 400 includes a vltage supply that maintains the clunm line 320 at electrical ptential VA' The ther resistive memry elements (thse tied t ungrunded rw lines) 330, 340, 350, 360, 370, frm an 30 equivalent resistance referred t as sneak resistance. The effective resistance f the sneak resistance is small. A typical value fr sneak resistance might be 1 KQ. evertheless, because bth ends f each ungrunded resistr are ideally maintained at the same ptential (here V A) as the clunm line , net current flw thrugh the sneak resistance is desirably nearly zer. In cntrast, a measurable current flws thrugh the grunded resistr memry element 310. This measurable current allws evaluatin f the resistance f the memry ele- 40 ment 310 by the sensing circuit 400. One prpsal fr sensing the resistance value f a memry cell is t charge a capacitr t a predetermined first vltage and then discharge the capacitr thrugh the memry cell resistance until it hlds a secnd lwer predetermined vltage. The time taken fr the capacitr t discharge frm the first t the secnd vltage is a measure f cell resistance. A prblem with this apprach is that since the resistance values representing the different lgic states f a cell are very clse in value (nly 5% difference) it is difficult t btain an accu- 50 rate and reliable resistance measurement, even if digital cunting techniques are emplyed t measure the discharge time f the capacitr. Thus, even when using digital cunting techniques, the discharge time f the capacitr must be cunted quite pre- 55 cisely t sense the different resistance values and distinguish lgic states. T achieve this precisin, either the cunting clck must be perated at a high frequency r the capacitr must be discharged relatively slw ly. either f these ptins is desirable, since slw capacitr discharge means slw read- 60 ing f stred memry values, and a high clck frequency requires high frequency cmpnents. In either case, a cunter having a large number f stages is als required. The present inventin prvides a resistive measuring circuit and perating methd which rapidly ascertains a resistive 65 value withut string large data cunts, and withut requiring highly precisined cmpnents. FIG. 4 illustrates an exemplary embdiment f a resistance sensing circuit 500 cnstructed in accrdance with the inventin. Sensing circuit 500 relies n the cyclical discharge f a capacitr 510 t detennine the value f a memry cell resistance 520. The duty cycle f a recharging signal fr the capacitr 510 represents a value f resistance 520. The resistance measuring circuit 500 utputs a bit stream frm an utput 900 f a cmparatr 910. The rati flgic ne bits t a ttal number f bits (r, in and ther aspect f the 10 inventin, the rati flgic ne bits t lgic zer bits) in the bit stream yields a numerical value. This numerical value crrespnds t the current that flws thrugh the resistance 520 in respnse t a knwn applied vltage. Fr example, assume that a current surce can deliver current at tw dis- 15 crete current levels, crrespnding t tw different states f a lgical input signal. When the signal is in lgic ne state, the surce delivers, fr example, 2 fla. When the signal is in a lgic zer state, the surce delivers, fr example, 0 fla. The lgical input signal is mnitred ver a finite time span cr- 20 respnding t a number f bit-length time perids. Over that time span, the number f lgic ne and lgic zer bits are recrded. By straightfrward algebra, the average current delivered by the current surce ver the crrespnding time span may be calculated as fllws: LA V G = (nwnber f lgic I bits) * 2 fla + (number f lgic 0 bits) * 0 fla ttal number f bits in the signal As an example, if, ver a time span crrespnding t 4 cycles, there is ne lgic ne bit and three lgic zer bits then the average current ver the fur cycles is 0.5 fla. The peratin f the FI G. 4 sensing circuit is nw described in greater detail. An MRAM resistive memry element 520 t be sensed has a first end 530 cnnected t a clunm line 540 and a secnd end 550 cnnected t grund 250 thrugh a rw line 560 and switch 565. Als cnnected t the clunm line is a first end 570 f a sneak resistance 580. The sneak resistance has a secnd end 590 cnnected t a surce f cnstant ptential VA 215. The sneak resistance 580 represents a plurality fmram resistive elements assciated with the particular clunm line 540 and with a respective plurality f unselected rw lines, as described abve with reference t FIG. 3. A first peratinal amplifier (p-amp) integratr 600 is prvided which has a nn-inverting (psitive) input 610, an inverting (negative) input 620, a calibrate ffset input 630, and an utput 640. The utput 640 f the first p-amp 600 is cnnected t a cntrl input (gate) 700 f a first transistr 71 0, which in this exemplary embdiment is an -channel transistr. The first transistr 710 includes a drain 720 cnnected t bth the selected clunm line 540 and the inverting input 620 f the first p-amp 600. The first transistr als includes a surce 730 peratively cnnected t a first tenninal 740 f a capacitr 510. The capacitr 510 includes a secnd tenninal 750 peratively cnnected t a grund ptential 250. The surce 730 f the first transistr 710 is als cnnected t a drain 760 f a secnd transistr 770. In this exemplary embdiment, this secnd transistr 770 is a PMOS transistr.

11 5 6 The secnd transistr 770 includes a surce 780 and a gate psitive, the secnd cunter 1010 is incremented. When the 790, in additin t the drain 760. The surce 780 is pera- secnd cunter 1010 reaches a preset value, it triggers the tively cnnected t a supply vltage 800, which in this exem- latch 1050, which latches that number f pulses cunted by plary embdiment is 2.5 vlts. The gate 790 is peratively the first cunter 1000 during the sensing perid. The number cnnected t an utput 900 f a clcked cmparatr 910. The 5 f pulses cunted is latched nt the data utput 1070 (and clcked cmparatr 910, shwn as a clcked secnd pera- data input 1090). The cmparatr 1100 then evaluates the tinal amplifier, includes the utput 900, a nn-inverting values presented at the first and secnd data inputs 1090, (psitive) input 920, an inverting (negative) input 930, and a 1110, and ascertains whether the value at the first data input clck input 940 cnnected t a surce f a clck signal is larger r smaller than the reference value at the secnd Thecmparatr910maybeimplementedasasimpleclcked 10 data input The reference value at input 1110 is set latch, r the cmparatr 910 may be simply enabled by the between tw cunt values which crrespnd t "hi" and clck CLK signal. "lw" resistance states fr resistr 520. Thus if the value f The utput 900 f the secnd p-amp is als cnnected t a cunter 1000 which cunts the rising transitins at the the first datainputl090 is larger than the reference value, then cmparatr utput 900. The nn-inverting input 920 f the 15 a first lgical value (e.g. lgic ne) is utput n an utput 1140 secnd p-amp 910 is cnnected t a surce f a reference f the digital cmparatr If the value f the first data vltage 960 (1 vlt in the exemplary embdiment shwn). input 1090 is smaller than the reference value, then a secnd A secnd cunter 1010 cnnts the ttal number f trans i- lgical value (e.g. lgic zer) is utput n the utput 1140 f tins f the clck 950 during a measuring cycle. This cunter the digital cmparatr In a variatin, a cmparatr includes an input 1020 fr receiving clck signal capable f cmparing the digital value applied at the data and at utput 1030 that exhibits a signal when cnnter 1010 input 1090 t a plurality f reference values 1110 can distinreaches a predetermined cunt. The utput 1030 is cnnected guish a value stred in a single resistive memry element as t a latch input 1040 f a latching buffer The latching between multiple resistance values. In a further variatin, the buffer 1050 includes a data input 1060 and data utput capacitr 510 is pre-charged prir t a measuring cycle. By The data input 1060 is cnnected t a data utput 1080 f the 25 pre-charging the capacitr 510, the number f cycles f the first cunter The data utput 1070 is cnnected t a first clck signal 950 required t measure the state f the memry data input 1090 f a digital cmparatr The digital element is reduced. In anther variatin the capacitr is nt cmparatr 1100 includes a secnd data input 1110 cn- pre-charged, in which case sensing the resistance f the nected t a data utput 1120 f a surce f a reference value memry element takes lnger, but the circuitry and/rprcess In ne embdiment, the surce f the reference value 30 is simplified is a buffer r ther device hlding a digital number. FIGS. 5 and 6 shw an exemplary relatinship between the The sensing circuit 500 perates in the fllwing manner utput signal prduced at utput 900 f the clcked cmparawhen activated when a rw line is grunded and a resistance tr 910 and the vltage n capacitr 510 ver time. FIG. 5 value is t be sensed. Capacitr 510 is initially discharged, shws the utput signal prduced by the clcked cmparatr resulting in a negative utput signal n the utput 900 f the 35 when a 100 MHz clck signal is applied t the clck input secnd p-amp 910. This causes the secnd transistr 770 t 940. At a clck frequency f 100 MHz, clck pulses are be placed in a cnductive state, permitting capacitr 510 t spaced at an interval f 10 ns. In the example shwn, the begin charging. When the vltage n capacitr 510 equals utput f the clcked cmparatr is high 1160 fr ne clck that applied t the nn-inverting input 920 f the secnd pulse (10 ns) and lw 1170 fr three clck pulses (30 ns). This p-amp 910 (here 1 vlt), the utput 900 f the secnd p- 40 crrespnds t the vltage wavefrm shwn in FIG. 6. In FIG. amp changes state t a psitive value at the next transitin f 6, the vltage f the capacitr 510 is shwn t begin rising the clck 950. This turns ff the secnd transistr 770. The when the utput 900 f the clcked cmparatr ges lw charge stred n capacitr 510 is discharged thrugh the first (time A), thereby turning n the PMOS transistr 770. The transistr 710 and cell resistance 520 nnderthe cntrl f the vltage rises fr 30 ns, r three clck pulses nntil time B. At first p-amp 600. The first p-amp 600 tries t maintain a 45 time B, the utput f the clcked cmparatr ges high again, cnstant vltage VA n the selected clunm line 540. turning ff the PMOS transistr. The vltage n the capacitr As charge is depleted frm capacitr 510 the vltage n the 510 then begins t drp again while the PMOS device capacitr drps until it falls belw the vltage (1 vlt) applied remains ff fr ne clck pulse, r 10 ns (nntil time C). t the reference input 920 f the clcked cmparatr 910. Accrdingly, in the example shwn, the duty cycle f the After this threshld is passed, the next psitive clck transi- 50 signal utput by the clcked cmparatr 910 is 75% (three tin applied t the clck input 940 causes the utput f cm- n-pulses fr every ff-pulse). paratr 910 t g lw again turning n the secnd transistr FIG. 9 shws a cmputer system 1200 including a digital 770 and causing current t begin flwing thrugh the secnd memry 1210 having a resistance measuring memry cell transistr 770 t recharge capacitr 510. sensr accrding t the inventin. The cmputer 1200, as In ne embdiment, the capacitr 510 is recharged during 55 shwn includes a central prcessing unit (CPU) 1220, fr ne clck cycle f clck surce 950, s the cmparatr utput example, a micrprcessr, that cmmunicates with ne r 900 switches t high and the secnd transistr 770 is shut ff mre input/utput (I/O) devices 1230 ver a bus The again at the next psitive clck transitin. Transistr 770 is cmputer system als includes peripheral devices such as sized t allw a substantially cnstant current (e.g., 2.5 fla) t disk strage 1250 and a user interface It may be desirflw t capacitr 510 when transistr 770 is in a cnductive 60 able t integrate the prcessr and memry n a single IC state. chip. The described charging and discharging f capacitr 510 While preferred embdiments f the inventin have been under the cntrl f the first 710 and secnd 770 transistrs described and illustrated abve, it shuld be understd that ccurs repeatedly during ne sense cycle. Each time the ut- these are exemplary f the inventin and are nt t be cnput f the cmparatr 910 ges lw, a current pulse is allwed 65 sidered as limiting. Additins, deletins, substitutins, and t pass thrugh the secnd transistr 770 and the first cunter ther mdificatins can be made withut departing frm the 1000 incremented. Each time the clck signal 950 transitins spirit r scpe f the present inventin. Accrdingly, the

12 7 inventin is nt t be cnsidered as limited by the freging descriptin but is nly limited by the scpe f the appended claims. The inventin claimed is: 1. A methd f measuring a resistance in a circuit, cmprising: maintaining a substantially cnstant vltage acrss the circuit; repeatedly charging and discharging a capacitance thrugh 10 the circuit; determining a value f a time-average current int the capacitance in respnse t repeatedly charging and discharging the capacitance during a set time perid; and determining the resistance in the circuit based n the value f the time-average current. 2. The methd f claim 1, wherein repeatedly charging and discharging the capacitance cmprises the act f sensing the charge remaining n the capacitance while discharging the capacitance. 3. The methd f claim 2, wherein the act f repeatedly charging and discharging the capacitance cmprises recharging the capacitance with a recharging pulse each time the capacitance vltage drps t a predetermined value. 4. The methd f claim 3, wherein the act f determining 25 the value f the time-average current cmprises determining a duty cycle f the recharging pulses. 5. A resistance measuring circuit, cmprising: a resistance electrically cupled between a rw line and a clumn line f a memry cell array; a capacitance having first and secnd ndes; an peratinal amplifier having negative feedback and electrically cupled t the resistance t maintain a cnstant vltage acrss the resistance when the capacitance is discharged; a first transistr electrically cupled t the capacitance t prvide a recharging pulse t the capacitance when a vltage acrss the first and secnd ndes is less than a reference vltage; a secnd transistr electrically cupled t the capacitance t enable the capacitance t be discharged thrugh the resistance when the vltage acrss the first and secnd ndes is greater than the reference vltage; and a circuit electrically cupled t the first transistr t determine a time average current int the capacitance based n a duty cycle f the recharging pulses The resistance measuring circuit f claim 5 wherein the circuit determines a value f the resistance based n the time average current and the cnstant vltage. 7. The resistance measuring circuit f claim 5, wherein the circuit cmprises: a cunter electrically cupled t the first transistr t cunt the recharging pulses fr a perid f time; and a cmparatr electrically cupled t the cunter t cmpare the cunt with a reference cunt t determine the time average current. 8. A resistance measuring circuit, cmprising: a resistance electrically cupled between a rw line and a clumn line f a memry cell array; a capacitance having first and secnd ndes; an peratinal amplifier having negative feedback and electrically cupled t the resistance t maintain a cnstant vltage acrss the resistance when the capacitance is discharged; a first switch electrically cupled t the capacitance t prvide a recharging pulse t the capacitance when a vltage acrss the first and secnd ndes f the capacitance is less than a reference vltage; a secnd switch electrically cupled t the capacitance t enable the capacitance t be discharged thrugh the resistance when the vltage acrss the first and secnd ndes f the capacitance is greater than the reference vltage; and a circuit electrically cupled t the first switch t cunt the recharging pulses fr a perid f time and t determine a lgical state indicated by the cunt. 9. The resistance measuring circuit f claim 8, wherein the cunt indicates a first lgical state if the cunt is greater than a reference cunt, and wherein the cunt indicates a secnd lgical state if the cunt is less than the reference cunt. 10. The resistance measuring circuit f claim 8, wherein 35 the first switch cmprises a transistr. 11. The resistance measuring circuit f claim 8, wherein the secnd switch cmprises a transistr. 12. The resistance measuring circuit f claim 8, wherein the circuit cmprises: 40 a cunter electrically cupled t the first switch t cunt the recharging pulses fr a perid f time; and a cmparatr electrically cupled t the cunter t cmpare the cunt with a reference cunt t determine the lgical state. * * * * *