A Low Cost DC-DC Stepping Inductance Voltage Regulator With Fast Transient Loading Response

Transcription

1 A w Cst DC-DC Stepping Inductance Vltage Regulatr With Fast Transient ading Respnse.K. Pn C.P. iu M.H. Png The Pwer Electrnics abratry, Department f Electrical & Electrnic Engineering The University f Hng Kng, Pkfulam Rad, Hng Kng nkpn@eee.hku.hk Abstract A fast transient cnverter mdified frm a buck cnverter is prpsed. It emplys stepping inductance methd by which the utput inductr f a buck cnverter is replaced by tw inductrs cnnecting in series. One has large inductance and the ther has small inductance. Inductr with small inductance will take ver the utput inductr during transient lad change and speed up dynamic respnse. In steady state the large inductance takes ver and keeps substantially small ripple current and minimize RMS lss. An experiment f a V DCDC cnverter put under a 0A transient lad change demnstrates the merit f this apprach. It is a lw cst methd applicable t cnverters with an utput inductr. I. ITRODUCTIO Fast transient respnse under fast lad change is a crucial issue in DC-DC cnverter with mdern micrprcessr. The lad current may change between full lad and nearly n lad cnditin within nan-secnds range. This fast lad change demands the utput terminal f the pwer supply t deliver full lading current, e.g. 0A, within nan-secnds time range. Althugh decupling capacitr becmes a necessary methd t reduce the need f very high slew rate utput current regulatr, the requirement f such regulatr still need t supply current at a slew rate f 150A/us. It is bvius that the barrier f utput current slew rate is determined by the equivalent inductance f the regulatr. Reducing utput inductance is a way t cmpile the specificatin. Hwever, just decrease the utput inductance will prduce side effects such as high ripple current. Switching cnverter engineers are facing a new design challenge t prvide high utput current slew rate and maintain lw ripple current, lw ripple vltage and high efficiency. Reducing utput inductance f single cnverter may increase the utput current slew rate, but this methd will als prduce higher ripple vltage and ripple current which is nt acceptable. evertheless, it is pssible t parallel several cnverters and each cnverter has a relatively large utput inductance. This parallel cnverter apprach can flexibly increase utput current slew rate by increasing the number f parallel cnverters. Interleaving parallel cnverter [1][] is ne special frm f parallel cnverter cnfiguratin which prduces equivalent small utput inductance. This apprach can help slve the higher ripple vltage by using cmplicated cntrl circuit. It gives gd perfrmance during transient cnditin, hwever the steady state perfrmance is still nt satisfactry due t higher lsses. Prir wrk [3][4] shw a methd f using a paralleled linear regulatr t clamp the utput vltage within a certain limit. It gives very gd perfrmance during steady state peratin but it is theretically dissipative during transient cnditin, althugh the lss is very small. A fast transient cnverter using stepping inductance is prpsed in this paper. It is theretically lssless, and is able t prduce high slew rate utput current and the result is cmparable t the abve tw appraches. It is lw cst and easy t implement. II. BASIC IDEA The fllwing shws the basic cnfiguratin f the stepping inductance cnverter. Here nly psitive change f current is described. M aux S 1 V S (a (b (c Fig. 1 Stepping inductance cnverter, a Basic cnfiguratin b Equivalent circuit during transient c simplified peratin Fig. 1a shws the basic cnfiguratin f the stepping inductance cnverter, switches, M, utput series inductrs, r and utput capacitr C frm and perate as a basic DCDC buck cnverter. Inductr r is chsen t be V 1 D r D 1 M r - V 1 I I r C R 1 R S S C R 1 R I I r S 1

2 much smaller than. Inductr aux, is magnetically cuple with. aux, V 1, V, S 1 and S frm an auxiliary circuit t shrt circuit the large value inductr during lad transient. S 1 is prgrammed t turn n during a fast and large increase in lad current, S is prgrammed t turn n during a fast and large decrease in lad current. The number f turns f aux is chsen t reduce the reflected current flw thrugh S 1, S in rder t reduce their cnductin lsses. Fig. 1b shws the equivalent circuit when S 1 is turned n under a step and large increase in lad current. Once S 1 is turned n, the equivalent ttal utput inductance will change frm r t a much smaller r. This increases utput inductr current slew rate in the perid where transient ccurred. This will result in much reduced vltage deviatin due t large step change in lad current. Fig. 1c shws the peratin f the fast transient cnverter by varius wavefrms. When the lad current increase in a step, the utput vltage starts t drp accrdingly. The auxiliary switch S 1, with an series vltage surce V 1, is prgrammed t turn n in rder t prvide a step reductin f the equivalent utput inductance. The equivalent utput inductance will change t a much smaller value r, and prvides a much higher slew rate utput inductr current I r. Once the fast utput inductr current reaches the level f the utput lad current, the drp f the utput vltage will stp and start t rise, as utput inductr current is higher than the lad current and flws int C. Auxiliary switch S 1 can be prgrammed t turn ff when the vltage rises back t a certain level. As is much greater than r, the equivalent utput inductr current will be dminated by I after S 1 is turn ff. Althugh magnitude f I is increased during the perid f S 1 is turn n, it is nt high enugh t reach t the level f lad current, hence will drp again after S 1 is turned ff. evertheless, S 1 can be prgrammed t turn n again when the utput vltage drps belw a certain level. These n and ff states will repeat until the magnetizing current I reaches a level equal t the lad current. is expected t keep turning n between that n and ff state f S 1 in rder t ensure I = as sn as pssible and prduce minimum transitin time fr the cnverter t g back t steady peratin as quickly as pssible. The main purpse f the vltage surce V 1 is t ptimized fr minimum transitin time. It keeps the utput inductr s current increasing when S 1 and are turned n. V 1 can be chsen frm t a certain value such that the reflected vltage acrss will nt cause reverse current t flw thrugh when S 1 is n. When the utput current decreases in a fast a large step the peratins are similar the mechanisms s described. At that time S will turn n crrespndingly and prvide a high negative slew rate current t avid vltage build up at C. A transitin perid will be created in which S will turn n and turn ff until the current flwing in inductr reduces t the lad current. III. IMPEMETATIO Practical circuit implement is simple. Vltage surce V 1 r V can be realized by making use f the input vltage, althugh utput vltage is als pssible. Switches S 1, S can be realized by small MOSFET, r may the leakage inductance between winding, aux1, and aux, prper timing f S 1 and S can be achieved by means f hysterisis cntrl accrding t the change f utput vltage. gate M gate M D Z1 S 1 gate S gate C 1 V Dz1 aux1 aux1 S 1 S D 1 D D 1 aux1 aux D (a IC 1 IC (b V S1_n (c V S1_ff (d Fig. Simplified practical implemental, a simplified circuit f stepping inductance cnverter bhysterisis cntrl and PWM circuit c equivalent circuit when bth S 1 and is turned n d equivalent circuit when S 1 is turn ff and is turn n Fig. a shws the practical implement f the stepping inductance cnverter cncept. Tw separated windings r inductrs aux1, aux magnetically cupled t and frm a transfrmer. S 1, S are respnsive t psitive r negative change f lad current. Dides D 1, D prevent reverse current flw. D 1, D, C 1, C, D z1, D z frm a snubber circuit t absrb current reflected frm leakage inductance when S 1 r S is turned ff. It is understd that ther kind f snubber r nn-dissipated snubber may als be used in this applicatin. V th- R V V th C C C C V C D Z O/P1 SR buck PWM cntrller O/P APEC001

3 Fig. b shws the cntrl circuit. The SR buck PWM cntrller can be any typical PWM cntrller fr Sync-Rect buck cnverter. Tw hysteresis cmparatr IC 1, IC, respnsive fr detecting the negative r psitive change f utput vltage. gic circuit is added t ensure n simultaneus cnductin f and M, and n simultaneus turn n f switches S 1 and M r S and. Fig. c shws a simplified equivalent circuit when S 1 and are turned n. S 1 is turned n if the utput vltage drps belw a predetermined level V th1-. will be turned n t as the SR buck PWM cntrller determine a vltage drp at utput vltage. After S 1 is turned n, the magnetizing inductr is shrted ut by an equivalent vltage surce V S1_n which has a value determined by the input vltage and turn rati f and aux1. Hence the vltage acrss the equivalent leakage inductr becmes the difference f input vltage, V S1_n and. It is designed t leave substantially large vltage acrss small leakage inductr t generate current with high slew rate and pumped t the utput t cunter act the utput vltage drp. In practice, the verall equivalent inductance can be as small as the parasitic inductance f the PCB trace. Hence it is pssible t tackle fast transient lad in micrprcessr applicatin. Fig. d shws simplified equivalent circuit when S 1 is turned ff and is still turned n. S 1 is turned ff if the change f utput vltage has risen back t a predetermined level V th-. V th- is the trigger level f a hysteresis cmparatr which mnitrs the utput vltage drp. The current I flwing in leakage inductr will be reflected t aux1 and reset by the vltage surce V Dz1 frmed by snubber as described abve. It is pssible t use a lssless snubber t further reduce the lsses in this reset mechanism. S 1 will keep turning n and ff until the magnetizing current flwing in rises up t the level f the lad current. IV. DESIG PARAMETERS Fig. 3 shws a micrscpic and exaggerated view during lading transient cnditin. V th1- di r 1 -_min V th- V th1 -_max _max _min I _S_n _max Vth Fig. 3 Definitin and exaggerated and micrscpic view between the relatin f utput vltage, inductr current and lading current. di I_S1_n I _min Fig. c, Fig. d and Fig. 3 explain the transient. Here we assume a the change f utput vltage cmparably small with the utput vltage, b the utput current has a very large stepping change which is much larger than the ripple current flwing in. S 1 r S will turn n when the utput vltage drps r rises thrugh the first threshld vltage V th1- r V th1, accrding t cases with a step increase r decrease in lad current. Psitive utput current slew rate n vltage acrss and as, Vi ( V di = Vi aux1 di r 1 f depends, ( 1 Similarly, negative utput current slew rate di = ( V V i aux where = number f turn f, aux1 = number f turn f aux1 di is, ( The behavir f the utput vltage transient can be analyzed accrding t the fllwing mde by assuming a step change f lading current. d r s 1 Fig. 4 equivalent mdel during transient lading cnditin and S 1 r S turn n. In rder t find ut the vltage change acrss C, the turning pint at which maximum deviated utput vltage -_max, _max is prduced has t be fund ut. The peaks can be fund ut by setting it s differentiatin equal t zer. Physically, when current I flwing in catches up with lad current _max, r I = _max, utput vltage will stp drpping and start t rise again. The maximum utput vltage drp -_max can be wrked ut by simple circuit analysis and given by the fllwing equatin ( I _ max I _ S1_ n _ max th1, (3 di C similarly the maximum vltage rise _max during transient is _ max th1 ( I _ min I_ S di C _ n I lading, (4 The inductr current will cntinue t increase r decrease until the changing utput vltage hit a secnd threshld vltage V th- r V th. Beynd this secnd turning pint the utput vltage in change in the ppsite manner. 1 sc s APEC001

4 The negative minimum deviated vltage -_min against can be als fund ut by cnsidering the vltage induced n C caused by the peak excessive inductr current I drpping back t utput current level, that is, _ min th 3 ( I _ max d I _ S1 _ n C ( V V ( Vi VDz1 Vi aux1 C th1 V th similarly psitive minimum deviated vltage _min again is _ min th 3 ( I _ max I _ S _ n C ( Vi V Dz1 C d ( V V aux th1 (5 V (6 th An imprtant criteria need t be drawn t avid self scillatin f the hysteresis cntrl mechanism. One must avid the minimum deviated vltage -_min r _min t crss ver the utput vltage level and tuch the ppsite threshld. The fllwing criteria shuld be met, (a (b V V 0 and V V 0 (7 th1 _ min > th1 _ min > V. EXPERIMETA RESUT A 5nput and utput V 0A cnverter is built. ading current is switched between _max = 0.5A and _min = 0.5A at a frequency f 00Hz. The fllwing figure shws the setup and values. (c 0.1uF 0.1uF 5V V Ω MTP3055 x V 15T 15T 3T 1.5uH 100uF x 3 ceramic Cap. Fig. 5 simplified experimental circuit Output inductr = 1.5uH, = 3T, with very small utput ceramic capacitr f C = 300uF, and switching frequency f s = 300kHz. Auxiliary winding aux1 = 15T, aux = 15T are chsen 5 times f t reduce the lsses f auxiliary MOSFETs S 1 and S,. S 1, S are MTP Ω small MOSFET. D 1 = D = D 1 = D = BYV7C. eakage inductance is measured as = 100nH. Which includes trace inductance D z1 1/W zener, D z = V 1/W zener. C 1 = C = 0.1uF. V th th- = 40mV V 470uF E-Cap 50mΩ 3.9Ω 0.1Ω (d Fig. 6 Experimental result f utput vltage variatin, CH1 utput CH lad current signal, a stepping inductance evaluatin prttype b withut stepping inductance c with stepping inductance d with stepping inductance and extended time base. The vltage deviatins are calculated accrding t the equatins s derived. Assuming the ripple current f the utput inductr is relatively small with cmpare t the lading current step change. Hence an apprximatin can be made, APEC001

5 I _S1_n = _min and I _S_n = _max The maximum vltage change -_max and _max with 0A lading change is calculated as -_max = 7mV and _max = 103mV. The experiment result shw the real situatin is better than the calculated result. The reasn is investigated as the auxiliary switch S 1 and S actually turn n befre the deviated utput vltage hit the first threshld vltage V th1- r V th1. It is caused by nise spikes induced frm the very high slew rate f lad current. Results in Fig. 6b and Fig. 6c shw almst 5 times reductin cmpared t unmdified buck cnverter. Fig. 6d shws a magnified view and it displays the small ripple vltage caused by the turn n and ff f S 1 and S. Cnductin lsses in auxiliary switch S 1 and S are greatly reduced by the turn rati f, aux1 and aux. The temperature rise f the MOSFETS S 1, S with 0.18Ω R ds_n and snubber zeners dides D z1, D z are belw 5 C. A transient fast change in input current will be intrduced by the fast utput current due t a fast lad transient. This is true fr all fast transient cnverters. An input filter is needed t slw dwn the input current during lad transient cnditin. Such input filter can als prvide filtering effect fr steady state peratin. VI. COCUSIOS A stepping inductr methd fr cnverters with an utput inductr is presented. The stepping inductance cnverter is very suitable fr lw cst fast transient vltage regulatr applicatin. It can be applied t cnventinal buck cnverter t much imprve transient respnse with nly tw additinal small MOSFETs and dides. It is als theretically lssless. Cntrl circuit is als easy t implemented and can be integrated with an existing buck PWM cntrller IC. Extra cst and design effrt fr such imprvement is minimum, as nly lw cst small size cmpnent r lgic circuit are needed. Steady state perfrmance is equivalent t tday s sphisticated SR buck cnverter, and practically very little pwer lss due t transient peratin. It is believed that such apprach is very suitable fr lw cst fast transient respnse vltage regulatr used n micrprcessr and ther fast lading change applicatin. VI. REFERECE 1 F.C. ee, Vltage Regulatr Mdule fr Future Generatin f Prcessrs, Tutrial tes, Sixteenth VPEC Pwer electrnics Seminar, Virginia Tech., 1-115, September 1998 M.T, Zhang, M.M. Jvanvic and F.C.Y. ee, Analysis and Evaluatin f Interleaving Techniques in Frward Cnverters, IEEE Trans. Pwer Electrn., Vl. 13,. 4, pp , C.K. Tse and.k. Pn, ullr-based Design f Cmpensatrs fr Fast Transient Recvery f Switching Regulatrs, IEEE Trans. Circ. & Syst. Part I, Vl. 4,. 9, pp , September F..K. Pn, C.K. Tse, C.P. iu, Very Fast Transient Vltage Regulatr Based n ad Crrectin, IEEE Pwer Electrn Specialists Cnference (PESC., Vl 1, pp , June 1999 APEC001