300V /IJS power AUDIO DESIGN

Transcription

1 UDO DESGN Building n his earlier fast driver amplifier wrk, Givanni Stchin has nw develped what is pssibly the fastest highpwer audi amplifier f its type. Mre impressively, he has dne s withut sacrificing audi purity. 300V /JS pwer n my previus article described hw the basic architecture f highspeed vltage feedback amplifiers can be applied t the design f highperfrmance audipwer equipment. Detailed design infrmatin fr a nnslewing 100 watt int SQ msfet pwer amplifier was given. t featured a linear utput speed f ±170Y /f!s and its rated utput pwer ttal harmnic distrtin figures were 0.004% and 0.045% at 1kHz and khz, respectively. Subsequent investigatins have shwn that further evlutin f the basic architecture can prvide higher speed and better thd figures cmparable with tpclass hifi amplifiers relative t the basic cnfiguratins. This article reprts the results f my recent investigatins and experiments and prvides design details fr a new lwdistrtin, very high speed loow int SQ audi pwer amplifier, which features a slew rate higher than ±300Y /f! s and rated pwer thd figures f less than % and 0.0% at 1kHz and khz, respectively. mprved highspeed architectures n my last article, demnstrated that the thd and speed perfrmances f the basic high speed vltagefeedback architectures appear t be influenced by the lw, i.e. unity t tw, current gain f the intermediate stage. This implies that a substantial imprvement f bth thd and speed figures can be btained when a higher current gain class B intermediate stage is incrprated in the riginal schemes. The prblem here is that this change has t be dne withut degrading the ther perfrmances and, mre imprtantly, the rbustness f the basic design. With this requirement in mind, my investigatins have fcused n the tplgies shwn in Figs 1 and 2. The input stages are designed t prvide class B peratin and the simultaneus availability f large pushpull currents, R and L, with the apprpriate phase, at ndes and B, Fig. 2. have already shwn 2 that this feature is very imprtant t avid the dangerus simultaneus cnductin f the upper and lwer half f the intermediate stage. During simultaneus cnductin there is a risk f driving intermediate stage transistrs ut f the dynamic safe perating area. viding simultaneus cnductin cntributes t the rbustness f the amplifier. t is particularly imprtant in very fast highpwer amplifiers, where the feedback lp frces the intermediate stage t prvide high peak currents during large/fast input transients. nther key feature f these schemes is the use f cmmnbase transistrs Trl. ll. These play a twfld rle: t allw the use f lw vltage high current gain transistrs Tr9 and Tr1 2, which increases the available gain and peak current f the intermediate stage; t imprve amplifier linearity. Relative t Fig. 2, the cnfiguratin f Fig. 1 ptentially prvides higher input stage large signal transcnductance and less pwer cnsumptin. s is well knwn, large signal transcnductance in bth schemes is determined mainly by crss cupling resistr R. Hwever, while in Fig. 2 the value f R is mainly gverned by the need t prvide the level shifting vltage with reasnable pwer cnsumptin, in Fig. 1 this limitatin des nt apply. s a result, R can be set as lw as cnvenient. Because f the abve, Fig. prmises better speed and lwer pwer cnsumptin than Fig. 2, althugh at the expense f ffset and nise precson and distrtin perfrmance. Differences in the tw schemes are nly in the input stage. ntermediate and utput stages are exactly the same fr bth designs. Cmpared with the simplified circuit diagram presented in my March ' 96 article, the clamping netwrk at the utput f the input stage in these designs shws ne additinal dide, which has been intrduced t increase the intermediate stage peak utput current t abut SOm. ccrdingly, higher maximum utput rates f change are t be expected. n rder t prduce cmparable results, the tw amplifiers are designed with as clse as pssible phase margins and unity gain frequencies under clsedlp cnditins. 278 ELECTRONCS WORLD pril 1997

2 UDO 55V>, 40R 3k3 R OR33 10R, 100n RF9630 Fig. 1. Simplified schematic f a pssible 1k5 Q implementatin f high speed, 1V lw distrtin pwer amplifier emplying a high 55V>++ slew rate input stage. 55V>r. 1N4448 Q Q L R R R S V 1 V 2 3k3 R 0R 50n + 9V 1k 1k OR33 10R, 100n RF9630 R L 55V 1N4448 L_ B _ R Fig. 2. n this preferred implementatin f a high Q Q speed, lw distrtin pwer amplifier, a nnslewing input stage is 33R the main difference relative t Fig. 1. pril 1997 ELECTRONCS WORLD 279

3 UDO DESGN 55V +48V 33R c5 1k5 Tr23 2N R Tr5 2N2907 Tr'6 1k5 Tr Tr24 1N4448HV (x2) Tr'5 c, Tr '9 C s RF640 RF640 DZ, 33V 1W V in 2n 3W 3W 0R C 1n OR47 OR47 22R V F 3k3 V ' 0 OR47 OR47 1k3 3W 3W DZ2 33V c 2 1W Tr2' RF s B Tr 26 Tr17 Tr22 RF9640 Tr2 5 Tr, s 60R Trs c 6 55V + L+(48V Fig. 3a), Detailed circuit diagram f the final Sme Spice simulatin results are reprted loow/hq audipwer amplifier, featuring a in Tables 1 and 2. Here, the main characteristics f the tw new amplifier cnfiguratins speed higher than ±300V/ps, and a rated pwer thd f 0,002% at 1kHz and 0,0 18% at are cmpared with the basic nnslewing khz. Nte that all dides are 1 N4448 architecture, with similar characteristics. Dides 1 N4448HV are 1 N4448 selected fr a t is clear that the new implementatins prvide better speed and thd perfprmances than reverse vltage higher than 1V, dd 100pF//l00nF decupling t each 55V rail the basic nnslewing architecture design, cnfirming the theretical predictins. and 1000pF//2xl00nF t each 48V rail. Figure and 2 have very similar clsedlp perfrmances. Hwever, due t the reduced 1n 50n cax cable V SR T the pwer amplifier >t...t++t, utput V' C(SR) Rin (Osci lscpe) Terminatin R(SR)Rin(Osc) = 10n Fig. 3b). Slew rate test circuit frm D. SeP. Cmpnent values and circuit have been adapted t highspeed measurement, Slew rate, SR, can be determined by the fllwing; SRVSR(m.x/(CSRRp)=lOOXVSR(m.xfr in V/ps, where Rp=R(sR//R'N(OSC)=OQ, Oscillscpe bandwidth is higher than 0MHz. number f transistrs in the input stage, Fig. 2 ffers better penlp perfrmance, in terms f frequency respnse and phase margin, as wels less nise. n the light f the abve, Fig. 2 seems t represent the best candidate fr the design f a highperfrmance audi pwer amplifier, althugh pwer cnsumptin is higher due t the level shifting current needed t bias the input stage. Mrever, this tplgy can be expected t prvide reduced sensitivity t layut and parasitics, as wels lad impedance variatins. Cnsequently it will simplify design and implementatin. mplementing the pwer amplifier Design has been ptimised thrugh intensive simulatin wrk and verificatin tests n the experimental prttype. Measurements have substantially cnfirmed simulatin results. Discrepancies nly ccur when simulatin data are clse t r belw the limits f available test equipment, the readings frm which.include nise, as wels thd. This is the case 280 ELECTRONCS WORLD pril 1997

4 UDO DESGN Table 1. Characteristics f Fig. and Fig. 2 fast audipwer amplifiers. Test cnditins are Q =1m, Rs=SO, Lad=8Q.//O.SlF. Fig. 4. nput stimulus type used fr verifying the amplifier's speed, during simulatin and experiments. Vertical scale is 3V/div. Maximum speed measurements were made using bth standard and Self methds. fr thd at khz. The differences at khz can be explained by layut prblems in the experimental prttype and/r by the influence f cmpnent mismatches. Final design Figure 3a shws the cmplete circuit diagram f the final lw thd, high speed loow, 8[2 audi pwer amplifier. Cmpared with Fig. 2, extra capacitrs C3 t Cs are intrduced in the assembled prttype. These cmpnents cmpensate fr layut parasitics and achieve a clean step respnse in all perating cnditins, Figs 4, 5 and 6. The dide clamping netwrk n the cllectrs f the input stage transistr has been simplified. Tw dides cnnected t zener dides DZ3 and DZ4 perfrm the same task f the riginal circuit. Here, psitive and negative peak currents f the intermediate stage are slightly higher and symmetrical than in Fig. 2. The biasing netwrk f the intermediate stage is made frm Tr13, Tr14, DZ3 and DZ4, in additin t current setting resistr RE' Nminal bias current, given by. and is abut 6m. Bias setting and stabilisatin f utput pwer msfets is achieved by means f the TL431 shunt regulatr and temperature sensing netwrk TS in Fig. 3a. This netwrk cn Characteristic Basic nsa 1 Fig. 1 Fig. 2 Best input ffset vltage2 350N 180iJV 170iJV DC gain, pen lp 80dB 110dB 111 db Unitygain frequency 22.5MHz 19MHz 22MHz Openlp gain at khz 64.5dB 67dB 68dB Openlp amplifier phase margin ]0 930 Clsedlp amplifier phase margin Slew rate, 10V pp square wave input ±160V/iJs ±210V/iJs ±185V/iJs Output nise, bandwidth 80kHz 34iJV rms 50"N rms 311.JV rms Table 2. THD f amplifiers in Fig 1 and Fig 2 with same test cnditins as Table 1. VudVpp) Basic nsa1 design Fig. 1 Fig Ntes 1 khz khz 1 khz khz 1 khz khz % % 1. Nnslewing amplifier % % % % % % % % % % 2. n the simulatin phase, devices and cmpnents have been cnsidered perfectly matched. 3. mplifier nly, i.e. withut the feedback netwrk. 4. mplifier plus feedback netwrk. Clsed lp gain is 30.6dB. db ' L :v(a) \ r..! r \v ib) \V'(a,b) 11 1\ 1\ 1\ lk 10k look lm 10M Fig. S. Simulated frequency respnse i.e. magnitude f the pwer amplifier in Fig. 3. Test cnditins are V(a) 10ad=8Q.//O.SpF, V(b) 10ad=8Q.//O.OSpF, vertical scale is lodb/div and frequency range is 1 Hz t 100MHz. sists f three didecnnected s and is munted very clse t the utput msfets n the same heats ink t prvide thermal cupling. This scheme prvides a stable wrking pint fr the temperature sensr TS, which is insensitive t / Ba variatins. This is because current hs is kept cnstant by the TL43/'s 2.SV internal reference, thrugh the relatinship, Hz /TS=Vref/R( T1) Since, as is well knwn, each transistr prvides a '::.Vt>e/'::.T f abut 2 mvrc, TS yields a ttal '::.VTS/'::.T f 6 mvrc. This has been fund adequate t cmpensate fr the intrinsic Q changes with temperature f pwer devices. Bias current Q f each msfet is set at 1m via trimmer VR 10 after a reasnable V 40 n R V' J ( V J l 0 15 V' V n r, 1\ \j'v V' lv V V 15 V' ' ' ' 1601' 1801' 01' 21' 2401' Fig. 6a). Simulated vltage step respnse f the pwer amplifier in Fig. 3. Test cnditins are V'=V peakpeak, lad=8q.//o.oospf, vertical scale is 1SV/div and frequency is 10kHz. Fig. 6b). Simulated vltage step respnse f the pwer amplifier in Fig. 3. Test cnditins in this case are the same as fr 6a), except fr the lad, which is 8Q.//O.SpF. pril 1997 ELECTRONCS WORLD 281

5 UDO DESGN amplifier warmup time. Make sure t set this trimmer t its highest value befre applying pwer t the amplifier. Measured Q variatins during peratin are less than %. Supplying pwer T increase the amplifier ' s efficiency, separate unregulated ±48V supply rails are used fr the utput pwer devices, which are RF640 and RF9640 types frm nternatinal Rectifier. The rest f the amplifier is pwered by tw regulated +55 and 55 V supply rails. Tables 3 and 4 demnstrate the ntable imprvement f harmnic distrtin figures. t 1kHz, measured thd is mainly limited by the available instrumentatin, as illustrated by the fact that it remains virtually unchanged when lad impedance reduces t 4ft The maximum rate f change f the utput vltage results in excess f 300V /f! s, cnfirming that the new architecture is viable fr reliable highspeed pwer amplificatin. Measurements f slewrate were made bth in the traditinal way, and in accrdance with the practical methd suggested by Duglas Self, 3 with apprpriate adaptatins. The test circuit is shwn in Fig. 3b. ssuming VO'»VSR' the maximum rate f change SR is determined by, where Rp=RsR//RN(se)=lOn. T the best f my knwledge, this speed is the highest ever reprted fr a high pwer audi amplifier, which makes use f vltagefeedback. The thery behind the speed perfrmance f this architecture can be basically explained as fllws. The maximum current available at ndes and B depends n the maximum input vltage, V max ' which can be safely applied t the input f the amplifier. This is given by equatin 4 f my March ' 96 article, = V;ma» 2 V he(n) = V EBO V he(n) (ma» 2R e + R 2R e + R This current amunts t abut 18m fr the cmpnent value and active device types used in Fig. 3a. Since capacitance at ndes and B in Fig. 3a is abut 50pF, the maximum slew rate acrss Cnd C2 is SR,B=360V/f!s. Capacitrs C 3 and C4 d nt play a majr rle in this cntext because the vltage variatin acrss them is limited t a few vlts. On the ther hand, the current available at the utput f the intermediate stage, ndes C and D, is abut 80m. Ttal nde capacitance, including the reflected capacitance f the utput pwer devices, is less than 230pF. Slew rate at the input f the utput stage will therefre exceed SRC,D(min)=350V /f! s. Bias current cnsideratins t is wrth pinting ut that this high value f slew rate can be sustained by the amplifier nly if biasing current Ba is large enugh t charge/discharge at the same rate the basecllectr capacitances Cbe f TrO and Trll, which equal 58 pf. This means that BOSRCD(min)Cbe has t be set at 2.8m. safety margin is recmmended fr taking int accunt parasitics and base drive requirements, which equals, B(pead(min)=80m/30=2.7 m. The minimum utput slew rate SR(min) will be slightly less than SRCD(min) ' due t the gate driving requirements f the utput pwer Table 3. Ttal harmnic distrtin f finamplifier in Fig. 3a, with R.=SOO, Q= 1m and 80kHz bandwidth. VO U! (V pp) Spice simulatin Measured Measured an lad an lad* 4n lad* 1kHz khz 1kHz khz 1kHz % % % 0.005% % % % % 0.008% % % % 0.00% % % % % % 0.015% % % % % 0.018% % *nstrumentatin limit, thd+nise):0.002% at 1 khz; 0.003% at khz. Table 4. Further characteristics f Fig. 3a amplifier, R.=SOO, lad=8fj., Q=1m khz 0.007% 0.010% 0.013% 0.018% 0.026% devices. The abve theretical values are in line with simulatin, and with measured results, Table 4. n this design, a nf capacitr has been added acrss R t increase the dynamic transcnductance and the available peak current f the input stage crrespnding t the maximum expected input signal transients, say 3V peak. n such a case, V 2V (pe a k) = i" (pe a k ) 2R, he( n) ::; 18m This results in a slight increase f speed fr input signals within the linear dynamic range f the amplifier and in a further reductin f the already lw residue f dynamic intermdulatin distrtin. Crsscupling capacitr C needs t be treated very carefully. n fact input transistrs Trl t Tr4, under large signal cnditins, behave like a full wave rectifier f the vltage difference VNVF. Current flwing in C is thus unidirectinal. This results in a dynamic charge buildup acrss C, which is particularly imprtant at high frequencies and during transients, when VlNVF is usually larger. The charge buildup culd end by prducing undesirable bias and gain mdulatin f the input stage, and, cnsequently, increased high frequency thd and intermdulatin distrtin. This effect is als evident frm the fact that while C can truly help t bst the linear speed f the amplifier during ccasinal transients, it des nt prduce the crrespnding imprvement f the linear pwer bandwidth and f the dynamic intermdulatin distrtin. Minimising charge buildup n rder t minimise the abve side effects, a lw value f capacitance shuld be chsen. Definitin f the right value f C is nt an easy task, since its influence n the circuit perfrmance is bth amplitude and frequency dependent. The fllwing rule f thumb has prved effective in many applicatins, 1 C::; 1O(21tRF M ) where FM is the maximum input frequency, which is khz fr audi applicatins. This implies that the zer intrduced by R//C in the large signal frequency respnse f the amplifier has t be lcated far abve the audi frequency range. ccrding t the abve empirical inequality, C shuld be lwer than 3.9nF. s a matter f fact, the value emplyed in this design, nf, has nt prduced measurable effects n thd perfrmance. Characteristic Spice simulatin nput ffset vltage Slew rat et, C=OpF +336/297V /s' Slew ratet, C=1 nf +360/304V/s Output nise, bw=80khz 31 V (rms) t ±6V peak pulse input, as in Fig. 4. Measurement results 1.6 mv +31 0/360V/s +360/370V/s 39V (rms) References. Stchin, G, "Nnslewing udi Pwer mplifier", Electrnics Wrld, March 1996, pp keith@keithsnk.inf 2. Stchin, G, "Ultrafast mplifier", EW, Octber 1995, pp Self, D, "High Speed udi Pwer", EW +WW, September 1994, pp kenh@snkeu 282 ELECTRONCS WORLD pril 1997