Compound Semiconductors; GaN and SiC, Separating Fact from Fiction in both Research and Business

Transcription

1 6/25/2013 Cmpund Semicnductrs; and, Separating Fact frm Fictin in bth Research and Business Prfessr Umesh Mishra, Ph.D. Redefining Energy Efficiency Cmpund semicnductrs separating Fact frm Fictin Why d we need a new technlgy? What technlgies are pssible? What are the relative merits f and? Perfrmance f vs. 2 1

2 New Slutins Needed t Meet Grwing Energy Demands Wind/Slar 2.1% Hydr 6.4% Nuclear 19.3% Other Renewables 2.6% Cal 45.6% Cnversin lsses 10% Lighting 19.0% Heating and Cling 16.0% Mtr Drives 51.0% Nat.Gas 24.0% IT 14.0% US Net Electricity Generatin By Surce Surce: EIA (Energy Infrmatin Administratin) US Net Electricity Cnsumptin Surce: EPRI, E Surce and Exxn Mbile S what is the issue with Silicn? Industry Pwer Density Radmap Silicn has prvided us the pathway fr pwer cnversin slutins fr several decades but has nw reached its physical limits and pen new pssibilities 4 2

3 New material ptins t keep us n the pwer density radmap established in the market as a high perfrmance dide; released as JFETs and s (target applicatin space 1200V) n Si high perfrmance slutin with a radmap t lw cst fr dides and transistrs n higher cst slutin fr applicatins demanding higher SFO: perfrmance with reduced sensitivity t cst NYC: 6 TWh n early stage f develpment 50 TWh Gallium Oxide very early stage Diamnd ut there 5 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but prviding a sustained radmap t develp a new standard in pwer cnversin Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) SFO: Transistr ( and ) 6 TWh Nvel transistr packaging (Quiet Tab ) Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 6 NYC: 50 TWh 3

4 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but sustained radmap Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) Transistr ( and ) SFO: Nvel transistr packaging (Quiet Tab ) 6 TWh Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 7 NYC: 50 TWh Cmparing Si, & Semicnductrs and ffer: High breakdwn field ffers: High mbility ffers: High thermal perfrmance Si 4H E g (ev) E bk (10 5 V/cm) v s (10 6 cm/s) μ (cm 2 /Vs) * 2000 k (W/mºC) (E bk v s /π) μe 2 bk * Inversin layer: <100; drift

5 Why is s remarkable? is a direct bandgap material; It emits light frm a dislcated material! Basis f a $10B LED industry tday (wh wuld have thught?!!) is the wide band gap slutin fr next generatin RF wireless base statins and military RADAR ; chsen ver dislcatin free MESFETS (wh wuld have thught?!!) The tight lattice and n shear stress t mve the dislcatins makes almst insensitive t dislcatins cmpared t and ther cmpund semicnductrs Energy Gap (ev) A1N direct bandgap indirect bandgap RF, Pwer, High Vltage LED, Laser R = 0 =90 c plane 1.0 Sapphire InN Lattice Cnstant (Å) NO shear stress exists fr c! 9 The heart f all pwer cnversin unit is a SWITCH N Current cllapse I DS High Maximum Current I MAX Lw R ON = V ON /I ON I ON I ON (dynamic) V ON Fast Switching Times fr Lw Switching Lss Very High Breakdwn Vltage V OFF V BD V DS Lw Leakage Ttal Lss f a switch= cnductin lss + switching lss 10 5

6 Switch gives the lwest cnductin lss Specific On-Resistance ( cm 2 ) 1.E+02 1.E+01 1.E+00 1.E-01 1.E-02 1.E-03 1.E-04 NCSU 97 ACCUFET Si Limit Limit DC Figure f Merit nly 1.E Breakdwn Vltage Ykgawa 06 DMOS Kansai 00 SIAFET On 04 SJLDMOS Purdue 98 LDMOS Tshiba 05 Semi SJMOS Fuji 02 SJMOS CREE 03 BJT Matsushita 06 GIT CREE 08 BJT NIAIST 06 IEMOS Transphrm 2010 Transphrm Target Slutins Al 0.22 Ga 0.78 N/ Limit Si Energy (ev) Distance (nm) Channel with High n s. m Lw R n Lw cnductin lss Wide band gap High Critical Field, High Breakdwn Vltage, High Temperature Stability 11 enables high frequency peratin with lw switching lss 2x advantage ver 14x advantage ver Si 5x advantage ver Si junctin Cnductin + Switching Lss Ttal Lss (A.U.) Ttal Switching Lss Lss (A.U.) (a.u.) E+03 Si Frequency (Hz) IGBT Est. 12 KHz: >50 Watts 1.0E KHz: > 150 Watts Ttal Lss minimized fr each switching frequency 100 KHz 1.0E E E E E E+08 Frequency (Hz) 12 6

7 Transphrm Imprvements in Dynamic Perfrmance f Direct relatin t perfrmance in real wrld applicatins Majr benchmark fr success in pwer devices Extracted frm cnverter circuit R ON ( ), I D (A) Previus status: Mid 2008 Previus status: End Id 2 Rn V D (V) R ON ( ), I D (A) Id Rn V D (V) R ON ( ) Id Rn V d (V) 13 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but sustained radmap Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) Transistr ( and ) SFO: Nvel transistr packaging (Quiet Tab ) 6 TWh Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 14 NYC: 50 TWh 7

8 n Si and 600V Dides Outperfrm Silicn 4A Dide Example Bth and dide have lwer VF than silicn. Less cnductin lss Bth and dide has zer minrity charge: 0 vs. 62nC (Si) Less spike & stable high temp peratin dide can be built n Si substrate Si Tj=125C 1.47V 1.4V 2.3V 15 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but sustained radmap Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) Transistr ( and ) SFO: Nvel transistr packaging (Quiet Tab ) 6 TWh Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 16 NYC: 50 TWh 8

9 Nrmally ff HEMTs designs Junctin gated HEMTs Channel etch thrugh G Dielectric S P Dielectric Al D S G Dielectric Al D Buffer Buffer P gate depletes the channel Remving the P layer frms the channel Advantage: Single chip nrmally ff transistr Disadvantage: Lw threshld vltage Advantage: Single chip nrmally ff transistr Disadvantage: Device/ Dielectric nt qualified 17 Cascde HEMT implementatin Advantage: Rbust High perfrmance Cmpatible with Si drivers Disadvantage Tw chip slutin Surce Gate Insulatr Drain Al Barrier 2DEG Device Cell Crss sectin Buffer Substrate ( r Si) Cascde Apprach t achieve nrmally ff Nrmally ff G LV Si FET HV HEMT 18 D Nrmally n Effective CKT D G S Nrmally ff 9

10 Gen 1 HEMT vs. Si Junctin HEMT Si ClMOS ( junctin ) 19 HEMT n Si vs. HEMT n VBD > 1100 V n Si and substrates Similar leakage with bth n and n Silicn 1 na/mm at >1kV! < 10% change in Rn under switching 0.1 ma n n Si 20 10

11 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but sustained radmap Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) Transistr ( and ) SFO: Nvel transistr packaging (Quiet Tab ) 6 TWh Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 21 NYC: 50 TWh Quiet Tab package made pssible by lateral devices Surce cnnected t case fr lw side switch (A) Drain cnnected t case fr high side switch (B) Package bdy (large capacitr) is always at a DC ptential; n switching Reduced charging capacitance: lwering charging lss and CM EMI GSD has better I O islatin than GDS pin ut AC grund Drain (B) cnnected t case High side switch Lw side switch Q 1 V CC G G V V D S D S L R L Grund 22 G S D (A) G S D Surce cnnected t case 11

12 Hw can a new technlgy penetrate a market dminated by Silicn? Have material prperties far superir t that f Silicn Nt just ne prduct but sustained radmap Prvide a slutin in an existing market that Si cannt prvide Cmpund semicnductr devices Dides ( and ) Transistr ( and ) SFO: Nvel transistr packaging (Quiet Tab ) 6 TWh Prvide a cst advantage in an existing market System slutins at cst parity r cheaper than Si based slutin Reduced cmpnents (dide free bridge peratin) Efficient high frequency peratin small mechanical and electrical size Create a new market 23 NYC: 50 TWh LLC DC cnverter s imprved perfrmance with at 500 khz Curtesy: Wrk dne by CPES at Virginia Tech. 500kHz fr cmpact pwer supply design. Peak efficiency gain by is ~ 1%. Lw lad efficiency gain (2 3%) 24 12

13 Perfrmance / Price Cmparisn System Perfrmance Si Device Cst Transphrm uniquely enables superir perfrmance at lwer cst System Perfrmance System Advantage Other Si System 26 Cst 13

14 3 Phase mdule & high frequency inverter (mtr drive r PV) High frequency design (100kHz 300kHz) enables cmpact filter (Lwer cst) Dide free Bridge (Lwer cst and lss) Mdule Inverter 27 Yaskawa PV cnverter prttype Output pwer 4.5kw (Single Phase 200V) Input vltage V Maximum Pwer Efficiency > 98% (vs. >96.5% with Silicn) Vlume abut 10L <18L (existing Silicn based) 40% vlume reductin 99 Significant lss reductin Silicn Prttype 28 Efficiency [%] Imprved Efficiency In Majr regin Output Pwer[W] 開発品 -PV 現製品 Si-PV 14

15 S where des this psitin and? The view f the future depends upn yur pint f view 29 Market perspective High end slutins Middle end slutins Junctin Junctin Silicn Junctin Lw end slutins Silicn Junctin Silicn 200 V 600 V 1200 V What Yle Develpement shwed in 2011 as future view 30 15

16 Market perspective High end slutins Middle end slutins Junctin Junctin Silicn Junctin Lw end slutins Silicn Junctin Silicn 200 V 600 V 1200 V A Junctin supplier s view f future 31 Market perspective High end slutins Middle end slutins Silicn Junctin Lw end slutins Silicn Junctin Silicn 200 V 600 V 1200 V A supplier s view f future 32 16

17 Market perspective High end slutins Middle end slutins Junctin Lw end slutins Silicn Junctin 200 V 600 V 1200 V Nw that 600 V n Silicn is Qualified, a slutin supplier s view fr future 33 17