An m-level Active-Clamped Converter Topology Operating Principle

Transcription

1 An m-level Active-lamped nverter Tplgy Operating Principle S. Busquets-Mnge and J. Niclás-Apruzzese Department f Electrnic Engineering, Technical University f atalnia, Barcelna, Spain sergi.busquets@upc.edu, jniclas@eel.upc.edu Abstract- This paper presents a nvel multilevel active-clamped cnverter tplgy, which is an extensin t m levels f the three-level active neutral-pint-clamped tplgy. The perating principle is established thrugh the definitin f a prper set f switching states and a transitin strategy between adjacent switching states. The benefits f the prpsed cnverter tplgy and cntrl in cmparisn t alternative multilevel cnverter tplgies are discussed. Simulatin results f a simple dc-dc cnverter cnfiguratin are presented t illustrate the cnverter perfrmance features. I. INTRODUTION Multilevel cnverters [] [4] have pened a dr fr advances in the electrical energy cnversin technlgy. These cnverters present the advantages f a lwer device vltage rating, a lwer harmnic distrtin, and higher efficiency cmpared t cnventinal tw-level cnverters. These cnverters are typically cnsidered fr high pwer applicatins, because they allw perating at higher dc-link vltage levels with the current available semicnductr technlgy. But they can als be attractive fr medium r even lw pwer/vltage applicatins, since they allw perating with lwer vltage-rated devices, with ptentially better perfrmance/ecnmical features [5], [6]. There are three basic multilevel cnverter tplgies: dide clamped, flying capacitr, and cascaded H-bridge with separate dc surces. A number f hybrid tplgies cmbining them have als been prpsed in the literature. This paper presents a nvel multilevel tplgy built upn a single semicnductr device. This tplgy is an extensin t an arbitrary number f levels f the ppular three-level active neutral-pint-clamped tplgy. A prper set f switching states and a switching state transitin strategy are defined t btain the maximum benefits frm the prpsed tplgy. The paper is rganized as fllws. Sectin II presents the cnverter leg tplgy. Sectin III defines the perating principle. Sectin IV discusses the features f the prpsed tplgy cmpared t alternative tplgies and the pssible cnverter cnfiguratins built upn the cnverter leg presented in Sectin II. Sectin V presents simulatin results in a fur-level dc-dc cnverter cnfiguratin t illustrate the peratin features, and Sectin VI utlines the cnclusins. II. TOPOLOGY Fig. presents ne leg f the generalized multilevel cnverter prpsed in [7]. The tplgy is frmed by a This wrk was supprted by the Ministeri de iencia e Innvación, Spain, under Grant SD pyramidal cnnectin f m (m)/ instances f the basic cell defined in the inset f Fig.. The leg presents ne utput terminal () and m input terminals (i k, k {,,, m}), where m is the number f cnverter levels. A capacitr r a vltage surce is cnnected acrss every tw adjacent input terminals, being the dc vltage f each f these cmpnents typically the same (V dclink /(m)). In this case, and if the cnverter is prperly perated [7], each device f the basic cell (capacitr, switch, and dide) has t withstand a vltage equal t V dclink /(m). The tplgy is general, in the sense that several tplgies can be derived frm this ne. Fr instance, as discussed in [7], remving the flying capacitrs and the inner switches leads t the dide-clamped tplgy. Remving the inner switches and dides leads t the flying capacitr tplgy. Anther ptin t simplify the tplgy, nt cnsidered in [7], is t remve nly the flying capacitrs. This leads t the active clamped tplgy prpsed here and presented in Fig.. Remving the flying capacitrs allws generating the tplgy frm a single device (e.g., metal-xide semicnductr field-effect transistr (MOSFET), where the dides in the tplgy f Fig. can be implemented thrugh the MOSFET bdy dide) and pens new peratinal pssibilities that are explred in the next sectin. The active neutral-pint-clamped tplgy presented in [8] and [9] represents the particular three-level case f the m-level tplgy presented here. III. OPERATING PRINIPLE A. Switching States The functinal mdel f the cnverter leg in Fig. is equivalent t the functinal mdel f a dide-clamped cnverter, where a single-ple m-thrw switch allws the cnnectin f the utput terminal () t each f the m pssible input terminals (i k ). A set f m switching states are defined t implement these m pssible cnnectins. The switching states are defined with the aid f m independent cntrl variables (c k, k {,,, m}) and their cmplementary values ( c k ), representing the state (n:, ff: 0) f the switches in Fig.. Each switch has an assciated cntrl variable, indicated within brackets in Fig.. T cnnect the utput terminal () t the input terminal (i k ), the cntrl variable values are c j 0 j k () c j k. j /0/$ IEEE 3

2 i m i m i m V dclink Basic ell i Fig.. Generalized multilevel cnverter leg tplgy (m levels) [7]. S p(m ) [c (m)] i m S n(m )(m ) [c (m )] S p(m ) [c (m)] i m S p3 [c 3] S p4 [c 4] S n(m )4 [c (m )] S n(m )(m ) [c (m )] i m S p [c ] S n(m )3 [c (m )] S p3 [c 3] i S p [c ] S n(m ) [c (m )] S n(m ) [c (m )] S p [c ] S p [c ] S n(m ) [c (m )] S n(m )3 [c (m )] S p3 [c ] V dclink S n(m ) [c (m )] S p3 [c ] S n(m 3) [c (m 3)] Basic ell S n(m 3) [c (m 3)] S p4 [c ] S n(m 4) [c (m 4)] S p(m ) [c ] S n [c ] S p(m ) [c ] S n [c ] i Fig.. Prpsed multilevel active-clamped cnverter leg tplgy (m levels). 3

3 Table I presents a summary f the m pssible switching states, defined accrding t (). Fig. 3 presents these switching states in the particular case f a five-level cnverter leg. The uncircled switches are ffstate devices. The circled switches are n-state devices. The slid-line circled switches cnnect the utput terminal t the desired input terminal and cnduct the utput terminal current (i ). The arrws in Fig. 3 indicate the directin f the current flw thrugh these switches. The dtted-line circled switches d nt cnduct any significant current and simply clamp the blcking vltage f the ff-state devices t the vltage acrss adjacent input terminals (i k and i k ). It can be bserved that the cnnectin f the utput terminal t the inner input terminals (i k, k {,, m}) presents mre than ne path f m series-cnnected n-state switches t cnduct the utput current. The distributin f the utput current i thrugh the different current paths will depend upn the switch characteristics. If MOSFETs are used, in which the n resistance presents a psitive temperature cefficient, current will be prperly distributed thrugh the slid-line circled devices. Assuming a value f the n resistance f an elementary switch equal t r, Table II presents the values f the equivalent n resistance f the cnnectin f the utput terminal t each input terminal in three-, fur-, and five-level cnverter legs. B. Transitins between Switching States. The transitin between tw adjacent switching states (k and k) requires changing the state f m switches. The transitin frm switching state k t switching state k requires turning Switching State nnectin f t TABLE I SWITHING STATES c c c 3 c k c m i k i k m i m Switching State TABLE II EQUIVALENT ON RESISTANE m = 3 m = 4 m = 5 r 3r 4r r.4r.875r 3 r.4r.5r 4 3r.875r 5 4r ff k diagnal switches (S nkj, j =,,, k) and turning n mk diagnal switches (S pkj, j =,,, mk). Obviusly, the transitin frm switching state k t switching state k requires turning ff mk switches (S pkj, j =,,, mk) and turning n k diagnal switches (S nkj, j =,,, k). In the transitin between adjacent switching states, it is required t first turn ff the devices t be turned ff. Then, after a prper blanking time, we can prceed t turn n the devices t be turned n. i i i i (a) (b) (c) i i i i i (d) (e) Fig. 3. Five-level cnverter-leg switching states. (a) nnectin t nde i. (b) nnectin t nde. (c) nnectin t nde. (d) nnectin t nde. (e) nnectin t nde. i 33

4 In the transitin between tw adjacent switching states, if (k f k i ) i >0, where k i and k f are the initial and final switching states, respectively; then, the switching lsses cncentrate n the first switch being turned n. All the remaining switches prduce negligible switching lsses since the vltage acrss them when they turn n r ff is apprximately zer. In the transitin between tw adjacent switching states, if (k f k i ) i <0; then, the switching lsses cncentrate n the last switch being turned ff. As befre, all the remaining switches prduce negligible switching lsses since the vltage acrss them when they turn n r ff is apprximately zer. Therefre, an interesting strategy t distribute the switching lsses amng the devices is t alternate the first device being turned-n and t alternate the last device being turned-ff in every transitin between adjacent switching states. On the ther hand, thse devices experiencing lwer cnductin lsses culd be selected t cncentrate the switching lsses s that all devices present similar verall lsses, and ultimately similar junctin temperatures. IV. DISUSSION The cnverter leg in Fig. can be emplyed t implement the same cnverter cnfiguratins as with a dide-clamped tplgy. Fig. 4(a) and Fig. 4(b) shw tw pssible cnfiguratins cnnecting capacitrs between adjacent input terminals t frm a dc-link. Fig. 4(a) represents a five-level bst-buck dc-dc cnverter with cmmn grunding fr the surce and lad systems [0]. Fig. 4(b) represents a multiphase dc-ac cnversin system (it can als be used fr dc-dc cnversin applicatins nt requiring a cmmn grunding fr the lad and surce). In a single phase cnfiguratin, tw cnverter legs are needed. In a multiphase system with p phases, p cnverter legs are needed. The balancing f the dc-link capacitr vltages can be guaranteed in every switching cycle thrugh using apprpriate pulsewidth mdulatin (PWM) strategies ([0]-[]) and cntrls [3], withut the need f intrducing additinal hardware. The balance is achieved by extracting, in every switching cycle, a zer average current frm the inner dc-link pints. If the dc-link capacitrs can be replaced by dc vltage surces, the peratinal capabilities f the cnverter significantly imprve (higher efficiency, lwer utput-vltage distrtin, ), because the capacitr vltage balance is n lnger a prblem and mre degrees f freedm are available t design the PWM strategies. Fig. 4(c) shws an example f a pssible dc-dc r dc-ac cnverter cnfiguratin using a single cnverter leg. The cnverter leg tplgy f Fig. presents a ttal f m (m) cntrlled switching devices. The number f switches is clearly higher than in alternative tplgies. Hwever, these extra switches prvide sme advantages. mpared t dide-clamped tplgies, the prpsed tplgy clamps the blcking vltage f all devices t V dclink /(m) (this is nt the case in dide-clamped tplgies under certain perating cnditins [9]), may present lwer Surce r Lad Surce r Lad V dc4 V dc3 V dc V dc Leg Leg i i Leg (a) i i i (b) i Leg Leg Leg p Lad r Surce Lad r Surce Lad r Surce (c) Fig. 4. nverter cnfiguratins (five-level example). (a) Bst-buck dc-dc cnverter with dc-link capacitrs. (b) Multiphase dc-ac cnverter with dclink capacitrs. (c) Dc-dc r dc-ac single-phase cnverter with dc-link vltage surces. 34

5 cnductin lsses (due t the availability f several paths fr the current t flw, while there is nly ne pssible path in dide-clamped tplgies), and allws distributing the switching lsses amng all the devices (in a dide-clamped tplgy, switching lsses are cncentrated in the available switches). mpared t tplgies with flying capacitrs, the prpsed tplgy avids dealing with the precharge f the flying capacitrs r the lsses and high peak currents that ccur when flying capacitrs with different vltages are cnnected in parallel [7]. The cst and reliability f these capacitrs can als be a prblem. In cases where separate dc vltage surces are available (e.g. Fig. 4(c)), the cmparisn with cascaded H-bridge tplgies is als meaningful. Despite using a significantly higher number f devices, the prpsed tplgy allws perating with a cmmn dc-link fr all legs and dc-link nde vltages that are cnstant with respect t grund. In a cascaded H-bridge tplgy, these dc-link nde vltages may scillate at high frequency, requiring galvanic islatin f the dc vltage surce terminals and prducing cmmn mde currents thrugh parasitic elements that culd be a prblem in the design. The cmparisn f the presented tplgy t cnventinal tw-level cnverter cnfiguratins in terms f efficiency and reliability remains a pending issue. Efficiency is expected t be higher, nt nly because lw vltage-rated devices can be used with better relative perfrmance features, but als because all switching transitins ccur at lwer blcking vltage levels, which in principle shuld prduce lwer switching lsses fr the same switching frequency and switching characteristics ([0]-[]). Reliability might be seen as an imprtant drawback f the presented tplgy because f the use f a high number f cmpnents. Hwever, while in a tw-level cnverter the failure f ne switch usually leads t a full system shut dwn, here the cnverter may cntinue perating, with bviusly sme reductin f the cnverter perfrmance capabilities. V. SIMULATION RESULTS This Sectin presents simulatin results t illustrate the perfrmance f the prpsed tplgy and cntrl strategy. A simple fur-level bst-buck dc-dc cnverter cnfiguratin, shwn in Fig. 5, is selected t facilitate the presentatin and discussin f results. The mdulatin strategy applied is described in [0]. Mdulatin Scheme and a value f the mdulatin parameter = 0.5 are chsen t prduce an utput vltage equal t the input vltage (V A =V B ) [0]. The simulatins are perfrmed using SPIE-based sftware. Fig. 6 presents relevant wavefrms ver tw switching cycles. In Fig. 6(a), nte that the dc-link capacitr vltages (v, v, and v 3 ) are balanced at the end f every switching cycle because a zer switching-cycle-averaged current is injected int the inner dc-link pints. Nte als that the utput leg currents (i a and i b ) present an almst sinusidal shape. This implies that the utput leg currents present nly ne harmnic at the switching frequency, as ppsed t a cnventinal tw-level cnverter, where the utput leg currents, presenting a triangular shape, include additinal harmnics at multiples f the switching frequency. Fig. 6(b) presents the current and vltage f each switch in the bttm half f the input cnverter leg. As can be bserved, in each switching state, the utput current is cnducted thrugh all n-state devices that cnnect the crrespnding input terminal t the utput terminal. The utput current is shared by all pssible current paths. The average cnductin lsses are in general different fr each device. The gating signals f the last six-switch ple (S n, S p3, S n, S p, S n33, and S p3 ) have been adjusted s that these devices are the first t be turned-n and the last t be turnedff in a switching state transitin and, therefre, they cncentrate the switching lsses. Fig. 7 presents the relevant switch current and vltage wavefrms under a transitin frm switching state t 3 (Fig. 7(a)) and a transitin frm switching state 3 t (Fig. 7(b)). In Fig. 7(a), S n is initially turned ff at time = 4.75 s. S n is turned ff 50 ns later. At time = 5. s, S p is turned n. S p is turned n 50 ns later. In Fig. 7(b), S p is initially turned ff at time = s. S p is turned ff 50 ns later. At time = 35. s, S n is turned n. S n is turned n 50 ns later. In bth cases, as desired, switch S n cncentrates the switching lsses. The ther devices change their state at zer vltage with n significant lsses. Sp Sp3 Sn33 v 3 i S v S A i a L a S p S n3 Sp a v b B L b i b S n3 S p S n V A Sn Sp3 v L R L Sn Fig. 5. Fur-level bst-buck dc-dc cnverter implemented with MOSFETs. 35

6 0 75V 5 va A vb B v vv v3 0 0 SEL A va a vb b 8A 0 s 0us 4 s 4us 8 s 8us 3 s 3us 36 s 36us 40 s 40us 44 s 44us 48 s 48us 5 s 5us 56 s 56us 60us 60 s ia ib i a i b 0-0 iisn vsn 0-0 iisn vsn 0-0 iisn vsn 0-0 iisn3 vsn3 0-0 iisp vsp 0 (a) SEL -0 0μs 0us 4μs 4us 8μs 8us 3μs 3us 36μs 36us 40μs 40us 44μs 44us 48μs 48us 5μs 5us 56μs 56us 60us 60μs isp3 vsp3 i Sp3 v Sp3 (b) Fig. 6. Simulatin results ver tw switching cycles in the fllwing cnditins: V A = 00 V, = 0 F, L a = L b = mh, R L = 0, L = 00 F, switching frequency f s = 50 khz, FDPF3860T (00 V, 0 A MOSFETs), gate resistance R g = 0, gate supply vltage V g = 0 V, blanking time t b = 500 ns, and n utput vltage regulatin (pen-lp cntrl). (a) Input and utput dc vltages (v A, v B ), dc-link capacitr vltages (v, v, v 3), leg utput vltages (v a, v b ), leg utput currents (i a, i b ). (b) Vltages and currents f the switches frm the bttm half f the input cnverter leg. VI. ONLUSION A nvel multilevel tplgy and perating principle (patent pending) has been presented. The tplgy is an extensin f the three-level active neutral-pint-clamped cnverter. Switching states are defined s that all pssible current paths cnnect the crrespnding input terminal t the utput terminal and blcking vltages are clamped t the desired level. Transitins between adjacent switching states can be perfrmed selecting the device that cncentrates the switching lsses. If a particular device (e.g., MOSFET) at specific vltage and current ratings is available with gd perfrmance, lw cst, and ideally integrated auxiliary circuitry (gate driver, gate driver pwer supply [4],...); then, this tplgy and cntrl culd be applied t implement a universal and easily scalable cnverter t be used in a number f applicatins. Due t space limitatins, experimental results and ther aspects will be presented in a future paper. REFERENES [] J. Rdríguez, J. Lai, and F. Peng, Multilevel inverters: a survey f tplgies, cntrls and applicatins, IEEE Trans. Ind. Electrn., vl. 49, pp , Aug. 00. [] J. Rdriguez, S. Bernet, B. Wu, J. O. Pntt, and S. Kur, Multilevel vltage-surce-cnverter tplgies fr industrial medium-vltage drives, IEEE Trans. Ind. Electrn., vl. 54, pp , Dec

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