Evaluation of a Delta-Connection of Three Single-Phase Unity Power Factor Rectifier Modules (

Transcription

1 Evaluatin f a Delta-Cnnectin f Three Single-Phase nity Pwer Factr Rectifier Mdules (-Rectifier) in Cmparisn t a Direct Three-Phase Rectifier Realizatin Part Cmpnent Stress Evaluatin, Efficiency, Cntrl Jhann MBÖCK Rland GREL Jhann W. KLAR minibeck@t-nline.at greul@lem.ee.ethz.ch klar@lem.ee.ethz.ch m-pec Pwer Electrnics Cnsultant A-75 Purgstall 5 ASTRA Swiss Federal nstitute f Technlgy (ETH) Zurich Pwer Electrnic Systems Labratry ETH-Zentrum/ETL/H CH-809 Zurich/SWTZERLAD Abstract. n this paper the vltage and current stress f a delta-cnnectin f three single-phase bst-type unity pwer factr rectifier mdules (-Rectifier) is analyzed in rder t perfrm a design cmparable t a direct threephase three-level six-switch unity pwer factr (cnventinal) rectifier system. The cnductin lsses f the pwer semicnductrs are calculated using analytical apprximatins f the average and values f the cmpnent currents, the switching lsses are taken frm previus experimental investigatins. Based n this data an verview f the estimated pwer lsses is given fr the -Rectifier as well as fr the cnventinal rectifier fr 0kW utput pwer, 800VDC utput and 0V/00V/ 80V/50V (, line-t-line) mains vltage. These investigatins finally lead t efficiency and cmpnent cunt figures. Furthermre, special attentin is paid t the cntrl f the whle three-phase system including the DC/DC cnverter utput stages f the line-t-line mdules f the -Rectifier. Finally, tpics f the cntinuatin f the research are identified as, e.g., the realizatin f a prttype in rder t verify the theretical results experimentally als fr unbalanced mains vltage cnditins and with nnideal cmpnents such as nnlinear input inductrs emplying irn pwder cres and the analysis f a -Rectifier being frmed by singlestage SEPC-type line-t-line mdules. inputs f the line-t-line mdules are replaced by threephase thyristr bridge rectifiers (cf. Fig.: gray shaded cmpnents) which d allw a switching ver t the tw remaining phases in case a mains phase fails. TRDCT Mdern high-pwer telecm pwer supply mdules are designed fr a rated utput pwer f typically P,max = 8V. 00A = 0kW and shw a tw-stage tplgy, i.e. a three-phase high pwer factr rectifier des supply an utput-side DC/DC cnverter. Fr the realizatin f a three-phase unity pwer factr rectifier in [] the tplgy depicted in Fig.(a) has been prpsed which is characterized by a delta-cnnectin f three single-phase mdules (-Rectifier). Single-phase unity pwer factr rectifier mdules are highly develped and well knwn in the industry. Furthermre, the - Rectifier shws advantages as high mdularity and the pssibility t deliver the full utput pwer als in case f a missing mains phase if the dide bridge rectifiers at the Fig.: Basic structure f the pwer circuits f three-phase bst-type unity pwer factr rectifiers; (a): delta cnnectin f single-phase mdules (-Rectifier), r (b) direct threephase realizatin as prpsed in [] (denminated as cnventinal rectifier in the fllwing). n cntrast, the utput pwer f a direct three-phase realizatin f the rectifier [] as shwn in Fig.(b) (dented as cnventinal rectifier in the fllwing) which can be cnsidered as a first step in the develpment f the well knwn VEA Rectifier [] has t be reduced t P = / P,max = 0.58P,max fr tw-phase peratin []. n the case at hand the six-switch direct three-phase tplgy has been selected as a basis fr an evaluatin f the -Rectifier instead f the three-switch VEA Rectifier in rder t have an equal number f switches emplyed in bth systems. The six-switch cnventinal

2 rectifier tplgy can be thught t be derived frm the VEA Rectifier tplgy by replacing the tw center pint dides f the bi-directinal switch in each phase by an additinal switch (requiring an additinal gate drive). As a mre detailed analysis shws the efficiency and the pwer factr f the cnventinal rectifier is very clse t the high perfrmance f the VEA Rectifier. The cnventinal rectifier and the -Rectifier emply an equal number f switches and fast recvery free-wheeling dides. Cnsequently, a direct cmparative evaluatin f bth systems can be perfrmed cnsidering the current stresses n the switches, n the dides and n the input inductrs as well as the cmplexity f the cntrl circuit. The fact, that the DC/DC cnversin fr the -Rectifier des require three individual DC/DC cnverters in cntrast t nly a single ne fr the cnventinal rectifier is nt cnsidered in this study because als the DC/DC cnverter stage f the cnventinal rectifier culd be split int several mdules in rder t decrease the pwer t be handled by the individual cnverter and/r t achieve a very cmpact design. We wuld like t pint ut, that the three-level line-tline mdules f the -Rectifier in Fig.(a) culd als be realized in a tw-level structure [] by mitting ne freewheeling dide D F and ne switch S ij per line-t-line mdule. Hwever, this des result in an increased vltage stress f the remaining pwer semicnductrs and/r in a lwer efficiency. Furthermre, there a significantly higher inductance f the input inductr L wuld be required fr equal average ripple i,i f the mains current resulting in a higher inductr vlume. Therefre, the tw-level - Rectifier is nt cnsidered in this paper. The vltage space vectrs f the equivalent input phase vltages u,i [] f the three-level -Rectifier are shwn in Fig.(a) and fr the cnventinal rectifier in Fig.(b). Bth systems shw fr a given input vltage range an equal value fr the required utput vltage level. Û (Û dentes the peak value f the input phase vltage) resulting in an equal vltage stress f the switches S and the free-wheeling dides D F. As described in [] the mdulatin limit M max = / f the -Rectifier results frm the fact, that the zer-sequence cmpnent u 0 f the PWM line-t-line rectifier mdule vltages has t shw a lcal average value equal t zer, i.e. u 0,avg = 0. Fr bth systems ne des nt have t emply a space vectr mdulatin technique fr the input current cntrl. An average current mde cntrller based n the abslute value f the line-t-line currents fr the -Rectifier (cf. Fig.) and directly n the phase currents fr the cnventinal rectifier in cmbinatin with a triangularshaped carrier signal and certain mains vltage precntrl signals m des allw t achieve cmparable perfrmance. There, fr the -Rectifier the current measurement culd be dne as fr single-phase PFC systems n the DC side by means f a cnventinal shunt. Then, the inversin f the triangular-shaped carrier signal f a line-t-line mdule in dependency f the crrespnding sign f the input line-t-line vltage as investigated in [] fr AC side current measurement can be mitted cnsidering the three-level peratin, i.e. 80 phase shift in switching frequency f the gating f the switches S ij+ and S ij. The cntrl f the -Rectifier has t generate six independent switching functins s ij,+ (ij=rs, ST, TR), while the cnventinal rectifier, althugh als utilizing six switches, des emply nly three gating signals, i.e. s s s, (i=r, S, T). i i i Fig.: Vltage space vectrs available fr input current cntrl; (a) three-level -Rectifier, (b) cnventinal rectifier (cf. Fig. in []).

3 Fig.: Blck diagram f the input current cntrl f a linet-line mdule f a three-level -Rectifier (cf. (a)) and phase current cntrl f a cnventinal rectifier (cf. (b)). Accrding t Fig. the -Rectifier and the cnventinal rectifier shw a largely cmparable ripple f the mains phase currents due t the high number f switching states and/r space vectrs available fr current cntrl in bth cases. are calculated in analytical frm. Sectin shws a typical dimensining f a line-t-line mdule f a - Rectifier fr an input line-t-line vltage range f ij V and an utput pwer level f, P. 5kW required fr supplying a DC/DC cnverter, mdule with an estimated efficiency f DC/DC 95%. This leads t an utput pwer f P 0kW fr a threephase unit. n sectin a cntrl cncept is prpsed fr the -Rectifier, which des allw t handle a mains phase lss. Finally, the main advantages and drawbacks f the -Rectifier as cmpared t the cnventinal rectifier are discussed in sectin 5. Furthermre, in sectin 6 an utlk n the cntinuatin f the research is given. STRESSES THE CMPETS n the fllwing the average and the values f the current stresses n the pwer semicnductr cmpnents are calculated as required fr the calculatin f the cnductin lsses. Simple analytical apprximatins are derived which can be used beynd the scpe f this paper fr the dimensining f the pwer cmpnents f a - Rectifier. We assume: a purely sinusidal phase current shape; hmic fundamental mains behavir; n lw frequency vltage drp acrss the bst inductr fr the shaping f the current accrding t the abslute value f a line-t-line mains vltage; cnstant switching frequency; linear behavir f the bst inductrs (inductance nt dependent n the current level. Accrdingly, restricting ur cnsideratins t the psitive half wave f a mains line-t-line vltage u,ij = Û sin( ) we have t prvide by prper mdulatin a lcal average value f the vltage acrss the crrespnding switches S ij+ and S ij f u,ij,avg u,ij. Fr characterizing the mdulatin we define a mdulatin index M Û ˆ () which accrding t Fig. shws a maximum value f M max. () Fig.: Time behavir f a mains phase vltage, f the R equivalent rectifier input phase vltage u, (cf. Fig. in R []) and f the current ripple i, f the mains phase R current i, f the cnventinal rectifier (cf. (a)) and f the R -Rectifier (cf. (b)). n the fllwing in sectin the average and current stresses f the pwer cmpnents f the rectifier systems u,. nductr Current Ripple Fr the calculatin f the input inductr current rippel ne has t decide between tw mdes f peratin f the three-level bst cnverter where u ( t) / fr t < r t > - (), ij u ( t) / fr t - (), ij

4 arcsin( ). (5) ˆ Fr u ( t) / ( M ( 0... ), cf. Eq.()) the ripple, ij envelpe is defined by iˆ, ij i M sin( t)( M sin( t)) (6) with Tp Tp i. (7) 8L L 8 Fr u ( t) / ( (, ij M... ), cf. Eq.()) we have fr the envelpe iˆ, i ( M sin( t) )( M sin( t)). (8) ij The maximum value f the envelpe f the inductr ripple current within a mains half perid results as iˆ i,. (9) ij As a mre detailed analysis shws this maximum value is reduced by a factr f as cmpared t a tw-level bst cnverter realizatin []. Fr M (... ) the glbal value f the ripple current ( value related t a mains vltage perid) is 8 9 i [ ( M M M ), ij, (0) M 6M ( )arctan( ) M ( )]. M 9 (L = L, []). Fr a first estimatin f the cre lsses f an input inductr an irn pwder cre and a mdulatin index M = are assumed. Accrding t (0) and () we then have fr the nrmalized value f the ripple current 0.08 (), ij,, n and with (7) and the specificatins in [] a value f mA (5), ij, what results fr L = L =.mh in a value f the flux linkage ripple, ij, L 56µVs, (6) which is required fr a cre lss calculatin accrding t [0]. The related flux density B fr a number f turns f =Wdg and a tridal cre f type Micrmetals T8-0 (A=.88cm ) results as B 0mT 00Gauss. (7) A Accrding t the three-level characteristic f the line-tline mdule the first harmnic f the inductr current ripple is at twice the pulse frequency f P = khz, i.e. at f Fe = 6kHz. With this set f perating data we have in a first apprximatin fr the cre lsses P Fe W 0 f.9 Fe[Hz] B.0 [Gauss] V Fe [cm ] (8) which can be tlerated in case the cre is arranged in a frced air-cled envirnment. Fr the derivatin f (0) ne has t cnsider that the peratin f the system within a mains half perid is partly accrding t () and partly accrding t (). Fr the nrmalized value (index n) f the input inductr current ripple we define. (), ij,, n, ij, i The glbal nrmalized value f the input inductr ripple current fr M ( 0... ), where the peratin within a mains half perid is nly accrding t (), can be calculated as ( M 8 8 M 9 8, ij,, n i M ). () n Fig.5 the nrmalized value f the line-t-line current and f the input phase current f a -Rectifier as well as the nrmalized ripple f the input phase current f a cnventinal rectifier are depicted. Advantageusly, the -Rectifier shws a lw value f the input current ripple within the whle mdulatin range. Hwever, fr calculating the cre lsses f an input inductr ne has t keep in mind, that three times the inductance value L f the cnventinal system is emplyed in the -Rectifier Fig.5: rmalized value,,n f the phase current f the three-level -Rectifier (cf. (a)) and f a cnventinal rectifier (cf.(b)). Furthermre shwn: value f the ripple f the input current f a line-t-line mdule f a -, ij,, n Rectifier (cf.(c)) as used fr the calculatin f the inductr cre lsses. As a mre detailed analysis shws, fr the cnventinal rectifier the inductr ripple current harmnics d ccur dminantly at the pulse frequency f = f P and at twice the pulse frequency f = f P in abut equal shares. t is interesting that fr assuming a linear dependency n the frequency and a quadratic dependency f the cre lsses n the flux density this des reduce the cre lsses due t the fact, that fr the lss calculatin ne has t take the squares f half f the ttal value B = B = B/, i.e.:

5 P ~ f B B f B f P. (9) As a mre detailed analysis shws the cre lss f a cnventinal rectifier emplying an inductr f equal vlume (L = 700µH, cf. []) in each phase is apprximately P Fe =.W per inductr. ˆ DF, avg DF, 7 ˆ C ut, ˆ ˆ. Current Stresses n the Pwer Cmpnents The ripple f the inductr current is nt cnsidered fr the analytical calculatin f the average and current stresses [6] f the pwer cmpnents. ne has t pint ut that a three-level and a tw-level -Rectifier shw equal (!) current stresses n the mains side dides, n a pwer transistr and n a free-wheeling dide... Mains Dides Fr the average and the current stress n the mains dides D we have D, avg D, ˆ (0) ˆ. ().. Free-wheeling Dides The average and the current stress n the freewheeling dides D F is ˆ D ˆ F avg (), DF, ˆ ˆ 7. ().. Pwer Transistrs The average and the current stress n the pwer transistrs S ij+ and S ij_ is S avg S ( ˆ ˆ ) ˆ ˆ (). (5).. utput Capacitr The current stress n the utput capacitr is calculated using as C ut, D F, DF, avg C ut, (6) ( ˆ ˆ ). (7) The results f the analytical calculatins are cmpiled in Fig.6. D D, avg, S avg S ˆ ˆ Fig.6: Circuit structure f a line-t-line mdule f the - Rectifier and current stresses n the pwer cmpnents accrding t (0) (7). Fr the current stresses n the pwer cmpnents f the cnventinal rectifier we wuld like t refer t [6] fr the sake f brevity.. Third Harmnic njectin Fr the calculatin f the average and current stresses n the pwer cmpnents an ideal sinusidal shape f the input current f a line-t-line rectifier mdule has been assumed. As prpsed in [] a reductin f the peak value f the pwer cmpnent currents can be achieved by a third harmnic f the line-t-line currents (zer sequence cmpnent), which culd be imagined as a current circulating inside the delta-cnnectin. This is f particular interest in cnnectin with the magnetic dimensining f the input inductr. Fr minimum peak value the amplitude f the third harmnic shuld be / 6 f the line-t-line current fundamental. The and average values f the cmpnent currents with third harmnic injectin shw nly minr differences t the values calculated fr purely sinusidal current, e.g. we have fr the mains dides D ˆ D (0), avg and D, D, avg D, ˆ withut rd harmnic () 9 ˆ (8) 8 7ˆ with rd harmnic injectin. (9) Fr the cnventinal rectifier a zer sequence vltage cmpnent is emplyed in rder t extend the mdulatin range M 0... as given fr purely sinusidal mdulatin t M (0... / ). Advantageusly this furthermre results in a reductin f the input inductr ripple current and in a reductin f the amplitude f the third harmnic f the center pint current. The ptimum rati f the third

6 harmnic cmpnent amplitude t the rectifier input vltage fundamental amplitude t be generated differs accrding t the ptimizatin t be perfrmed; e.g. fr maximum mdulatin range we have a rati f M /M = / 6, fr a minimizatin f the ripple current value M /M / and fr the eliminatin f the third harmnic f the center pint current M /M = 7 / 7. The current stress values f the cnventinal rectifier have been calculated based n purely sinusidal mdulatin in [6]. As fr the - Rectifier these current values d hld with sufficient accuracy als in case a third harmnic is injected in rder t extend the mdulatin range. DMESG, EFFCECY Fr the dimensining f the -Rectifier the fllwing specificatins are assumed: line-t-line input vltage range V utput vltage =800V, ij ttal utput pwer f the three-phase system P = 0kW, which results in an input pwer f a line-t-line mdule f P, =.5kW assuming an efficiency the DC/DC cnverter cnnected in series f DC/DC 95% pulse frequency f P = khz. The stresses n the cmpnents and the resulting cmpnent pwer lsses are listed in Tab.. The calculatins are based n the analytical expressins derived in sectin and n experimental switching lss data accrding t [7] and [8]. The efficiency is fr an input line-t-line vltage f, e.g. ij 80V in the, range f = 97.% fr hard switching. n case a sft turn-n technique accrding t [9] is emplyed which des nt cause an increase f the transient turn-ff vervltage the efficiency culd be imprved t S = 97.7%. The stresses n the pwer cmpnents f a cnventinal rectifier f equal specificatins (utput pwer P = 0.5kW) were calculated based n [6] and are listed in Tab.. As a cmparisn f Tabs. and shws, the efficiency f the -Rectifier is lwer by % as cmpared t the cnventinal rectifier. This is due t the higher current stress n the utput electrlytic capacitrs and/r due t the higher resulting capacitr lsses. The differences f the lsses f the semicnductr cmpnents are nt significant because the peak current stress f the -Rectifier is reduced by a factr f as cmpared t the cnventinal rectifier but the stress is applied within the whle mains perid in cntrast t the cnventinal rectifier where the peak current stress is higher but applied nly fr half a mains perid. nput pwer P. = W nput vltage,l-l = V nput current (line-t-line),ij, = A utput vltage = V Switch current R DS,n = C Cnductin lss Turn-n (k n =8.5µJ/A) Turn-ff (k ff =8.µJ/A) x Switch ttal lsses Free-wheeling dide current DF0 =0.95V, R DF =m x Free-wheeling dide lsses Mains dide current D0 =0.85V, R D =0m x Mains dide lsses Ttal pwer semicnductr lsses S, = A S,avg = A P S,C = W P S,n = W P S,ff = W P S = W DF, = A DF,avg = A P DF = W D, = A D,avg = A P D = W W nput chke (R L =5m, P FE P L = W =5W) utput capacitr current C, = A x utput capacitr 70µF/00V (R ESR =0.) P C = W Auxiliary pwer P aux = W (husekeeping, fans) Snubbers, PCB, var. P add = W distributed lsses Ttal pwer lsses P = W Efficiency = % Efficiency with turn-n s = % snubber Tab.: Lsses f a.5kw/khz line-t-line mdule f a - Rectifier. The imprvement f the verall efficiency in case a turn-n snubber is emplyed is in the range f %. nput pwer P = W nput vltage,l-l = V nput current,i, = A utput vltage = V Switch current S, = A R DS,n = C S,avg = A Cnductin lss P S,C = W Turn-n (k n =8.5µJ/A) P S,n = W Turn-ff (k ff =8.µJ/A) P S,ff = W 6x Switch ttal lsses P S = W Free-wheeling dide current DF, = A DF0 =0.95V, R DF =m DF,avg = A 6x Free-wheeling dide lsses P DF = W Mains dide current D, = A D0 =0.85V, R D =0m D,avg = A 6x Mains dide lsses P D = W Ttal pwer semicnductr lsses W nput chke (R L = 5m, P FE = 5W, wrst case) P L = W utput capacitr current C, = A x utput capacitr 70µF/00V (R ESR =0.) P C = W Auxiliary pwer P aux = W (husekeeping, fans) Snubbers, PCB, var. distributed lsses P add = W Ttal pwer lsses P = W Efficiency = % Efficiency with turn-n snubber s = % Tab.: Lsses f a 0.5kW/kHz three-phase cnventinal rectifier. The imprvement f the verall efficiency in case a turn-n snubber is emplyed is in the range f % (as fr the -Rectifier, cf. Tab.).

7 Fig.7: Cntrl f a -Rectifier based three-phase telecmmunicatins pwer supply mdule tlerating heavy mains vltage unbalance (and/r twphase peratin) realized in multi-layer cntrl structure as used fr pwer electrnic building blcks [5]. n Table the semicnductr cmpnents emplyed fr the calculatin f the efficiency are cmpiled. Part S D F D Type nfinen SPW760C nt. Rect. HFA5PB60 ST TY00 (Thyristr) Tab.: List f pwer semicnductr cmpnents which have been selected as basis fr the calculatin f the efficiency f the -Rectifier (cf. Tab.) and f the cnventinal rectifier (cf. Tab.). SYSTEM CTRL Figure 7 shws the structure f the cntrl f a threephase -Rectifier-based telecmmunicatins pwer supply mdule, which is able t handle heavily unbalanced mains vltage cnditins. The cascaded system cntrl is rganized in a multi-layer structure as emplyed in pwer electrnic building blcks (PEBB) [5]. Crrespnding t the dminant time cnstants there are fur layers: Hardware manager: transistr gate-drive, current sensrs, fast prtectin (<µs); Tplgy manager: current cntrl, hardware interfaces, cmmunicatin backbne, synchrnizatin and pwer management f the line-t-line mdules (<00µs); Applicatin manager: mains frequency current shaping, cnventinal prtectin, utput vltage cntrl (<0ms); System manager: cmmunicatin t central supervising unit, pwer management. The switching functins s ij+ and s ij f each line-t-line mdule are generated by an inner current cntrl (cf. Fig.). This inner cntrl lp requires a current reference value i,ij *, ij = RS, ST, TR, which is generated by multiplying a reference cnductance g* with the actual abslute value f the line-t-line vltages u,ij. The cnductance g* is defined by the DC/DC cnverter utput vltage cntrl and by the mdule utput vltage cntrller g * ij (bth realized as P-type cntrllers), i.e. g* = g* + g ij. Highly dynamic limiting f g* is prvided in rder nt t exceed the maximum allwable peak current stress max f the pwer semicnductr cmpnents and/r a maximum level u,max (as defined by the vltage rating f the electrlytic capacitrs and by blcking capability f the pwer semicnductrs) f the rectifier mdule utput vltage in case f, e.g. a lad dump r in case f the return f a missing mains phase. The reference cnductance g * is derived with lw bandwidth (f g 0Hz) frm the DC/DC cnverter utput vltage cntrller p * = i *. ut u * ut, cnsequently a divisin by the sum f squares f the input line-t-line vltage value has t be perfrmed fr calculating a mains-side reference input cnductance fr all line-t-line rectifier mdules which des fulfill the utput pwer requirement.

8 The limitatin f g * is with reference t the peak values f the three line-t-line mains vltages in rder nt t exceed max in the statinary case. We wuld like t pint ut that the abve-mentined requirements are given nt nly fr the -Rectifier but fr any tw-stage three-phase and/r single-phase rectifier system. Fr the cnventinal rectifier the different functins need t be implemented nly nce [], fr the -Rectifier sme functins have t be implemented fr each line-t-line mdule. A special issue f the realizatin f a three-phase unit by three line-t-line mdules is the divisin f the utput vltage cntrller utput (ttal utput current reference value) int reference values f the utput currents i * ut,ij f the DC/DC cnverter cnnected t the line-t-line * mdules. The calculatin f i ut,ij is perfrmed by multipliers cnsidering the squares f the nrmalized input line-t-line vltages. The multipliers are shwn in Fig.7 n the left-hand-side f the utput vltage cntrller. The utput current reference values i * ut,ij are limited accrding t the maximum admissible utput current ut,max f the DC/DC cnverters as defined by the system design and are decreased in case the rectifier mdule utput vltage (DC link vltage) ges under a certain minimum level u *,min. 5 DSCSS As the analysis in the previus sectins shws the - Rectifier is characterized by a vltage and current stress n the pwer transistrs and free-wheeling dides and/r a realizatin effrt f the pwer circuit which is very much cmparable t the cnventinal direct three-phase apprach. Als, cncerning the cmplexity f the cntrl bth systems des nt shw large differences. The main difference is the additinal effrt fr the tw-phase input bridge rectifier f each line-t-line mdule which has t be cmpared t tw input dides as required fr each phase f the cnventinal rectifier and the current stress n the DC link capacitrs. n case f a symmetrical mains the cnventinal rectifier shws a significantly lwer current stress n the utput capacitrs due t the cnstant pwer flw f the three-phase system. This, hwever is nly a minr advantage in case a high hld-up time is required where a large capacitance f the utput capacitrs has t be installed. Further research will shw the pssibility f reducing the lsses f the DC link capacitrs by cnnecting fil-type capacitrs in parallel fr the handling f the switching frequency cmpnents f the capacitr current. The secnd weakness f the -Rectifier is the high effrt fr the realizatin f a DC/DC cnverter utput stage. Hwever, fr high-pwer telecm pwer supply mdules with an utput pwer in the range f P 0kW this is nt f much relevance because the DC/DC cnverters culd be realized by six individual mdules with 00V input vltage, where always a single DC/DC cnverter mdule is cnnected t a partial utput vltage f a linet-line rectifier mdule and all DC/DC cnverter mdule utputs are cnnected in parallel. There, each DC/DC cnverter mdule has t be designed fr a cnvenient pwer level f.5 kw, which des allw t avid bulky heatsinks and/r transfrmers and/r des facilitate a very cmpact design. The cntrl f the individual mdules culd easily be integrated int the multi-layer cntrl structure f the -Rectifier. As a main advantage f the -Rectifier, ne has t pint ut that the mdificatin f the tw-phase input rectifier bridge t a three-phase thyristr bridge des allw t supply the full utput pwer als in the case f a mains phase lss by switching ver t the tw remaining mains phases. There, hwever, ne shuld take care that the resulting high current stress n the remaining phases des nt cause prblems. Furthermre, the thyristrs culd be emplyed fr shrt-circuiting the pre-charge resistrs after utput capacitr pre-charging at system start-up. A further advantage f the -Rectifier is the pssibility f using a lw-cst shunt fr the input current measurement. This cncept is well knwn frm single-phase PFC. 6 CCLSS As this paper shws the -Rectifier is an interesting alternative t a direct three-phase three-level unity pwer factr rectifier system. Accrdingly the -Rectifier cncept will be further investigated at the ETH Zurich in cllabratin with m-pec where the main tpics will be: practical realizatin f a -Rectifier system including a DC/DC cnversin cnnected in series and the system cntrl; investigatin f the influence f a mains vltage unbalance, f a nn-linearity f the bst inductr irn cres, and f the discntinuus inductr current mde ccurring at light lad cncerning the frmatin f a zer sequence cmpnent f the ripple currents f the line-t-line input currents and/r the partial mutual cmpensatin f the ripple cmpnents f the line-tline currents in the mains phase currents; single-stage realizatin f the line-t-line mdules, e.g. in the frm f a SEPC cnverter (cf. Fig.8, []). The increase f the vltage and current stresses as cmpared t the bst-type mdules culd be f minr cncern in lw pwer and/r lw vltage applicatins where a true three phase system is prvided as, e.g. fr the pwering f the in-flight entertainment systems in future airplanes where 00W culd be a typical pwer demand per passenger seat in the business-class. Fig.8: Basic structure f the pwer circuit f a SEPC-type -Rectifier [].

9 REFERECES [] Klar, J. W., Stögerer, F., and ishida, Y.: Evaluatin f a Delta-Cnnectin f Three Single-Phase nity Pwer Factr Rectifier Systems (-Rectifier) in Cmparisn t a Direct Three-Phase Rectifier Realizatin. Part Mdulatin Schemes and nput Current Ripple. Prceedings f the 7 th Eurpean Pwer Quality Cnference, uremberg, Germany, June 9-, pp (00). [] Klar, J. W., and Zach, F. C.: A vel Three-Phase tility nterface Minimizing Line Current Harmnics f High- Pwer Telecmmunicatins Rectifier Mdules. Prceedings f the 6 th EEE nternatinal Telecmmunicatins Energy Cnference, Vancuver, Canada, ct. 0-v., pp (99). [] Zha, Y., Li, Y., and Lip, T.A.: Frce Cmmutated Three-Level Bst Type Rectifier. Recrd f the 8th EEE ndustry Applicatins Sciety Annual Meeting, Trnt, Canada, ct. -8, Vl., pp (99). [] Stögerer, F., Miniböck, J., and Klar, J. W.: A vel Cncept fr Mains Vltage Prprtinal nput Current Shaping f a VEA Rectifier Eliminating Cntrller Multipliers. Part : peratin fr Heavily nbalanced Mains Phase Vltages and Wide nput Vltage Range. Prceedings f the 6th EEE Applied Pwer Electrnics Cnference, Anaheim, March -8, Vl., pp (00). [5] Zehringer, R.W., Pieder J., Suter, M., Celanvic,.: Pwer Electrnics Slutins fr Distributed Pwer Generatin. Prceedings f the rd nternatinal Pwer Electrnics Cnference, uremberg, Germany, June 9-, pp. -8 (00). [6] Klar, J.W., Ertl, H., and Zach, F. C.: Design and Experimental nvestigatin f a Three-Phase High Pwer Density High Efficiency nity Pwer Factr PWM (VEA) Rectifier Emplying a vel Pwer Semicnductr Mdule. Prceedings f the th EEE Applied Pwer Electrnics Cnference, San Jse, SA, March -7, Vl., pp. 5-5 (996). [7] Miniböck, J., Stögerer, F., Klar, J.W.: Experimental Analysis f the Applicatin f Latest SiC Dide and ClMS Pwer Transistr Technlgy in a 0kW Three- Phase PWM (VEA) Rectifier. Prceedings f the rd nternatinal Pwer Electrnics Cnference, uremberg, Germany, June 9-, pp. -5 (00). [8] Miniböck, J., Stögerer, F., and Klar, J.W.: Cmparative Theretical and Experimental Evaluatin f Bridge Leg Tplgies f a Three-Phase Three-Level nity Pwer Factr Rectifier. Prceedings f the EEE Pwer Electrnics Specialists Cnference, Vancuver, Canada, June 7-, Vl., pp (00). [9] Mantv, G., and Wallace, K.: Dide Recvery Current Suppressin Circuit. Prceedings f the nd nternatinal Telecmmunicatins Energy Cnference, Phenix (AZ), SA, Sept. 0-, pp. 5-9 (000). [0]Micrmetals: rn Pwder Cres, Pwer Cnversin & Line Filter Applicatins. Catalg /ssue H, 995. []Ayyanar, R., Mhan,., and Sun, J.: Single-Stage Three- Phase Pwer-Factr-Crrectin Circuit sing Three slated Single-Phase SEPC Cnverters perating in CCM. Prceedings f the st Pwer Electrnics Specialists Cnference, Galway, reland, June 8-, Vl., pp (000).ac