Features. for DDR applications. VIN C92 D11 D12 PVCC BST2 BST1 GDH2 GDH1 C93 C94 VPN2 VPN1 CS2+ CS1+ RCS- RCS- CS2- CS1- IN1- IN2- COMP1 REFIN VIN2

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1 Descriptin The SC446 is a high-frequency dual synchrnus stepdwn switching pwer supply cntrller t prvides utf-phase high-current utput gate drives t all N-channel MOSFET pwer stages The SC446 perates in synchrnus cntinuus-cnductin mde Bth phases are capable f maintaining regulatin with surcing r sinking lad currents, making the SC446 suitable fr generating bth DDQ and the tracking TT fr DD applicatins The SC446 emplys fixed frequency peak current-mde cntrl fr the ease f frequency cmpensatin and fast transient respnse The dual-phase step-dwn cntrllers f the SC446 can be cnfigured t prvide tw individually cntrlled and regulated utputs r a single utput with shared current in each phase The Step-dwn cntrllers perate frm an input f at least 47 and are capable f regulating utputs as lw as 05 The step-dwn cntrllers in the SC446 have the prvisin t sense a synthesized MOSFET DS(ON) fr current-mde cntrl This sensing scheme (US patent 6,44,597) eliminates the need f the current-sense resistr and is mre nise-immune than direct sensing f the high-side r the lw-side MOSFET vltage Precise current-sensing with sense resistr is ptinal ndividual sft-start and verlad shutdwn timer is included in each step-dwn cntrller The SC446 implements hiccup verlad prtectin n tw-phase singleutput cnfiguratin, the master timer cntrls the sftstart and verlad shutdwn functins f bth cntrllers Typical Applicatin Circuit SC446 Dual-Phase Single r Tw Output Synchrnus Step-Dwn Cntrllers N Features -Phase synchrnus cntinuus cnductin mde fr high efficiency step-dwn cnverters Out f phase peratin fr lw input current ripples Output surce and sink currents Fixed frequency peak current-mde cntrl 75m/-0m maximum current sense vltage Synthesized MOSFET DS(ON) current-sensing fr lw-cst applicatins Optinal resistr current-sensing fr precise currentlimit Dual utputs r -phase single utput peratin Excellent current sharing between individual phases Wide input vltage range: 47 t 6 ndividual sft-start, verlad shutdwn and enable Duty cycle up t 88% 05 feedback vltage fr lw-vltage utputs External reference input fr DD applicatins Buffered DDQ / utput Prgrammable frequency up t MHz per phase External synchrnizatin ndustrial temperature range 8-lead TSSOP package Applicatins Telecmmunicatin pwer supplies DD memry pwer supplies Graphic pwer supplies Servers and base statins C9 D D PCC O L Q 73 C93 BST GDH BST GDH C94 74 Q L O C99 C95 CFLTE Q Q4 CFLTE C98 C00 79 C96 75 FLTE GDL GDL PGND FLTE 76 C97 80 CS PN PN CS CS CS 8 CS- CS- CS- CS- 8 N- N- C0 COMP COMP C0 83 C03 EF EFN EF C04 C05 84 N N AGND SYNC SYNC sc 85 SS/EN ACC N Figure C06 C07 SS/EN EFOUT U SC446 C08 Dual ndependant Outputs C09 evisin: March 3, 004 US Patent N 6,44,597, wwwsemtechcm

2 SC446 Abslute Maximum ating Exceeding the specificatins belw may result in permanent damage t the device, r device malfunctin Operatin utside f the parameters specified in the Electrical Characteristics sectin is nt implied Parameter Supply Electrical Characteristics Parameter Undervltage Lckut ACC Start ACC Start ACC Operating ACC Quiescent Threshld Hysteresis Current Current in ULO Channel Errr Amplifier Symbl ACC ACC CC Nn-inverting nput ltage N Nn-inverting ltage Fr Step-Dwn Cntrllers nput Line egulatin TH ACC Cnditins 004 Semtech Crp wwwsemtechcm Min Typ ncreasing 5 7 HYST Max Units ACC 6 ma ACC ACC TH ACC TH ma < ACC< 5 00 %/ nput Offset ltage ± 3 m nverting nput Bias Current N- Amplifier Transcnductance G Amplifier Open-Lp Gain a L 00 M 60 O na Ω µ 6 dβ Amplifier Unity Gain Bandwidth 5 ΜΗz Minimum COMP Switching Threshld CS SS S- ncreasing C 0 Symbl nput ltage Fr the Secnd Cnverter N EF, EF N EF OUT ltages EF Maximum atings Units ACC, PCC -03 t 0 03 t 0 - B BST 03 t 3, 03 t ACC0 3 N-, EFOUT ltage EFN High-Side Driver Supply ltages ST, N-, N- ltages N- COMP, COMP ltages OMP, CS, CS-, CS and CS- ltages CS, S-, SYNC ltage YNC SS/EN AND SS/EN ltages S, Peak Gate Drive Currents GDH t 6-03 t ACC t ACC0 3 C COMP C CS, CS- 03 t ACC S 03 t ACC0 3 S SS 03 t 6,,, GDH GDL DL - - G 3 A Peak PN and PN Output Currents, 00 ma PN PN Ambient Temperature ange T A -40 t 85 C Thermal Thermal Strage esistance Junctin t Case (TSSOP-8) esistance Junctin t Ambient (TSSOP-8) Temperature ange θ JC 3 C/ W θ JA 84 C/ W T STG 60 t 50 LEA 60 - C Lead Temperature (Sldering) 0 sec T D C Maximum Junctin Temperature T J 50 C Unless specified: ACC PCC N, BST BST, SYNC 0, OSC 5kΩ, -40 C < T A T J < 85 C

3 SC446 Electrical Characteristics (Cnt) Unless specified: ACC PCC N, BST BST, SYNC 0, OSC 5kΩ, -40 C < T A T J < 85 C Parameter Symbl Amplifier Output Sink Current N- Amplifier Output Surce Current N- Channel Errr Amplifier Cnditins, C OMP 0, COMP High-side Gate Drive Peak Sink Current BST, A BST 004 Semtech Crp 3 wwwsemtechcm Min Typ Max Units 5 6 µa 5 µa nput Cmmn-mde ltage ange ( Nte ) 0 3 nverting nput ltage ange ( Nte ) 0 ACC nput Offset ltage 5 ± 3 m Nn-inverting nput Bias Current N nverting nput Bias Current N- nverting nput ltage fr -Phase Single Output Operatin Amplifier Transcnductance G Amplifier Open-Lp Gain a L M 60 O na na 5 Ω µ 6 dβ Amplifier Unity Gain Bandwidth 5 MHz Minimum COMP Switching Threshld CS SS S- ncreasing C 0 A mplifier Output Sink Current 5 COMP 6 µa A mplifier Output Surce Current 5 COMP µa Oscillatr Channel Frequency f f KHz CH, CH S ynchrnizing Frequency ( Nte ) f KHz CH SYNC nput High ltage 5 SYNC nput Lw ltage 0 5 SYNC nput Current SYN C Channel Maximum Duty Cycle D AX, Channel Minimum Duty Cycle D N, Current-limit Cmparatrs S YNC S YNC 0 D M MAX 8 M D N 00 µa 8 % M 0 % nput Cmmn-Mde ange 0 ACC - Cycle-by-cycle Peak Current Limit alley Current Overlad Shutdwn Threshld LM, LM LM-, LM- Psitive Current-Sense nput Bias Current S, Negative Current Gate Drivers High-side Current Current-Sense nput Bias Gate Drive Peak Surce C CS CS-, CS- CS- 05, C S- Surcing Mde CS- 05, C S- Sinking Mde C S CS- 0 C S- CS- 0 C S CS- 0 C S CS- 0 BST m m µa µa, 5 A BST

4 SC446 Electrical Characteristics (Cnt) Unless specified: ACC PCC N, BST BST, SYNC 0, OSC 5kΩ, -40 C < T A T J < 85 C Parameter Lw-side Current Lw-side Gate Drive Peak Surce Gate Drive Peak Sink Current Symbl Cnditins 004 Semtech Crp 4 wwwsemtechcm Min Typ Max Units ACC PCC 5 A ACC PCC A Gate Drive ise Time C L 00pF 0 ns Gate Drive Fall Time C L 00pF 0 ns Lw-side Gate Drive t High-side Gate Drive Nn-verlapping Delay High-side Gate Drive t Lw-side Gate Drive Nn-verlapping Delay Minimum On-Time Sft-Start, Overlad Latchff and Enable Sft-Start Charging Current S, Overlad ltage Latchff Enabling Sft-Start C L 0 90 ns C L 0 90 ns TA 5 C 50 ns S SS S S S SS Overlad Latchff N- Threshld SS Overlad Latchff N- Threshld SS Sft-Start Discharge Current SS(DS), SS(DS) N- N- S S 5 µa and SS 38, D N- ncreasing ecreasing 38, Decreasing N- 05, EF 05, EFN S S S EF 07 X EFN 4 µa Overlad Latchff ecvery Sft-Start SSC, ltage SS and SS Decreasing SSC Gate Drive Disable SS/EN ltage Gate Drive Enable SS/EN ltage 5 Channel irtual Phase Nde ltage Output High ltage PNH Output Lw ltage PNL Output Surcing Current -00µ A, PN BST 00µ A, PN BST B ST 4, PN P CC CC P m 7 ma Output Sinking Current BST 4, 0 7 ma PN Channel irtual Phase Nde ltage Output High ltage PNH Output Lw ltage PNL Output Surcing Current -00µ A, PN BST 00µ A, PN BST B ST 4, PN N N m 7 ma O utput Sinking Current BST 4, 0 7 ma PN External eference Buffer External eference nput ltage ange EFN 0 4 Buffered Output ltage EFOUT EFN 5, EFOUT -ma EFN 00 - EFN EFN 00

5 SC446 Electrical Characteristics (Cnt) Unless specified: ACC PCC N, BST BST, SYNC 0, OSC 5kΩ, -40 C < T A T J < 85 C Parameter Lad egulatin nternal 05 eference Buffer Symbl Output ltage EF Lad egulatin EF Cnditins Min Typ Max Units 0 < < -5mA 00 %/ma EFOUT -ma 90 Ntes: () Guaranteed by design nt tested in prductin () This device is ESD sensitive Use f standard ESD handling precautins is required m 0 < < -5mA 005 %/ma EF Pin Cnfiguratins CS CS- OSC N- COMP SYNC AGND EF EF OUT EF N COMP N- CS- CS (TOP EW) (8-Pin TSSOP) Figure SS/EN PN BST GDH GDL PCC PGND GDL GDH BST PN N ACC SS/EN Ordering nfrmatin Device ) S C446TSTT SC446EB ) P ackage ( TSSOP- 8 Evaluatin Bard ( emp ange( T T A ) -40 t 85 C Ntes: () Only available in tape and reel packaging A reel cntains 500 devices fr TSSOP package () Lead free prduct 004 Semtech Crp 5 wwwsemtechcm

6 SC446 Pin Descriptins TSSOP Package Pin Pin Name Pin Functin C S The Nn-inverting nput f the Current-sense Amplifier/Cmparatr fr the Cntrller CS- The nverting nput f the Current-sense Amplifier/Cmparatr fr the Cntrller tied t the utput f the cnverter Nrmally 3 OSC An external resistr cnnected frm this pin t GND sets the scillatr frequency 4 N- nverting nput f the Errr Amplifier fr the Step-dwn Cntrller Tie an external resistive divider between OUTPUT and the grund fr utput vltage sensing 5 COMP The Errr Amplifier Output fr Step-dwn Cntrller cmpensatin This pin is used fr lp 6 SYNC Edge-triggered Synchrnizatin nput When nt synchrnized, tie this pin t a vltage abve 5 r the grund An external clck (frequency > frequency set with OSC) at this pin synchrnizes the cntrllers 7 A GND Analg Signal Grund 8 EF Buffered Output f the nternal 05 eference The nn-inverting input f the errr amplifier fr the step-dwn cnverter is internally cnnected t this pin 9 EF 0 EF Buffered utput f the external vltage applied t Pin 0 O UT N An external eference vltage is applied t this pinthe nn-inverting input amplifier fr the step-dwn cnverter is internally cnnected t this pin f the errr COMP The Errr Amplifier Output fr Step-dwn Cntrller cmpensatin This pin is used fr lp N- nverting nput f the Errr Amplifier fr the Step-dwn Cntrller Tie an external resistive divider between utput and the grund fr utput vltage sensing Tie t ACC fr tw-phase single utput applicatins 3 CS- The nverting nput f the Current-sense Amplifier/Cmparatr fr the Cntrller tied t the utput f the cnverter Nrmally 4 CS The Nn-inverting nput f the Current-sense Amplifier/Cmparatr fr the Cntrller 5 SS/EN An external capacitr tied t this pin sets (i) the sft-start time (ii) utput verlad latch ff time fr step-dwn cnverter Pulling this pin belw 07 shuts ff the gate drivers fr the secnd cntrller Leave pen fr tw-phase single utput applicatins 6 A CC Pwer Supply ltage fr the Analg Prtin f the Cntrllers 7 N 8 PN 9 BST This pin is tied t the vltage supplying the drain f the high side pwer MOSFET f cnverter This pin is used nly in "Cmbi" current sense The Secnd Step-dwn Cnverter irtual Phase Nde (Unladed) Used fr "Cmbi" current sense nly This pin is left pen when sensing current with a sense resistr at the cnverter utput Btstrapped Supply fr the High-side Gate Drive Cnnect t a btstrap capacitr and an external dide as described in applicatin infrmatin 0 GDH Gate Drive Output fr the High-side N-channel MOSFET f Output swings frm grund t BST Gate drive vltage 004 Semtech Crp 6 wwwsemtechcm

7 SC446 Pin Descriptins Pin Pin Name Pin Functin GDL Gate Drive Output fr the Lw-side N-channel MOSFET f Output swings frm grund t PCC Gate drive vltage P GND Grund Supply fr All the Gate drivers 3 P CC Pwer Supply ltage fr Lw-side MOSFET Drivers 4 GDL 5 GDH Gate Drive Output fr the Lw-side N-channel MOSFET f Output swings frm grund t PCC Gate Drive Output fr the High-side N-channel MOSFET f Output swings frm grund t BST Gate drive vltage Gate drive vltage 6 BST 7 PN 8 SS/EN Btstrapped Supply fr the High-side Gate Drive Cnnect t a btstrap capacitr and an external dide as described in applicatin infrmatin The First Step-dwn Cnverter irtual Phase Nde (Unladed) Used fr "Cmbi" current sense nly This pin is left pen when sensing current with a sense resistr at the cnverter utput An external capacitr tied t this pin sets (i) the sft-start time (ii) utput verlad latch ff time fr buck cnverter Pulling this pin belw 07 shuts ff the gate drivers fr the first cntrller 004 Semtech Crp 7 wwwsemtechcm

8 SC446 Blck Diagram SYNC 6 OSC 3 COMP 5 N- 4 EF/N 8 - EA 05 OSCLLATO - PWM CLK CLK - ULO S Q EFEENCE ULO 43/45 Nn-Overlapping Cnductin Cntrl ACC 6 BST 6 GDH 5 PCC 3 GDL 4 CS CS- COMP N- EF N/N 0 EF OUT 9 AGND 7 - SEN 75m 0m EA LM LM- SLOPE COMP Σ OCN 07 EF OUT 075 EF Sft-Start And Overlad Hiccup Cntrl OL DSBL PN 7 PGND SS/EN 8 GDH 0 N 7 PN 8 GDL Figure 3 SC446 Blck Diagram (Channel PWM Cntrl Only) OCN N- 075( EF) / 07( EFOUT) - µα S Q OL SS/EN 05/3 DSBL ULO 09/ 34µΑ Figure 4 Sft-Start and Overlad Hiccup Cntrl Circuit 004 Semtech Crp 8 wwwsemtechcm

9 SC446 Operatin Overview The SC446 is a cnstant frequency phase currentmde step-dwn PWM switching cntrller driving all N- channel MOSFET s The tw channels f the cntrller perate at 80 degrees ut f phase frm each ther Since input currents are interleaved in a tw-phase cnverter, input ripple current is lwer and smaller input capacitr can be used fr filtering Als, with lwer inductr current and smaller inductr ripple current per phase, verall lsses are reduced The SC446 perates in synchrnus cntinuuscnductin mde t can be cnfigured either as tw independent step-dwn cntrllers prducing tw separate utputs r as a dual-phase single-utput cntrller by tying the N- pin t CC n single utput peratin, the channel ne errr amplifier cntrls bth channels and the channel tw errr amplifier is disabled Sft-start and verlad hiccup f bth channels is synchrnized t channel ne Frequency Setting and Synchrnizatin The internal scillatr f the SC446 runs at twice the phase frequency The free-running frequency f the scillatr can be prgrammed with an external resistr frm the OSC pin t the grund The step-dwn cntrllers are capable f perating up t MHz t is necessary t cnsider the perating duty-rati befre deciding the switching frequency See Applicatins nfrmatin sectin fr mre details When synchrnized externally, the applied clck frequency shuld be twice the desired phase frequency The synchrnizing clck frequency shuld als be between - 33 times the set free-running frequency Cntrl Lp The SC446 uses peak current-mde cntrl fr fast transient respnse, ease f cmpensatin and current sharing in single utput peratin The lw-side MOSFET f each channel is turned ff at the falling-edge f the phase timing clck After a brief nn-verlapping time interval f 90ns, the high-side MOSFET is turned n The phase inductr current ramps up When the sensed inductr current reaches the threshld determined by the errr amplifier utput and ramp cmpensatin, the high-side MOSFET is turned ff After a nn-verlapping cnductin time f 90ns, the lw-side MOSFET is turned n The supply vltages fr the high-side gate drivers are btained frm tw dide-capacitr btstrap circuits f the btstrap capacitr is charged frm CC, the high-side gate drive vltage swing will be frm apprximately CC t the grund The pwer dissipated in the high-side gate driver is nt higher with higher vltage swing because the gatesurce vltage f the high-side MOSFET still swing frm zer t CC The utputs f the lw-side gate drivers swing frm C t the grund The SC446 has internal ramp-cmpensatin t prevent sub-harmnic scillatin when perating abve 50% duty cycle There is enugh ramp internally fr a sensed vltage ripple between ¼ t /3 f the full-scale sensed vltage limit f 75m The maximum sensed vltage limit is unaffected by the cmpensatin ramp Current-Sensing There are tw ways t sense the inductr current fr current-mde cntrl with the SC446 Since the peak inductr current crrespnds t 75m f sensed vltage (CS - CS-), resistr current sensing can be used at the utput withut resulting in excessive pwer dissipatin Althugh accurate and far easier t lay ut than highside resistr sensing, a pair f precisin sense resistrs adds cst t the cnverter The SC446 has prvisin t recnstruct a differential vltage prprtinal t the inductr current at the utput f the cnverter (US patent 6,44,597) The vltage t current rati r the equivalent sense resistance eq is a cmbinatin f high-side and lwside MOSFET DS(ON) s and the inductr series resistance (hence the name Cmbi-Sense ) The SC446 prvides the virtual phase vltages PN and PN (these are 004 Semtech Crp 9 wwwsemtechcm

10 SC446 Operatin (Cnt) unladed versins f their respective pwer phase vltages) fr current sensing This methd des nt require any precisin sense resistr t is cheaper t implement but is less accurate than resistr current sensing Since the sensed vltage is develped at the utput f the step-dwn cnverter, it is less prne t switching transient spikes This methd will be described in mre details in the Applicatins nfrmatin sectin Errr Amplifiers n clsed lp peratin, the errr amplifier utput ranges frm t 35 The upper utput perating range f either errr amplifier is reserved fr psitive currentsense vltage (CS - CS-) and crrespnds t psitive (surcing) utput current f the amplifier swings t its lwer perating range, the amplifier will still mdulate the high-side gate drive duty-rati Hwever the peak current-sense vltage (hence the peak inductr current) will be limited t a negative value The errr amplifier utput is abut when the peak sense-vltage is zer The built-in ffset in the current sense amplifier tgether with synchrnus cntinuus-cnductin mde f peratin allws the SC446 t regulate the utput irrespective f the directin f the lad current The nn-inverting input f the first feedback amplifier is tied t the internal 05 vltage reference Bth the nninverting and the inverting inputs f the secnd errr amplifier are brught ut as device pins s that the utput f the secnd cnverter can be made t track the utput f the first channel Fr example in DD applicatins, Channel can be used t generate DDQ (5) frm the input (5 r ) and channel is used t prduce a tracking TT (5) with DDQ being its input Current-Limit The maximum current sense vltage f 75m is the cycle-by-cycle peak current limit when the lad is drawing current frm the cnverter There is n cycle-by-cycle current limiting when the inductr current flws in the negative directin Hwever nce the valley f the current sense vltage exceeds 0m, the crrespnding channel will underg shutdwn and restart (hiccup) Sft-Start and Overlad Prtectin The undervltage lckut circuit discharges the SS/EN capacitrs After CC rises abve 45, the SS/EN capacitrs are slwly charged by internal µa current surce With internal PNP transistrs, the SS/EN vltages clamp the errr amplifier utputs When the errr amplifier utput rises t, the high-side MOSFET starts t switch As the SS/EN capacitr cntinues t be charged, the COMP vltage fllws The cnverter gradually delivers increasing pwer t the utput The inductr current fllws the COMP vltage envelpe until the utput ges int regulatin The SS/EN clamp n COMP is then released After the SS/EN capacitr is charged abve 3 (high enugh fr the errr amplifier t prvide full lad current), the verlad detectin circuit is activated f the utput vltage falls belw 70% f its set value r the valley current-sense vltage exceeds 0m, an verlad latch will be set and bth the tp and the bttm MOSFETs will be turned ff The SS/EN capacitr is slwly discharged with an internal 4µA current sink The verlad latch is reset when the SS/EN capacitr is discharged belw 05 The SS/EN capacitr is then recharged with the µa current surce and the cnverter underges sft-start f verlad persists, the SC446 will underg repetitive shutdwn and restart (Figure 3) f the utput is shrt-circuited, the inductr current will nt increase indefinitely between the time the inductr current reaching its current limit and the instant the cnverter shuts dwn This is due t cycle skipping reduces the actual perating frequency The SS/EN pin can als be used as the enable input fr that channel Bth the high-side and the lw-side MOSFETs will be turned ff if the SS/EN pin is pulled belw Semtech Crp 0 wwwsemtechcm

11 SC446 Applicatin nfrmatin SC446 cnsists f tw current-mde synchrnus buck cntrllers with many integrated functins By prper applicatin circuitry cnfiguratin, SC446 can be used t generate ) tw independent utputs frm a cmmn input r tw different inputs r ) dual phase utput with current sharing, 3) current surcing/sinking frm cmmn r separate inputs as in DD ( and ) memry applicatin The applicatin infrmatin related t the cnverter design using SC446 is described in the fllwing Step-dwn Cnverter Starting frm the fllwing step-dwn cnverter specificatins, nput vltage range: [, ] in in,min in, max nput vltage ripple (peak-t-peak): in Output vltage: Output vltage accuracy: ε Output vltage ripple (peak-t-peak): Nminal utput (lad) current: Maximum utput current limit:,max Output (lad) current transient slew rate: d (A/s) Circuit efficiency: η Selectin criteria and design prcedures fr the fllwing are described ) utput inductr (L) type and value, ) utput capacitr (C ) type and value, 3) input capacitr (C in ) type and value, 4) pwer MOSFET s, 5) current sensing and limiting circuit, 6) vltage sensing circuit, 7) lp cmpensatin netwrk Operating Frequency (f s ) The switching frequency in the SC446 is userprgrammable The advantages f using cnstant frequency peratin are simple passive cmpnent selectin and ease f feedback cmpensatin Befre setting the perating frequency, the fllwing trade-ffs shuld be cnsidered ) Passive cmpnent size ) Circuitry efficiency 3) EM cnditin 4) Minimum switch n time and 5) Maximum duty rati Fr a given utput pwer, the sizes f the passive cmpnents are inversely prprtinal t the switching frequency, whereas MOSFET s/dides switching lsses are prprtinal t the perating frequency Other issues such as heat dissipatin, packaging and the cst issues are als t be cnsidered The frequency bands fr signal transmissin shuld be avided because f EM interference Minimum Switch On Time Cnsideratin n the SC446 the falling edge f the clck turns n the tp MOSFET The inductr current and the sensed vltage ramp up After the sensed vltage crsses a threshld determined by the errr amplifier utput, the tp MOSFET is turned ff The prpagatin delay time frm the turnn f the cntrlling FET t its turn-ff is the minimum switch n time The SC446 has a minimum n time f abut 50ns at rm temperature This is the shrtest n interval f the cntrlling FET The cntrller either des nt turn n the tp MOSFET at all r turns it n fr at least 50ns Fr a synchrnus step-dwn cnverter, the perating duty cycle is O / N S the required n time fr the tp MOSFET is O /( N fs) f the frequency is set such that the required pulse width is less than 50ns, then the cnverter will start skipping cycles Due t minimum n time limitatin, simultaneusly perating at very high switching frequency and very shrt duty cycle is nt practical f the vltage cnversin rati O / N and hence the required duty cycle is higher, the switching frequency can be increased t reduce the sizes f passive cmpnents There will nt be enugh mdulatin headrm if the n time is simply made equal t the minimum n time f the SC446 Fr ease f cntrl, we recmmend the required pulse width t be at least 5 times the minimum n time 004 Semtech Crp wwwsemtechcm

12 SC446 Applicatin nfrmatin (Cnt) Setting the Switching Frequency The switching frequency is set with an external resistr cnnected frm Pin 3 t the grund The set frequency is inversely prprtinal t the resistr value (Figure 5) fs (khz) sc (k Ohm) Figure 5 Free running frequency vs OSC nductr (L) and ipple Current Bth step-dwn cntrllers in the SC446 perate in synchrnus cntinuus-cnductin mde (CCM) regardless f the utput lad The utput inductr selectin/design is based n the utput DC and transient requirements Bth utput current and vltage ripples are reduced with larger inductrs but it takes lnger t change the inductr current during lad transients Cnversely smaller inductrs results in lwer DC cpper lsses but the AC cre lsses (flux swing) and the winding AC resistance lsses are higher A cmprmise is t chse the inductance such that peak-t-peak inductr ripple-current is 0% t 30% f the rated utput lad current Assuming that the inductr current ripple (peak-t-peak) value is δ*, the inductance value will then be ( D) L δ f s The peak current in the inductr becmes (δ/)* and the MS current is The fllwings are t be cnsidered when chsing inductrs a) nductr cre material: Fr high efficiency applicatins abve 350KHz, ferrite, Kl-Mu and plypermally materials shuld be used Lw-cst pwdered irn cres can be used fr cst sensitive-applicatins belw 350KHz but with attendant higher cre lsses b) Select inductance value: Smetimes the calculated inductance value is nt available ff-the-shelf The designer can chse the adjacent (larger) standard inductance value The inductance varies with temperature and DC current t is a gd engineering practice t re-evaluate the resultant current ripple at the rated DC utput current c) Current rating: The saturatin current f the inductr shuld be at least 5 times f the peak inductr current under all cnditins Output Capacitr (C ) and ut ipple The utput capacitr prvides utput current filtering in steady state and serves as a reservir during lad transient The utput capacitr can be mdeled as an ideal capacitr in series with its parasitic ES ( esr ) and ESL (L esl ) (Figure 6) C Lesl esr Figure 6 An equivalent circuit f C f the current thrugh the branch is i b (t), the vltage acrss the terminals will then be t dib(t) v (t) ib(t)dt Lesl C dt 0 i (t) esr b This basic equatin illustrates the effect f ES, ESL and C n the utput vltage L,rms δ The first term is the DC vltage acrss C at time t0 The secnd term is the vltage variatin caused by the charge balance between the lad and the cnverter utput The 004 Semtech Crp wwwsemtechcm

13 SC446 Applicatin nfrmatin (Cnt) third term is vltage ripple due t ESL and the furth term is the vltage ripple due t ES The ttal utput vltage ripple is then a vectr sum f the last three terms Since the inductr current is a triangular wavefrm with peak-t-peak value δ*, the ripple-vltage caused by inductr current ripples is v C δ 8C f the ripple-vltage due t ESL is v ESL L and the ES ripple-vltage is v ES s f esl s esr, δ, D δ Aluminum capacitrs (eg electrlytic, slid OS-CON, POSCAP, tantalum) have high capacitances and lw ESL s The ES has the dminant effect n the utput ripple vltage t is therefre very imprtant t minimize the ES When determining the ES value, bth the steady state ripple-vltage and the dynamic lad transient need t be cnsidered T keep the steady state utput ripple-vltage <, the ES shuld satisfy esr < δ T limit the dynamic utput vltage versht/undersht within α (say 3%) f the steady state utput vltage) frm n lad t full lad, the ES value shuld satisfy esr α < Then, the required ES value f the utput capacitrs shuld be esr min{ esr, esr } The vltage rating f aluminum capacitrs shuld be at least 5 The MS current ripple rating shuld als be greater than δ 3 Usually it is necessary t have several capacitrs f the same type in parallel t satisfy the ES requirement The vltage ripple cause by the capacitr charge/discharge shuld be an rder f magnitude smaller than the vltage ripple caused by the ES T guarantee this, the capacitance shuld satisfy C 0 > πf n many applicatins, several lw ES ceramic capacitrs are added in parallel with the aluminum capacitrs in rder t further reduce ES and imprve high frequency decupling Because the values f capacitance and ES are usually different in ceramic and aluminum capacitrs, the fllwing remarks are made t clarify sme practical issues emark : High frequency ceramic capacitrs may nt carry mst f the ripple current t als depends n the capacitr value Only when the capacitr value is set prperly, the effect f ceramic capacitr lw ES starts t be significant Fr example, if a 0µF, 4mΩ ceramic capacitr is cnnected in parallel with x500µf, 90mΩ electrlytic capacitrs, the ripple current in the ceramic capacitr is nly abut 4% f the current in the electrlytic capacitrs at the ripple frequency f a 00µF, mω ceramic capacitr is used, the ripple current in the ceramic capacitr will be abut 4 times f that in the electrlytic capacitrs When tw 00µF, mω ceramic capacitrs are used, the current rati increases t 83 n this case mst f the ripple current flws in the ceramic decupling capacitr The ES f the ceramic capacitrs will then determine the utput ripple-vltage emark : The ttal equivalent capacitance f the filter bank is nt simply the sum f all the paralleled capacitrs The ttal equivalent ES is nt simply the parallel cmbinatin f all the individual ES s either nstead they shuld be calculated using the fllwing frmulae C eq eq (a b ) ( ω) : ( C ( ω) : a a b a ( ( a a ω C b C b a C s b ) ω C a esr C (C b b ) ω Ca Cb b ) ω Ca Cb a (C ( C a (C b ) C b ) bcb a a Cb ) C a where a and C a are the ES and capacitance f electrlytic capacitrs, and b and C b are the ES and capacitance f the ceramic capacitrs respectively (Figure 7) ) 004 Semtech Crp 3 wwwsemtechcm

14 SC446 Applicatin nfrmatin (Cnt) Ca Cb Ceq a b eq Figure 7 Equivalent C branch eq and Ceq are bth functins f frequency Fr rigrus design, the equivalent ES shuld be evaluated at the ripple frequency fr vltage ripple calculatin when bth ceramic and electrlytic capacitrs are used f a b and C a C b C, then eq and C eq will be frequencyindependent and nput Capacitr (C in ) eq / and C eq C The input supply t the cnverter usually cmes frm a pre-regulatr Since the input supply is nt ideal, input capacitrs are needed t filter the current pulses at the switching frequency A simple buck cnverter is shwn in Figure 8 Figure 9 Typical wavefrms at cnverter input t can be seen that the current in the input capacitr pulses with high di/dt Capacitrs with lw ESL shuld be used t is als imprtant t place the input capacitr clse t the MOSFET s n the PC bard t reduce trace inductances arund the pulse current lp The MS value f the capacitr current is apprximately δ D D Cin D[( )( ) ( D)] η η The pwer dissipated in the input capacitrs is then P Cin Cin esr Figure 8 A simple mdel fr the cnverter input n Figure 8 the DC input vltage surce has an internal impedance in and the input capacitr C in has an ES f esr MOSFET and input capacitr current wavefrms, ES vltage ripple and input vltage ripple are shwn in Figure 9 Fr reliable peratin, the maximum pwer dissipatin in the capacitrs shuld nt result in mre than 0 C f temperature rise Many manufacturers specify the maximum allwable ripple current (AMS) rating f the capacitr at a given ripple frequency and ambient temperature The input capacitance shuld be high enugh t handle the ripple current Fr higher pwer applicatins, multiple capacitrs are placed in parallel t increase the ripple current handling capability 004 Semtech Crp 4 wwwsemtechcm

15 SC446 Applicatin nfrmatin (Cnt) Smetimes meeting tight input vltage ripple specificatins may require the use f larger input capacitance At full lad, the peak-t-peak input vltage ripple due t the ES is δ ves esr ( ) The peak-t-peak input vltage ripple due t the capacitr is v C D C f in s Frm these tw expressins, C N can be fund t meet the input vltage ripple specificatin n a multi-phase cnverter, channel interleaving can be used t reduce ripple The tw step-dwn channels f the SC446 perate at 80 degrees frm each ther f bth step-dwn channels in the SC446 are cnnected in parallel, bth the input and the utput MS currents will be reduced ipple cancellatin effect f interleaving allws the use f smaller input capacitrs When cnverter utputs are cnnected in parallel and interleaved, smaller inductrs and capacitrs can be used fr each channel The ttal utput ripple-vltage remains unchanged Smaller inductrs speeds up utput lad transient When tw channels with a cmmn input are interleaved, the ttal DC input current is simply the sum f the individual DC input currents The cmbined input current wavefrm depends n duty rati and the utput current wavefrm Assuming that the utput current ripple is small, the fllwing frmula can be used t estimate the MS value f the ripple current in the input capacitr Let the duty rati and utput current f Channel and Channel be D, D and,, respectively f D <05 and D <05, then Cin D D f D >05 and (D -05) < D <05, then Cin 05 (D 05)( ) (D D 05) f D >05 and D < (D -05) < 05, then, Cin 05 D ( f D >05 and D > 05, then Cin (D D )( ) Chsing Pwer MOSFET s ) (D D ( D ) 05) ( D ) Main cnsideratins in selecting the MOSFET s are pwer dissipatin, cst and packaging Switching lsses and cnductin lsses f the MOSFET s are directly related t the ttal gate charge (C g ) and channel n-resistance ( ds(n) ) n rder t judge the perfrmance f MOSFET s, the prduct f the ttal gate charge and n-resistance is used as a figure f merit (FOM) Transistrs with the same FOM fllw the same curve in Figure 0 Gate Charge (nc) 50 Cg( 00, ds) Cg( 00, ds) Cg( 500, ds) ds On-resistance (mohm) FOM:00*0^{-} FOM:00*0^{-} FOM:500*0^{-} Figure 0 Figure f Merit curves The clser the curve is t the rigin, the lwer is the FOM This means lwer switching lss r lwer cnductin lss r bth t may be difficult t find MOSFET s with bth lw C g and lw ds(n Usually a trade-ff between ds(n and C g has t be made MOSFET selectin als depends n applicatins n many applicatins, either switching lss r cnductin lss dminates fr a particular MOSFET Fr synchrnus buck cnverters with high input t utput vltage ratis, the tp MOSFET is hard switched but cnducts with very lw duty cycle The bttm switch cnducts at high duty cycle but switches at near zer vltage Fr such applicatins, MOSFET s with lw C g are used fr the tp switch and Semtech Crp 5 wwwsemtechcm

16 SC446 Applicatin nfrmatin (Cnt) MOSFET s with lw ds(n) are used fr the bttm switch MOSFET pwer dissipatin cnsists f a) cnductin lss due t the channel resistance ds(n), b) switching lss due t the switch rise time t r and fall time t f, and c) the gate lss due t the gate resistance G Tp Switch: The MS value f the tp switch current is calculated as δ Q,rms D( ) The cnductin lsses is then P tc Q,rms ds(n) ds(n) varies with temperature and gate-surce vltage Curves shwing ds(n) variatins can be fund in manufacturers data sheet Frm the Si4860 datasheet, ds(n) is less than 8mΩ when gs is greater than 0 Hwever ds(n) increases by 50% as the junctin temperature increases frm 5 C t 0 C The switching lsses can be estimated using the simple frmula δ P (t t )( ) f ts r f in s where t r is the rise time and t f is the fall time f the switching prcess Different manufactures have different definitins and test cnditins fr t r and t f T clarify these, we sketch the typical MOSFET switching characteristics under clamped inductive mde in Figure Q gs is the additinal gate charge required fr the switch current t reach its full-scale value ds and Q gd is the charge needed t charge gate-t-drain (Miller) capacitance when ds is falling Switching lsses ccur during the time interval [t, t 3 ] Defining t r t 3 -t and t r can be apprximated as t r (Q gs cc Q gd where gt is the ttal resistance frm the driver supply rail t the gate f the MOSFET t includes the gate driver internal impedance gi, external resistance ge and the gate resistance g within the MOSFET ie gsp ) gt gt gi ge g gsp is the Miller plateau vltage shwn in Figure Similarly an apprximate expressin fr t f is t f (Q gs Q Only a prtin f the ttal lsses P g Q g cc f s is dissipated in the MOSFET package Here Q g is the ttal gate charge specified in the datasheet The pwer dissipated within the MOSFET package is P tg g gt gsp Q g gd f cc s The ttal pwer lss f the tp switch is then P t P tc P ts P tg ) gt Figure MOSFET switching characteristics n Figure, Q gs is the gate charge needed t bring the gate-t-surce vltage gs t the threshld vltage gs_th, f the input supply f the pwer cnverter varies ver a wide range, then it will be necessary t weigh the relative imprtance f cnductin and switching lsses This is because cnductin lss is inversely prprtinal t the input vltage Switching lss hwever increases with the input vltage The ttal pwer lss f MOSFET shuld be calculated and cmpared fr high-line and lw-line cases The wrst case is then used fr thermal design Bttm Switch: The MS current in bttm switch can be shwn t be δ Q,rms ( D)( ) 004 Semtech Crp 6 wwwsemtechcm

17 SC446 Applicatin nfrmatin (Cnt) The cnductin lss is then P bc Q,rms ds(n) where ds(n) is the channel resistance f bttm MOSFET f the input vltage t utput vltage rati is high (eg in, 5), the duty rati D will be small Since the bttm switch cnducts with duty rati (-D), the crrespnding cnductin lsses can be quite high Due t nn-verlapping cnductin between the tp and the bttm MOSFET s, the internal bdy dide r the external Schttky dide acrss the drain and surce terminals always cnducts prir t the turn n f the bttm MOSFET The bttm MOSFET switches n with nly a dide vltage between its drain and surce terminals The switching lss P bs (t t )( r f δ ) f d s is negligible due t near zer-vltage switching The gate lss is estimated as P g bg Qgccfs gt The ttal bttm switch lss is then P b P bc P bs P bg Once the pwer lsses P lss fr the tp (P t ) and bttm (P b ) MOSFET s are knwn, thermal and package design at cmpnent and system level shuld be dne t verify that the maximum die junctin temperature (T j,max, usually 5 C) is nt exceeded under the wrst-case cnditin The equivalent thermal impedance frm junctin t ambient (θ ja ) shuld satisfy θ ja T j,max P T lss a,max θ ja depends n the die t substrate bnding, packaging material, the thermal cntact surface, thermal cmpund prperty, the available effective heat sink area and the air flw cnditin (free r frced cnvectin) Actual temperature measurement f the prttype shuld be carried ut t verify the thermal design Darlingtn biplar transistrs are used fr the utput stage The key advantage f the Darlingtn cnfiguratin is that the ttal current gain is greatly imprved which leads t larger driving current gs This in turn will help reduce the MOSFETs switching lsses n rder t estimate the lsses assciated with the gate driver, we first measured the gate driver wavefrm (typical wavefrms f ce and gs ) as shwn in Figure Figure Measured gate driver utput wavefrms with Ω current limit resistr t is clear that the saturatin vltage is nt a cnstant t changes with the driving current in a nnlinear fashin A simple frmula t calculate the lsses with a reasnable accuracy is nt available But, we use a curve fitting technique t estimate the pwer lsses in gate driver First, the saturatin vltage v ce (t) is apprximated as v ce (t) cc t ( ) T Where, cc is the gate driver cllectr vltage, T is a time cnstant related t the fall time f v ce Fr the example in Fig, cc, T 05T f with T f being measured as ~50 ns With these parameters, the apprximated v ce (t) is pltted as in Figure 3 a) ntegrated Pwer MOSFET Drivers n SC446 there are fur internally integrated gate drivers t drive all the MOSFETs in dual channels With the device biplar prcess, emitter-fllwer based 004 Semtech Crp 7 wwwsemtechcm

18 SC446 Applicatin nfrmatin (Cnt) vce () v ce () t t time (s) 0 7 Figure 3 a) Apprximated gate driver v ce (t) wavefrm Similarly, the gate drive current is apprximated as i gs (t) gsp ( t T ) e t ( ) T Where, gsp is a scaling parameter prprtinal t the gate drive peak current, T is a time cnstant prprtinal t the fall time f v ce Fr the example in Figure 3, gsp 35A, T 077T f with T f being measured as ~50 ns igs (A) 58 i gs () t t time (s) 0 7 Figure 3 b) Apprximated gate drive current i gs (t) wavefrm With these parameters, the apprximated i gs (t) is pltted as in Figure 3 b) Based n the apprximatin frmulae f v ce (t) and i gs (t), ne can calculate the pwer lsses fr each gate driver pair as P gd T s T s 0 v ce (t)i gs (t)dt Fr SC446, there are 4 gate drivers, the ttal gate driver lsses is then 4P gd Fr the example in Figure, the pwer lsses fr each gate driver is estimated as mw when the perating frequency is abut 300kHz The ttal lsses fr the 4 gate drivers is then abut 488 mw emark 3: t is beneficial t select lw gate charge MOSFET s fr lwer switching lsses in the MOSFET package and lwer pwer dissipatin in the gate-driving C Once the MOSFET is chsen with a specified input gate charge, ne can adjust the gate driving resistr t balance the driver C lsses and the pwer MOSFET switching lsses T the first rder f apprximatin, smaller gate resistance leads t higher gate driving current and faster MOSFET switching But, the driver incurs mre pwer lsses On the ther hand, larger gate drive resistance limits the gate drive current, which leads t lw ce and less pwer lsses But, the MOSFET suffers mre switching lsses Using lw gate charge MOSFET s reduces switching lss T prevent sht-thrugh between the tp and the bttm MOSFET s during cmmutatin, ne MOSFET shuld be cmpletely turned ff befre the ther is turned n n the SC446 the tp and the bttm gate drive pulses are made nn-verlapping When nt driving any lad, the nnverlapping cmmutatin intervals frm the tp t the bttm and frm the bttm t the tp gate drives are set at 90ns f MOSFET s are driven frm the SC446, the nn-verlapping cmmutatin times will decrease due t finite gate-surce vltage rise and fall times The gatesurce vltage wavefrms f the MOSFET s shuld nt verlap abve their respective threshlds when driven frm the SC446 Use f lw gate charge MOSFET s reduces transitin times and the tendency f sht-thrugh The cmbined rise and fall times during bth cmmutatins shuld be less than the preset nn-verlapping intervals Current Sensing (Cmbi-Sense) nductr current sensing is required fr the current-mde cntrl Althugh the inductr current can be sensed with a precisin resistr in series with the inductr, a nvel lssless Cmbi-sense technique is used in the SC446 This SEMTECH prprietary technique has the advantages f 004 Semtech Crp 8 wwwsemtechcm

19 C i n SC446 Applicatin nfrmatin (Cnt) ) lssless current sensing, ) higher signal-t-nise rati, and 3) preventing thermal run-away in ds The basic arrangement f the Cmbi-sense is shwn in Figure 4 Where, L is the equivalent series resistance f the utput inductr The added s and C s frm a C branch fr inductr current sensing This branch is driven frm a small ttem ple driver (Q3 and Q4) integrated within SC446 The base driving signals be3 and be4 Cin il(t) L L PN s Cs PN Cut lad vc(t) Figure 5 a) Equivalent sub-circuit in Q Cin gs gs PN Q il(t) L s L Cs vc (t) Cut lad in PN il(t) L L be3 Q3 ds PN s Cs vc(t) Cut lad P N be4 Q4 Figure 5 b) Equivalent sub-circuit Figure 4 The basic structure f Cmbi-Sense are designed t fllw the gate drive signals gs and gs, respectively, with minimal delay drive deally, the leading and falling edges f the irtual Phase Nde (PN) fllw that f the Phase Nde (PN) when Q~Q4 switch accrdingly Specifically, when Q/Q3 are ON and Q/Q4 are OFF, the equivalent circuit f Figure 4 reduces t Figure 5 a) Where, ds is the n-resistance f the tp MOSFET The tw branches, cnsisting f {(dsl), L} and { s, C S }, are in parallel The DC vltage drp (dsl) equals Cs n this way, the utput current is sensed frm Cs when (dsl) is knwn When Q/Q3 are OFF and Q/Q4 are ON, the equivalent circuit f Figure 4 becmes the sub-circuit as shwn in Figure 5 b) Where, ds is the channel resistance f the bttm MOSFET n this case, the branch { s,c s } is in parallel with {(dsl), L} and Cs (dsl) n average, r equivalently Cs [D(dsL)(-D)(dsL)], Cs [D ds(-d)dsl] eq t is nted that the DC value f Cs is independent f the value f L, s and C s This means that, if nly the average lad current infrmatin is needed (such as in average current mde cntrl), this current sensing methd is effective withut time cnstant matching requirement n the current mde cntrl as implemented in SC446, the vltage ripple n C s is critical fr PWM peratin n fact, the AC vltage ripple peak-t-peak value f Cs (dented as Cs ) directly effects the signal-t-nise rati f the PWM peratin n general, smaller Cs leads t lwer signal-t-nise rati and mre nise sensitive peratin Larger Cs leads t mre circuit (pwer stage) 004 Semtech Crp 9 wwwsemtechcm

20 SC446 Applicatin nfrmatin (Cnt) parameter sensitive peratin A gd engineering cmprmise is t make Cs ~ eq δ in Q The prerequisite fr such relatin is the s called time cnstant matching cnditin L eq C s s Cin gs gs PN Q il(t) L s L s Cs vc(t) Cut lad When dsds, the abve relatins becme equatins Fr an example f applicatin circuit, L3µH, L56mΩ and dsds8mω, the time cnstant s C s shuld be set as 36µs f ne selects C s 33 nf, then s 4 kω be3 Q3 PN be4 Q4 - SEN s3 s Scaling the Current Limit Over-current is handled differently in the SC446 depending n the directin f the inductr current f the differential sense vltage between CS and CS- exceeds 75m, the tp MOSFET will be turned ff and the bttm MOSFET will be turned n t limit the inductr current This 75m is the cycle-by-cycle peak current limit when the lad is drawing current frm the cnverter There is n cycle-by-cycle current limit when the inductr current flws in the reverse directin f the vltage between CS and CS- falls belw -3m, the cntrller will underg verlad shutdwn and time-ut with bth the tp and the bttm MOSFETs shut ff (See the sectin Overlad Prtectin and Hiccup) n the circuit f Figure 4, the equivalent inductr current limits are set accrding t LMcp 75m, when the lad is surcing current frm the cnverter and LMcn eq 0m, when the lad is frcing current back t the input pwer surce f eq 956mW, then LM 78/-8A The circuit in Figure 6 allws the user t scale the equivalent current limit with the same eq eq Figure 6 Scaling the equivalent current limit a) When the required current limit value LM is greater than LMcp, ne just needs t remve s3, and slve fr s, and S s is then calculated frm s Cs L eq s LM eq 75m, s s s f the current limit is t be set t LM 5A with the existing pwer circuit parameter and C s, it is calculated that s 4 kω, s 787 kω and s 866 kω b) When the required current limit LM is less than LMcp, ne just needs t remve s and slve fr s and S3 C s s s L s eq, s s LM eq O 75m, s3, 004 Semtech Crp 0 wwwsemtechcm

21 SC446 Applicatin nfrmatin (Cnt) s is then btained frm s s3 s f the current limit is t be set t LM 5A with the existing pwer circuit parameter and C s, it is calculated that s 4 kω, s3 90 kω and s 4 kω Similar steps and equatins apply t the current limit setting and scaling fr current sinking mde emark 4: When the current limit LM is lwer than LMcp, the designer has the freedm f selecting higher ds(on) MOSFETs t reduce cst As a result, eg is increased and LMcp is reduced Althugh the use f lw-cst MOSFET s is always preferred, the current-limit setting technique described abve allws quick adjustment n a well-tested prttype withut the need t replace the pwer MOSFETs Overlad Prtectin and Hiccup During start-up, the capacitr frm the SS/EN pin t grund functins as a sft-start capacitr After the cnverter starts and enters regulatin, the same capacitr perates as an verlad shutff timing capacitr As the lad current increases, the cycle-bycycle current-limit cmparatr will first limit the inductr current Further increase in lading will cause the utput vltage (hence the feedback vltage) t fall f the feedback vltage falls t less than (75% fr Ch, 7% fr Ch) f the reference vltage, the cntrller will shut ff bth the tp and the bttm MOSFET s Meanwhile an internal 4µA current surce discharges the sft-start capacitr C 3 (C 33 ) cnnected t the SS/EN pin When the capacitr is discharged t 05, a µa current surce recharges the SS/EN capacitr and cnverter restarts f verlad persists, the cntrller will shut dwn the cnverter when the sft start capacitr vltage exceeds 3 The cnverter will repeatedly start and shut ff until it is n lnger verladed This hiccup mde f verlad prtectin is a frm f fldback current limiting The fllwing calculatins estimate the average inductr current when the cnverter utput is shrted t the grund a) The time taken t discharge the capacitr frm 3 t 05 s3 s tssf C3 (3 05) 4µ A f C 3 0µF t ssf is then calculated as 93ms b) The sft start time frm 05 t 3 tssr C3 (3 05) µ A When C 3 0µF t ssr is then calculated as 35ms Nte that during sft start, the cnverter nly starts switching when the vltage at SS/EN exceeds c) The effective start-up time is tss C3 (3 ) µ A The average inductr current is then Leff LMcp t ssf tss t Leff 030 LMcp and is independent f the sft start capacitr value The cnverter will nt verheat in hiccup Setting the Output ltage The nn-inverting input f the channel-ne errr amplifier is internally tied the 05 vltage reference utput (Pin 8) The nn-inverting input f the channel-tw errr amplifier is brught ut as a device pin (Pin 0) t which the user can cnnect Pin 8 r an external vltage reference A simple vltage divider ( at tp and at bttm) sets the cnverter utput vltage The vltage feedback gain h05/ is related t the divider resistrs value as hh Once either r is chsen, the ther can be calculated fr the desired utput vltage Since the number f standard resistance values is limited, the calculated resistance may nt be available as a standard value resistr As a result, there will be a set errr in the cnverter utput vltage This nn-randm errr is caused by the feedback vltage divider rati t cannt be crrected by the feedback lp ssr 004 Semtech Crp wwwsemtechcm

22 SC446 Applicatin nfrmatin (Cnt) The fllwing table lists a few standard resistr cmbinatins fr realizing sme cmmnly used utput vltages peratin abve 50% duty-cycle, a cmpensatin ramp is added t the sensed-current n the SC446 the cmpensatin ramp is made duty-rati dependent The cmpensatin ramp is apprximately () ( -h)/h (Ohm) K K 6K 40K 56K (Ohm) K K K K K K K Only the vltages in bldface can be precisely set with standard % resistrs Frm this table, ne may als bserve that when the value h 05 h 05 and its multiples fall int the standard resistr value chart (%, 5% r s), it is pssible t use standard value resistrs t exactly set up the required utput vltage value The input bias current f the errr amplifier als causes an errr in setting the utput vltage The maximum inverting input bias currents f errr amplifiers and is -50nA Since the nn-inverting input is biased t 05, the percentage errr in the secnd utput vltage will be 00% (05µA) /[05 ( ) ] T keep this errr belw 0%, < 4kΩ 76D ramp De * 30µ A The slpe f the cmpensatin ramp is then 76D Se ( 76D)e fs * 30µ A The slpe f the internal cmpensatin ramp is well abve the minimal slpe requirement fr current lp stability and is sufficient fr all the applicatins With the inner current lp stable, the utput vltage is then regulated with the uter vltage feedback lp A simplified equivalent circuit mdel f the synchrnus Buck cnverter with current mde cntrl is shwn in Figure 7 k Lp Cmpensatin SC446 uses current-mde cntrl fr bth step-dwn channels Current-mde cntrl is a dual-lp cntrl system in which the inductr peak current is lsely cntrlled by the inner current-lp The higher gain uter lp regulates the utput vltage Since the current lp makes the inductr appear as a current surce, the cmplex high-q ples f the utput LC netwrks is split int a dminant ple determined by the utput capacitr and the lad resistance and a high frequency ple This ple-splitting prperty f current-mde cntrl greatly simplifies lp cmpensatin The inner current-lp is unstable (sub-harmnic scillatin) unless the inductr current up-slpe is steeper than the inductr current dwn-slpe Fr stable Figure 7 A simple mdel f synchrnus buck cnverter with current mde cntrl The vltage transcnductance errr amplifier (in the SC446) has a g m f 60 A/ The target f the cmpensatin design is t select the cmpensatin netwrk cnsisting f C, C 3 and, alng with the feedback resistrs, and the current sensing gain, such that the cnverter utput vltage is regulated with satisfactry dynamic perfrmance 004 Semtech Crp wwwsemtechcm

23 SC446 Applicatin nfrmatin (Cnt) With the utput vltage knwn, the feedback gain h and the feedback resistr values are determined using the equatins given in the Output ltage Setting sectin with 05 h Fr the rated utput current, the current sensing gain k is first estimated as k Frm Figure 7, the transfer functin frm the vltage errr amplifier utput v c t the cnverter utput v is (s) : G (s) c vc (s) k where, the single dminant ple is s p ( esr s sz s s and the zer due t the utput capacitr ES is s z C The dminant ple mves as utput lad varies The cntrller transfer functin (frm the cnverter utput v t the vltage errr amplifier utput v c ) is where and esr )C, p s gmh sz C(s), s(c C ) s 3 s s p s z C, CC3 C C 3 p The lp transfer functin is then T(s)G vc (s)c(s) T simplify design, we assume that C 3 <<C, esr <<, selects S p S z and specifies the lp crssver frequency f c t is nted that the crssver frequency determines the cnverter dynamic bandwidth With these assumptins, the cntrller parameters are determined as fllwing and C C 3 gmhk πf c C C esrc with a cnstant K Fr example, if 5, 5A, f s 300kHz, C 68mF, esr 467mΩ, ne can calculate that and,, K, 67mΩ, 05 h 0, k 74 f the cnverter crssver frequency is set arund /0 f the switching frequency, f c 30kHz, the cntrller parameters then can be calculated use C 033µF gmhk C 038µ F, πf c C 8485kΩ, C 004 Semtech Crp 3 wwwsemtechcm

24 SC446 Applicatin nfrmatin (Cnt) use 770kΩ With K, it is further calculated that esrc C3 K 0pF, use C 3 0pF The Bde plt f the lp transfer functin (magnitude and phase) is shwn in Figure 8 0 lg G vc ()Cf f ( ) f ( ) 80 argg vc ()Cf f π f 30 5 Figure 8 The lp transfer functin Bde plt f the example t is clear that the resulted crssver frequency is abut 7 khz with phase margin 9 n sme initial prttypes, if the circuit nise makes the cntrl lp jittering, it is suggested t use a bigger C 3 value than the calculated ne here Effectively, the cnverter bandwidth is reduced in rder t reject sme f high frequency nises n the final wrking circuit, the lp transfer functin shuld be measured using netwrk analyzer and cmpared with the design t ensure circuit stability under different line and lad cnditins The lad transient respnse behavir is further tested and measured t meet the specificatin PC Bard Layut ssues Circuit bard layut is very imprtant fr the prper peratin f high frequency switching pwer cnverters A pwer grund plane is required t reduce grund bunces The fllwings are suggested fr prper layut Pwer Stage ) Separate the pwer grund frm the signal grund n SC446, the pwer grund PGND shuld be tied t the surce terminal f lwer MOSFETs The signal grund AGND shuld be tied t the negative terminal f the utput capacitr ) Minimize the size f high pulse current lp Keep the tp MOSFET, bttm MOSFET and the input capacitrs within a small area with shrt and wide traces n additin t the aluminum energy strage capacitrs, add multilayer ceramic (MLC) capacitrs frm the input t the pwer grund t imprve high frequency bypass 3) educe high frequency vltage ringing Widen and shrten the drain and surce traces f the MOSFET s t reduce stray inductances Add a small C snubber if necessary t reduce the high frequency ringing at the phase nde Smetimes slwing dwn the gate drive signal als helps in reducing the high frequency ringing at the phase nde 4) Shrten the gate driver path ntegrity f the gate drive (vltage level, leading and falling edges) is imprtant fr circuit peratin and efficiency Shrt and wide gate drive traces reduce trace inductances Bnd wire inductance is abut ~3nH f the length f the PCB trace frm the gate driver t the MOSFET gate is inch, the trace inductance will be abut 5nH f the gate drive current is A with 0ns rise and falling times, the vltage drps acrss the bnd wire and the PCB trace will be 06 and 5 respectively This may slw dwn the switching 004 Semtech Crp 4 wwwsemtechcm

25 SC446 Applicatin nfrmatin (Cnt) transient f the MOSFET s These inductances may als ring with the gate capacitance 5) Put the decupling capacitr fr the gate drive pwer supplies (BST and PCC) clse t the C and pwer grund Cntrl Sectin 6) The frequency-setting resistr sc shuld be placed clse t Pin 3 Trace length frm this resistr t the analg grund shuld be minimized 7) Slder the bias decupling capacitr right acrss the ACC and analg grund AGND 8) Place the Cmbi-sense cmpnents away frm the pwer circuit and clse t the crrespnding CS and CSpins Use X7 type ceramic capacitr fr the Cmbi-sense capacitr because f their temperature stability 9) Use an islated lcal grund plane fr the cntrller and tie it t the negative side f utput capacitr bank 004 Semtech Crp 5 wwwsemtechcm

26 6 004 Semtech Crp wwwsemtechcm SC446 Applicatin nfrmatin 76 C0 CS- 78 O C99 FLTE N CS SYNC C0 8 C06 C97 CS- C05 C9 U SC446 EFOUT PGND GDH BST N- PN SYNC CS PCC COMP SS/EN CS- SS/EN COMP N- EFN CS- CS PN N BST GDH GDL GDL EF sc AGND ACC 80 D 77 FLTE C96 C03 73 C00 CFLTE C93 C95 85 C04 83 C09 8 CFLTE N EF Dual ndependant Outputs C94 84 Q D 74 N 75 L C08 Q3 C07 79 Q C98 Q4 CS O L Figure CS EF 37 CS- CS C50 Single Output, Current Share Mde Q 33 C5 C53 Q CS N ACC U SC446 EFOUT PGND GDH BST N- PN SYNC CS PCC COMP SS/EN CS- SS/EN COMP N- EFN CS- CS PN N BST GDH GDL GDL EF sc AGND ACC C49 D6 CFLTE 4 O D5 40 C45 Q9 C4 36 C44 C39 4 FLTE CFLTE C40 Q0 C48 C43 O 39 C38 SYNC FLTE L6 C55 C47 C54 L5 C46 N C5 C4 N Figure 0

27 SC446 Applicatin nfrmatin (Cnt) N C56 D7 D8 PCC TT L7 Q3 43 C57 BST GDH BST GDH C58 44 Q4 L8 DDQ C63 C59 Q5 CFLTE Q6 CFLTE C6 C64 49 C60 45 FLTE GDL GDL PGND FLTE 46 C6 50 CS PN PN CS CS CS 5 CS- CS- CS- CS- 5 N- N- 53 C65 C67 DDQ N SYNC COMP EFN N SYNC COMP EF AGND sc C68 57 C69 C66 55 SS/EN ACC N C70 C7 SS/EN EFOUT U SC446 C7 C73 Figure DD Memry Applicatins (Cmmn nput ltage) DDQ N C74 D9 D0 PCC TT L9 Q7 58 C75 BST GDH BST GDH C76 59 Q8 L0 DDQ C8 C77 Q9 CFLTE 6 63 Q0 CFLTE C80 C8 64 C78 60 FLTE GDL GDL PGND FLTE 6 C79 65 CS PN PN CS CS CS 66 CS- CS- CS- CS- 67 N- N- 68 C83 C85 DDQ 69 7 DDQ SYNC COMP EFN N SYNC COMP EF AGND sc C86 7 C87 C84 70 SS/EN ACC N C88 C89 SS/EN EFOUT U SC446 C90 C9 DD Memry Applicatins (Separate nput ltage) Figure 004 Semtech Crp 7 wwwsemtechcm

28 SC446 Typical Perfrmance Characteristics Channel : 5A Efficiency vs Lad Current (%) Lad egulatin in5 in in in5 Efficiency (%) Lad Current (A) ut ariatin (%) Lad Current (A) Sft-Start Line 5A ut ariatin (%) nput ltage () Lad Transient Output in 3 Output ltage () Lad Current (A) 004 Semtech Crp 8 wwwsemtechcm

29 SC446 Typical Perfrmance Characteristics Efficiency vs Lad Current Channel : 5A Lad egulatin in5 in in5 in Efficiency (%) Lad Current (A) Sft-Start ut ariatin (%) Lad Current (A) Fig 8 Line egulatin at 5A ut ariatin (%) nput ltage () Lad Transient Output in Output ltage () Lad Current (A) 004 Semtech Crp 9 wwwsemtechcm

30 SC446 Typical Applicatin Circuit O GND C C4 Ntes: N NGND N N C4 C3 C7 C5 C C6 C38 D D C C8 C5 C4 C3 C 9 PCC 3 C7 8 C8 Q 6 9 Q C37 Q4 4 BST BST 3 Q3 C L GDH GDH L D6 D5 Q7 Q8 D9 C3 4 C 6 D0 GDL GDL 8 PGND 3 7 CS PN PN CS CS Q6 Q5 D7 D8 C9 0 5 C0 7 8 CS 4 CS- N- N- CS- 3 CS- CS- C8 C7 COMP COMP 6 9 C3 C9 0 6 C35 C34 EF EFN 0 C AGND N sc SYNC 6 8 ACC SS/EN 5 EFOUT SS/EN 30 C33 C3 U SC Dual ndependant Outputs: 50, pen, 30, 4, 5, 6 pen, 70 Single Output with Current Sharing Mde: 5 pen, 0, 30, 4, 5, 6 pen, 70 3 DD Memry Applicatins (Cmmn nput ltage): 50, pen, 30, 4 pen, 56K, 7 pen 4 DD Memry Applicatins (Separate nput ltage): 50,, 3 pen, 40, 56K, 7 pen C 5 C0 C5 9 7 C9 C6 O GND Figure Semtech Crp 30 wwwsemtechcm

31 SC446 Evaluatin Bard - Bill f Materials ef Qty eference Part Number/alu e Manufacturer 4 C,C4,C5,C7 470uF, 6, OS-CON 0mhm, Alum r ishay P/N: 94SA477X006GBP r Sany P/N: 6SA470M 3 C,C3,C6 0uF, 6, X5, Ceramic 06 Taiy Yuden P/N: EMK36BJ06MM 3 4 C,C4,C5,C6 0uF, 4, X5, Ceramic 06 Taiy Yuden P/N: AMK35BJ06MM 4 8 C8,C9,C0,C,C, C3,C4,C5, 560uF, 4, 4mhm, Alum r OS-CON ishay P/N: 94SP567X0004EBP r Sany P/N: 4SP560M 5 C7,C8 033uF, 50, X5 (r X7) 06 ishay P/N: J06Y334KXAAT r Panasnic 6 4 C3,C9,C36,C37 nf, Ceramic, C0,C 33nF, Ceramic, C7 68pF, Ceramic, C8 33pF, Ceramic, C9,C34,C35 0uF, Ceramic, 0805 C3,C33 00nF, Ceramic, 0805 C 38 0uF, 6, Alum 3 C30,C3 047nF, Ceramic, D,D 40, A, Schttky General Semi P/N: N589 MELF r Mtrla P/N: MBS40T3 5 4 D5,D6,D8,D9 40, A, Schttky, SOD-3 Dides nc P/N: N589HW r ishay General Semi P/N: SL04 6 D7,D0 7 L,L 8 8 Q,Q,Q3,Q4,Q5,Q6, - Q7,Q8 9 CS, CS 0 CS-C, CS- 40, 3A, Schttky ishay, General Semi P/N: 30BQ040 r CMSH340 r SS34 3uH, 85A, 56 mhm Panasnic P/N: ETQPAF3 E 30, 8A, 5 mhm, 44nC, SO-8 ishay P/N: Si4860DY 0k 0k 4 3,4,7, 8, 5%, ,6 0k, k, %, ,3,8, 9 5, Semtech Crp 3 wwwsemtechcm

32 SC446 Evaluatin Bard - Bill f Materials ef Qty eference Part Number/alu e Manufacturer 5 9 k, %, , %, k, %, ,9 770k, k, % ,3, 7 0 hm 3 U S C446 Semtech Crp 004 Semtech Crp 3 wwwsemtechcm

33 SC446 Typical Characteristics Typical wavefrms in the evaluatin bard circuit #A Steady state Channel : 5A Over current prtectin Output shrt applied Lad transient respnse Lading: 0A t 5A Output shrt remved Un-lading: 5A t 0A 004 Semtech Crp 33 wwwsemtechcm

34 SC446 Typical Characteristics (Cnt) Typical wavefrms in the evaluatin bard circuit #A Steady state Channel : 5A Lad transient respnse Lading: 0A t 5A Un-lading: 5A t 0A 004 Semtech Crp 34 wwwsemtechcm

35 SC446 Typical Characteristics (Cnt) Over current prtectin Output shrt applied Output shrt remved 004 Semtech Crp 35 wwwsemtechcm