HIGHLY EFFICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR FOR DDR APPLICATIONS. Description. Vin Boot. Vcc SW. OCSet Vp. Comp PGnd

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1 SupIRBuck TM eatures Wide Input ltage Range.0 t 6 Wide Output ltage Range 0.6 t 0.9*in Cntinuus 8A Lad Capability Integrated Btstrap-dide High Bandwidth E/A fr excellent transient perfrmance Prgrammable Switching requency up t.5 MHz Prgrammable Over Current Prtectin PGd utput Hiccup Current Limit Prgrammable Sft-Start Enable Input with ltage Mnitring Capability Enhanced Pre-Bias Start-up p input fr DDR Tracking applicatins -40 C t 25 C perating junctin temperature Thermal Prtectin 5mm x 6mm Pwer QN Package, 0.9 mm height Lead-free, halgen-free and RHS cmpliant Applicatins Server Applicatins Strage Applicatins Embedded Telecm Systems PD HIGHLY EICIENT INTEGRATED SYNCHRONOUS BUCK REGULATOR OR DDR APPLICATIONS Descriptin The IR8W SupIRBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC regulatr. The MOSETS c-packaged with the n-chip PWM cntrller make IR8W a spaceefficient slutin, prviding accurate pwer delivery fr DDR memry applicatins. IR8W is cnfigured t generate terminatin vltage (TT) fr DDR memry applicatins. IR8W ffers prgrammability f start up time, switching frequency and current limit while perating in wide input and utput vltage range. The switching frequency is prgrammable frm 250kHz t.5mhz fr an ptimum slutin. It als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t give required system level security in the event f fault cnditins. Distributed Pint f Lad Pwer Architectures Netcm Applicatins.0 <in<6 4.5 <cc<5.5 Enable in Bt DDQ cc SW PGd PGd OCSet p Rt b SS/ SD Gnd Cmp PGnd ig.. Typical applicatin diagram

2 ABSOLUTE MAXIMUM RATINGS (ltages referenced t GND unless therwise specified) in. -0. t 25 cc t 8 (Nte2) Bt t SW t 25(DC), -4 t 25(AC, 00ns) Bt t SW t cc+0. (Nte) OCSet t 0, 0mA Input / utput Pins t cc+0. (Nte) PGND t GND t +0. Strage Temperature Range C T 50 C Junctin Temperature Range C T 50 C (Nte2) ESD Classificatin JEDEC Class C Misture sensitivity level... JEDEC Level 2@260 C (Nte5) Nte: Must nt exceed 8 Nte2: cc must nt exceed 7.5 fr Junctin Temperature between -0 C and -40 C Stresses beynd thse listed under Abslute Maximum Ratings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins are nt implied. PACKAGE INORMATION 5mm x 6mm POWER QN SW IN 2 0 PGnd θ θ JA J-PCB 5 C / W 2 C / W Bt Enable 4 5 Gnd 9 8 CC PGd ORDERING INORMATION p B COMP Gnd Rt SS OCSet PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR8WMTRPb M IR8WMTRPb

3 Blck Diagram ig. 2. Simplified blck diagram f the IR8W

4 Pin Descriptin Pin Name Descriptin p 2 b Cmp Track pin. Use External resistrs frm DDQ rail. The p vltage can be set t 0.9 fr DDR2 applicatin and 0.75 r 0.6 fr DDR applicatin. Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier. Output f errr amplifier. An external resistr and capacitr netwrk is typically cnnected frm this pin t b pin t prvide lp cmpensatin. 4 Gnd Signal grund fr internal reference and cntrl circuitry. 5 Rt 6 SS/SD 7 OCSet 8 PGd 9 CC 0 PGnd Set the switching frequency. Cnnect an external resistr frm this pin t Gnd t set the switching frequency. Sft start / shutdwn. This pin prvides user prgrammable sft-start functin. Cnnect an external capacitr frm this pin t Gnd t set the start up time f the utput vltage. The cnverter can be shutdwn by pulling this pin belw 0.. Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld. Pwer Gd status pin. Output is pen drain. Cnnect a pull up resistr frm this pin t cc. If unused, it can be left pen. This pin pwers the internal IC and drivers. A minimum f u high frequency capacitr must be cnnected frm this pin t the pwer grund (PGnd). Pwer Grund. This pin serves as a separated grund fr the MOSET drivers and shuld be cnnected t the system s pwer grund plane. SW Switch nde. This pin is cnnected t the utput inductr. 2 IN Input vltage cnnectin pin. Bt Supply vltage fr high side driver. Cnnect a 0.u capacitr frm this pin t SW. 4 Enable Enable pin t turn n and ff the device. 5 Gnd Signal grund fr internal reference and cntrl circuitry. 4

5 Recmmended Operating Cnditins Symbl Definitin Min Max Units in Input ltage.0 6 cc Supply ltage Bt t SW Supply ltage Output ltage *in I Output Current 0 8 A s Switching requency khz T j Junctin Temperature C Electrical Specificatins Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, p0.6, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Pwer Lss Parameter Symbl Test Cnditin Min TYP MAX Units Pwer Lss P lss cc5, in 2, 0.75, I 8A, s400khz, L0.6uH, Nte4.28 W MOSET R ds(n) Tp Switch R ds(n)_tp Bt - sw 5, I D0A, Tj25 C Bttm Switch R ds(n)_bt cc5, I D0A, Tj25 C mω Supply Current CC Supply Current (Standby) I CC(Standby) SS0, N Switching, Enable lw 500 μa cc Supply Current (Dyn) I CC(Dyn) SS, cc5, s500khz Enable high Under ltage Lckut 2 ma CC -Start-Threshld CC _ULO_Start cc Rising Trip Level CC -Stp-Threshld CC _ULO_Stp cc alling Trip Level Enable-Start-Threshld Enable_ULO_Start Supply ramping up Enable-Stp-Threshld Enable_ULO_Stp Supply ramping dwn Enable leakage current Ien Enable. 5 μa 5

6 Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, p0.6, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Oscillatr Parameter Symbl Test Cnditin Min TYP MAX Units Rt ltage requency S Rt59K Rt28.7K khz Rt9.K, Nte Ramp Amplitude ramp Nte4.8 p-p Ramp Offset Ramp (s) Nte4 0.6 Min Pulse Width Dmin(ctrl) Nte4 50 ixed Off Time Nte Max Duty Cycle Dmax s250khz 92 % Errr Amplifier Input Offset ltage s fb-p m p0.6 Input Bias Current Ib(E/A) - + μa Input Bias Current Ip(E/A) - + ns Sink Current Isink(E/A) Surce Current Isurce(E/A) 8 0 ma Slew Rate SR Nte /μs Gain-Bandwidth Prduct GBW P Nte MHz DC Gain Gain Nte db Maximum ltage max(e/a) cc Minimum ltage min(e/a) m Cmmn Mde ltage Nte4 0 Sft Start/SD Sft Start Current ISS Surce μa Sft Start Clamp ltage ss(clamp) Shutdwn Output Threshld Over Current Prtectin OCSET Current SD 0. I OCSET s250khz s500khz s500khz μa OC Cmp Offset ltage OSET Nte m SS ff time SS_Hiccup 4096 Cycles Btstrap Dide rward ltage I(Bt)0mA m Deadband Deadband time Nte ns 6

7 Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, p0.6, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. Parameter SYM Test Cnditin Min TYP MAX Units Thermal Shutdwn Thermal Shutdwn Nte4 40 C Hysteresis Nte4 20 Pwer Gd Pwer Gd upper PG(upper) b Rising Threshld Upper Threshld PG(upper)_Dly b Rising 256/s S Delay Pwer Gd lwer PG(lwer) b alling Threshld Lwer Threshld PG(lwer)_Dly b alling 256/s S Delay Delay Cmparatr PG(Delay) Relative t charge vltage, SS rising Threshld Delay Cmparatr Delay(hys) Nte m Hysteresis PGd ltage Lw PG(vltage) I PGd -5mA 0.5 Leakage Current I leakage 0 0 μa Switch Nde SW Bias Current Isw SW0, Enable0 SW0,Enablehigh,SS,p0, Nte4 6 μa Nte: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte4: Guaranteed by Design but nt tested in prductin. Nte5: Upgrade t industrial/msl2 level applies frm date cdes 4 (marking explained n applicatin nte AN2 page 2). Prducts with prir date cde f 4 are qualified with MSL fr Cnsumer market. 7

8 TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C) s 500 khz Icc(Standby) Ic(Dyn) [ua] [khz] Temp[ C] REQUENCY Temp[ C] [ua] [ma] Temp[ C] IOCSET(500kHz) Temp[ C] 4.46 cc(ulo) Start 4.6 cc(ulo) Stp [] 4.26 [] Temp[ C] Temp[ C] [] Enable(ULO) Start Temp[ C] [] Enable(ULO) Stp Temp[ ο C] 26.0 ISS [ua] Temp[ C] 8

9 Rdsn f MOSETs Over Temperature at cc5 Resistance [mω] PD Temperature [ C] Sync-ET Ctrl-ET 9

10 Typical Efficiency and Pwer Lss Curves in2, 0.75, cc5, I.0A-8A, s 400kHz, L0.6uH (MPL04-0R frm Delta), Rm Temperature, N Air lw Efficiency (%) Lad Current (A).2..0 Pwer Lss (W) Lad Current (A) 0

11 Typical Efficiency and Pwer Lss Curves in5, 0.75, cc5, I.0A-8A, s 400kHz, L0.6uH (MPL04-0R frm Delta), Rm Temperature, N Air lw Efficiency (%) Lad Current (A).2..0 Pwer Lss (W) Lad Current (A)

12 Circuit Descriptin THEORY O OPERATION Intrductin The IR8W uses a PWM vltage mde cntrl scheme with external cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency is prgrammable frm 250kHz t.5mhz and prvides the capability f ptimizing the design in terms f size and perfrmance. IR8W prvides precisely regulated utput vltage prgrammed via tw external resistrs frm 0.6 t 0.9*in. The IR8W perates with an external bias supply frm 4.5 t 5.5, allwing an extended perating input vltage range frm.0 t 6. If the input t the Enable pin is derived frm the bus vltage by a suitably prgrammed resistive divider, it can be ensured that the IR8W des nt turn n until the bus vltage reaches the desired level. Only after the bus vltage reaches r exceeds this level will the vltage at Enable pin exceed its threshld, thus enabling the IR8W. Therefre, in additin t being a lgic input pin t enable the IR8W, the Enable feature, with its precise threshld, als allws the user t implement an Under-ltage Lckut fr the bus vltage in. This is desirable particularly fr high utput vltage applicatins, where we might want the IR8W t be disabled at least until in exceeds the desired utput vltage level. The device utilizes the n-resistance f the lw side MOSET as current sense element, this methd enhances the cnverter s efficiency and reduces cst by eliminating the need fr external current sense resistr. IR8W includes tw lw R ds(n) MOSETs using IR s HEXET technlgy. These are specifically designed fr high efficiency applicatins. Under-ltage Lckut and POR The under-vltage lckut circuit mnitrs the input supply cc and the Enable input. It assures that the MOSET driver utputs remain in the ff state whenever either f these tw signals drp belw the set threshlds. Nrmal peratin resumes nce cc and Enable rise abve their threshlds. The POR (Pwer On Ready) signal is generated when all these signals reach the valid lgic level (see system blck diagram). When the POR is asserted the sft start sequence starts (see sft start sectin). ig. a. Nrmal Start up, Device turns n when the Bus vltage reaches 0.2 igure b. shws the recmmended start-up sequence fr the nn-tracking peratin f IR8W, when Enable is used as a lgic input. Enable The Enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by Under-ltage Lckut (ULO) circuit. Therefre, the IR8W will turn n nly when the vltage at the Enable pin exceeds this threshld, typically,.2. ig. b. Recmmended startup sequence, Nn-Tracking peratin 2

13 igure c. shws the recmmended startup sequence fr tracking peratin f IR8W with Enable used as lgic input. ig. 5. Pre-Bias startup pulses ig. c. Recmmended startup sequence, Sequenced peratin Pre-Bias Startup IR8W is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSET ff until the first gate signal fr cntrl MOSET is generated. igure 4 shws a typical Pre-Bias cnditin at start up. The synchrnus MOSET always starts with a narrw pulse width and gradually increases its duty cycle with a step f 25%, 50%, 75% and 00% until it reaches the steady state value. The number f these startup pulses fr the synchrnus MOSET is internally prgrammed. igure 5 shws a series f 2, 6, 8 startup pulses. Sft-Start The IR8W has a prgrammable sft-start t cntrl the utput vltage rise and limit the current surge at the start-up. T ensure crrect start-up, the sft-start sequence initiates when the Enable and cc rise abve their ULO threshlds and generate the Pwer On Ready (POR) signal. The internal current surce (typically 20uA) charges the external capacitr C ss linearly frm 0 t. igure 6 shws the wavefrms during the sft start. The start up time can be estimated by: p * C T start 20μA SS () During the sft start the OCP is enabled t prtect the device fr any shrt circuit and ver current cnditin. ig. 6. Theretical peratin wavefrms during sft-start ig. 4. Pre-Bias startup

14 Operating requency The switching frequency can be prgrammed between 250kHz 500kHz by cnnecting an external resistr frm R t pin t Gnd. Table tabulates the scillatr frequency versus R t. Table. Switching requency and I OCSet vs. External Resistr (R t ) R t (kω) s (khz) I cset (μa) Shutdwn The IR8W can be shutdwn by pulling the Enable pin belw its threshld. This will tristate bth, the high side driver as well as the lw side driver. Alternatively, the utput can be shutdwn by pulling the sft-start pin belw 0.. Nrmal peratin is resumed by cycling the vltage at the Sft Start pin. Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the R DS(n) f lw side MOSET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr (R OCSet ) is cnnected between OCSet pin and the switch nde (SW) which sets the current limit set pint. An internal current surce surces current (I OCSet ) ut f the OCSet pin. This current is a functin f the switching frequency and hence, f R t. Table. shws I OCSet at different switching frequencies. The internal current surce develps a vltage acrss R OCSet. When the lw side MOSET is turned n, the inductr current flws thrugh the Q2 and results in a vltage at OCSet which is given by: OCSet ( IOCSet ROCSet ) ( R ) I DS(n L )...() ig. 7. Cnnectin f ver current sensing resistr An ver current is detected if the OCSet pin ges belw grund. Hence, at the current limit threshld, OCset 0. Then, fr a current limit setting I Limit,R OCSet is calculated as fllws: R I OCSet OCSet 400 (μa)...(2) R (kω) R DS( n) * I t OCSet I Limit......(4) An vercurrent detectin trips the OCP cmparatr, latches OCP signal and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by shrting the sft-start capacitr t grund and cunting the number f switching cycles. The Sft Start pin is held lw until 4096 cycles have been cmpleted. The OCP signal resets and the cnverter recvers. After every sft start cycle, the cnverter stays in this mde until the verlad r shrt circuit is remved. The OCP circuit starts sampling current typically 60 ns after the lw gate drive rises t abut. This delay functins t filter ut switching nise. 4

15 Thermal Shutdwn Temperature sensing is prvided inside IR8W. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSETs and discharges the sft start capacitr. Autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld. Pwer Gd Output The IC cntinually mnitrs the utput vltage via eedback (b pin). The Pwer Gd signal is flagged when the b pin vltage is abve 0.5 and between 85% t 5 % f p. This pin is pen drain and it needs t be externally pulled high. High state indicates that utput is in regulatin. ig. 8a shws the PGd timing diagram fr nn-tracking peratin. In this case, during startup, PGd ges high after the SS vltage reaches 2. if the b vltage is within the PGd cmparatr windw. ig. 8a. and ig 8b. als shw a 256 cycle delay between the b vltage entering within the threshlds defined by the PGd windw and PGd ging high. TIMING DIAGRAM O PGOOD UNCTION ig.8a IR8W Nn-Tracking Operatin ig.8b IR8W Tracking Operatin 5

16 Minimum n time Cnsideratins The minimum ON time is the shrtest amunt f time fr which the Cntrl ET may be reliably turned n, and this depends n the internal timing delays. r the IR8W, the typical minimum n-time is specified as 50 ns. Any design r applicatin using the IR8W must ensure peratin with a pulse width that is higher than this minimum n-time and preferably higher than 00 ns. This is necessary fr the circuit t perate withut jitter and pulseskipping, which can cause high inductr current ripple and high utput vltage ripple. In any applicatin that uses the IR8W, the fllwing cnditin must be satisfied: t t n n(min) t n(min) in D s in t s n ut The minimum utput vltage fr the IR8W is limited t ut(min) 0.6. s ut in t ut s n(min) Maximum Duty Rati Cnsideratins A fixed ff-time f 200 ns maximum is specified fr the IR8W. This prvides an upper limit n the perating duty rati at any given switching frequency. It is clear, that higher the switching frequency, the lwer is the maximum duty rati at which the IR8W can perate. T allw a margin f 50ns, the maximum perating duty rati in any applicatin using the IR8W shuld still accmmdate abut 250 ns ff-time. ig 9. shws a plt f the maximum duty rati v/s the switching frequency, with 250 ns ff-time. Max Duty Cycle (%) Max Duty Cycle Switching requency (khz) ig. 9. Maximum duty cycle v/s switching frequency. in in s t s ut(min) n(min) ns 6 0 /s urthermre, fr the IR8W, especially fr active bus terminatin applicatins, it is strngly recmmended t use a switching frequency f 400 khz t btain clean and jitter free peratin in surcing as well as sinking mdes. Therefre, the maximum input vltage that may be stepped dwn t 0.6 at 400 khz withut jitter r pulse skipping is

17 Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr IR8W. The applicatin circuit is shwn n page 22. Enabling the IR8W As explained earlier, the precise threshld f the Enable lends itself well t implementatin f a ULO fr the Bus ltage. I in Δ s 2 (.2 max) A 22.5m 400kHz IR8W in r a typical Enable threshld f EN.2 r a in (min) 0.2, R 49.9K and R 2 7.5kΩ is a gd chice. Prgramming the frequency r s 400 khz, select R t 5.7 kω, using Table.. Output ltage Prgramming Output vltage is prgrammed by the tracking reference vltage at p and external vltage divider. The divider is ratied such that the vltage at the b pin is equal t the vltage at the p pin pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: R + 8 R p 9 R Enable R 2 R2 in (min) * EN.2... (5) R R R 2 R + 2 EN in( min ) EN... (6) (7) When an external resistr divider is cnnected t the utput as shwn in figure 0. Equatin (5) can be rewritten as: p R 9 R (8) p r lw vltage applicatins, such as this design, it is ften advisable t eliminate the bias resistr R9 frm b t grund. r the calculated value f R8 see feedback cmpensatin sectin. ig. 0. Typical applicatin f the IR8W fr prgramming the utput vltage urther, the tracking reference p may be itself derived frm sme master reference by means f a resistive divider as shwn in ig. 9. This is cmmn in active bus terminatin circuits such as ltage Tracking Terminatin (TT) where the tracking reference p may be btained as half f the master reference DDQ which frms the input t ne r mre memry banks. In this design, DDQ.5 R p R p2.5 kω p0.75 It is desirable t use a small capacitr such as 0n in parallel with R p2 t bypass high frequency nise n p pin. Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. rm (), fr a desired start-up time f the cnverter, the sft start capacitr can be calculated by using: C DDQ R p R p2 SS p b IR8W ( μ) T ( ms ) (9) start Where T start is the desired start-up time (ms). r tracking applicatins the utput is generally required t track p even at start-up. Hence, it is necessary t ensure that the SS pin is already up t befre the tracking reference signal is applied t the p pin. This can be dne by chsing a small value fr the sft-start capacitr t ensure that the vltage at the SS pin rises t quickly. A u capacitr is chsen fr this purpse. R8 R9 7

18 Btstrap Capacitr Selectin T drive the Cntrl ET, it is necessary t supply a gate vltage at least 4 greater than the vltage at the SW pin, which is cnnected the surce f the Cntrl ET. This is achieved by using a btstrap cnfiguratin, which cmprises the internal btstrap dide and an external btstrap capacitr (C6), as shwn in ig.. The peratin f the circuit is as fllws: When the lwer MOSET is turned n, the capacitr nde cnnected t SW is pulled dwn t grund. The capacitr charges twards cc thrugh the internal btstrap dide, which has a frward vltage drp D. The vltage c acrss the btstrap capacitr C6 is apprximately given as When the upper MOSET turns n in the next cycle, the capacitr nde cnnected t SW rises t the bus vltage in. Hwever, if the value f C6 is apprpriately chsen, the vltage c acrss C6 remains apprximately unchanged and the vltage at the Bt pin becmes Bt A btstrap capacitr f value 0.u is suitable fr mst applicatins. Input Capacitr Selectin The ripple current generated during the n time f the upper MOSET shuld be prvided by the input capacitr. The RMS value f this ripple is expressed by: I c RMS in cc + I D ( D) (2) D... (0) cc D... () ig.. Btstrap circuit t generate c vltage D Where: D is the Duty Cycle I RMS is the RMS value f the input capacitr current. I is the utput current. r I 8 A and D , the I RMS.94 A Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ESR and ESL at higher frequency which enables better efficiency. r this applicatin, it is advisable t have x0u 6 ceramic capacitrs ECJ-YXC06K frm Panasnic. In additin t these, althugh nt mandatry, a 0u 25 SMD capacitr EE-KEP frm Panasnic may be used as a bulk capacitr, and is recmmended if the input pwer supply is nt lcated clse t the cnverter. Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value results in a smaller size and faster respnse t a lad transient but pr efficiency and high utput nise due t large ripple current. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr ( Δi). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. r the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing relatin: in L Where: in in ( ) () Δi L ; Δt D Δt s Δi * in Maximum input vltage Output ltage Δi Inductr ripple current Switching frequency s in Δt Turn n time D Duty cycle... (4) If Δi 5%(I ), then the utput inductr is calculated t be 0.6μH. Select L0.6 μh. The MPL04-0R6 frm Delta prvides a cmpact, lw prfile inductr suitable fr this applicatin. s 8

19 Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series Resistance (ESR). Hwever the : actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as Δ Δ Δ Δ ( ESL) Δ ( ESR) ( ESR) ( C) + Δ ΔI in ΔI 8 * C ( ESL) L L * ESR L * ESL * + Δ s ( C)... (5) The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure 2). The resnant frequency f the LC filter is expressed as fllws: LC igure 2 shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system runs the risk f being unstable. Gain 0 db 2 π L C -40dB/decade (6) Phase 0 0 Δ Output vltage ripple ΔI L Inductr ripple current Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determines the result f transient respnse, selectin f the capacitr is critical. The IR8W can perfrm well with all types f capacitrs. As a rule, the capacitr must have lw enugh ESR t meet utput ripple and lad transient requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre it is advisable t select ceramic capacitrs due t their lw ESR and ESL and small size. Eight f the Panasnic ECJ- 2B0J226ML (22u, 6., mohm) capacitrs is a gd chice. eedback Cmpensatin The IR8W is a vltage mde cntrller. The cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed-lp transfer functin with the highest 0 db crssing frequency and adequate phase margin (greater than 45 ). ig. 2. Gain and Phase f LC filter The IR8W uses a vltage-type errr amplifier with high-gain (0dB) and wide-bandwidth. The utput f the errr amplifier is available fr DC gain cntrl and AC phase cmpensatin. The errr amplifier can be cmpensated either in type II r type III cmpensatin. Lcal feedback with Type II cmpensatin is shwn in ig.. This methd requires that the utput capacitr shuld have enugh ESR t satisfy stability requirements. In general the utput capacitr s ESR generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ESR zer f the utput capacitr is expressed as fllws: ESR LC requency 2 π*esr*c requency LC... (7) 9

20 Z IN OUT R8 R C POLE C4 Z f Where: in Maximum Input ltage sc Oscillatr Ramp ltage Crssver requency ESR Zer requency f the Output Capacitr LC Resnant requency f the Output ilter R 8 eedback Resistr H(s) db Gain(dB) Z R9 RE E/A The transfer functin ( e / ) is given by: POLE The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: b ig.. Type II cmpensatin netwrk and its asympttic gain plt ( ) H s e Zf + sr C H( s) Z sr C R R 8 z 2π * R * C...(8) irst select the desired zer-crssver frequency ( ): ESR Use the fllwing equatin t calculate R: R IN (9) (20) ( /5~/0) s > and * sc * in * * ESR 2 LC * R (2) e Cmp requency T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: 75% z LC z 0. 75* 2π L * C (22) Use equatins (20), (2) and (22) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and R. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: P 2π * R C * C 4 4 * C + C POLE POLE (2) The ple sets t ne half f the switching frequency which results in the capacitr C POLE : C POLE (24) π*r *R * * π s s C 4 r a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ESR values, we shuld implement lcal feedback with a type III cmpensatin netwrk. The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 4. Again, the transfer functin is given by: e Zf H( s) Z By replacing Z in and Z f accrding t figure 4, the transfer functin can be expressed as: H( s) sr ( C 8 4 ( + sr C ) C + C) + sr C 4 IN [ + sc ( R + R )] * C + C 0 ( + sr 0...(25) C ) 7 20

21 ZIN OUT C Cmpensatr Type ESR vs Output Capacitr C7 R0 R8 R C4 Zf Type II LC < ESR < < s /2 Electrlytic Tantalum R9 b E/A e Cmp Type III LC < < ESR Tantalum Ceramic ig.4. Type III Cmpensatin netwrk and its asympttic gain plt The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: H(s) db P P2 P Z Z (26) 2π * R C4 * C 2π * R C4 + C 2π * R * C 2π * C Crss ver frequency is expressed as: Gain(dB) 0 R * C7 * 7 * C 4 7 * ( R in sc (27) 2π * R (29) 8 + R 0 * 2π * L * C RE Z Z2 P2 P ) 2π * C * C 7 * R...(28) 8 requency...(0) () Based n the frequency f the zer generated by the utput capacitr and its ESR, relative t crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types and lcatin f the crssver frequency. The higher the crssver frequency, the ptentially faster the lad transient respnse. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. Typically, the cntrl lp bandwidth r crssver frequency is selected such that The DC gain shuld be large enugh t prvide high DC-regulatin accuracy. The phase margin shuld be greater than 45 fr verall stability. r this design we have: in sc.8 p0.75 L 0.6 uh C 8x22u, ESRmOhm each It must be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. r instance, the small signal capacitance f the 22u capacitr used in this design is 2u at 0.75 DC bias and 400 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency LC and using equatin (6) t cmpute the small signal C. These result t: LC khz ESR 4.4 MHz s/2 200 khz ( /5~/0) s * Select crssver frequency: 60 khz Since LC < < s /2< ESR, TypeIII is selected t place the ple and zers. 2

22 Detailed calculatin f cmpensatin TypeIII Desired Phase Margin Θ 70 Z2 P2 Select: P Select: 0.5* Select:C Calculate R sin Θ 0.58 khz + sin Θ + sin Θ khz sin Θ Z * 200 khz 2.2n Calculate R, C 2π * * L * C * R C * s C4 2π * * R Z C 2π * * R P 7 0, R ; C ; C 8 Z2 R.47kΩ 5.29 khz and and C in 4 4 sc 54.4p, and R : ; R :.48 kω 20.47n, Select: 9 4 Select: C C 22 n 560p Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr (R OCSET ) frm the SW pin t the OCSet pin. The resistr can be calculated by using equatin (4). This resistr R OCSET must be placed clse t the IC. The R DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrst case peratin. I SET I I I R SET I (50% ver OCSet R L( critical ) DS(n) OCSet 8.5mΩ * mΩ (LIM) R 9.22μA OCSet R I DS( n) 8 A*.5 2A nminal.25kω Select OCSet utput (at 400kHz) current) R.24 kω Setting the Pwer Gd Threshld A windw cmparatr internally sets a lwer Pwer Gd threshld at 85% f p and an upper Pwer Gd threshld at 5% f p. When the vltage at the B pin is within the windw set by these threshlds, PGd is asserted. The PGd is an pen drain utput. Hence, it is necessary t use a pull up resistr R PG frm PGd pin t cc. The value f the pull-up resistr must be chsen such as t limit the current flwing int the PGd pin, when the utput vltage is nt in regulatin, t less than 5 ma. A typical value used is 4.7kΩ. s (2) R 0 2π * C * 7 P2 ; R 0 25 Ω, Select: R 0 20 Ω R8 2π * C * Select: R 8 7 Z2 -R 6.65kΩ 0 ; R 8 6.6kΩ, 22

23 Applicatin Diagram: ig. 5. Applicatin circuit diagram fr a 2 t 0.75, 8 A Pint Of Lad Cnverter Suggested Bill f Materials fr the applicatin circuit: Part Reference Quantity alue Descriptin Manufacturer Part Number 0u SMD Elecrlytic, size, 25, 20% Panasnic EE-KEP Cin 0u 206, 6, X5R, 20% TDK C26X5RE06M 0.u 060, 25, X7R, 0% Panasnic ECJ-BE04K L 0.6uH.5x0x4mm, 20%,.7mOhm Delta MPL04-0R6 C 8 22u 0805, 6., X5R, 20% Panasnic ECJ-2B0J226ML R 49.9k Thick ilm, 060,/0 W,% Rhm MCR0EZPX4992 R2 7.5k Thick ilm, 060,/0W,% Rhm MCR0EZPX750 R t 5.7k Thick ilm, 060,/0W,% Rhm MCR0EZPX572 R cset.24k Thick ilm, 060,/0W,% Rhm MCR0EZPX24 R PG 0k Thick ilm, 060,/0W,% Rhm MCR0EZPX002 C ss 0.022u 060, 25, X7R, 0% Panasnic ECJ-BE22K R.47k Thick ilm, 060,/0W,% Rhm MCR0EZPX47 C 560p 50, 060, NPO, 5% Panasnic ECJ-CH56J C6 0.u 060, 25, X7R, 0% Panasnic ECJ-BE04K C4 2200p 060, 50, X7R, 0% Panasnic ECJ-BH22K R8 6.65k Thick ilm, 060,/0W,% Rhm MCR0EZPX665 R0 20 Thick ilm, 060,/0W,% Rhm ERJ-EK200 C7 2200p 060, 50, X7R, 0% Panasnic ECJ-BH222K C p2 22n 060, 50, X7R, 0% Panasnic ECJ-BH22K C cc.0u 060, 6, X5R, 20% Panasnic ECJ-BBC05M U IR8W SupIRBuck, 8A, PQN 5x6mm Internatinal Rectifier 2

24 TYPICAL OPERATING WAEORMS in2.0, cc5, 0.75, I0- ±8A, Rm Temperature, N Air lw ig. 6: Start up at 8A, surcing current Ch :PGd, Ch 2 : ut, Ch :SS, Ch 4 : DDQ ig. 7: Start up with Prebias, 0A Lad Ch :PGd, Ch 2 : ut, Ch :SS, Ch 4 : DDQ ig. 8: Inductr nde at 8A, surcing current, Ch :SW, Ch 4 :I ut ig. 9: Inductr nde at -A, sinking current, Ch :SW, Ch 4 :I ut ig. 20: Output ltage Ripple, 8A, surcing current, Ch 2 : ut ig. 2: Shrt (Hiccup) Recvery Ch 2 : ut, Ch : SS, Ch 4 :PGd 24

25 TYPICAL OPERATING WAEORMS in2, cc5, 0.75, Rm Temperature, N Air lw ig. 22: Tracking 8A, surcing current, Ch 2 : ut, Ch : DDQ, Ch 4 :PGd ig. 2: Tracking -A lad, sinking current, Ch 2 : ut, Ch 2 : I L, Ch : DDQ, Ch 4 :PGd ig. 24: Transient Respnse, A/us -0.5A t +0.5A lad, Ch : ut, Ch :I 25

26 TYPICAL OPERATING WAEORMS in2, cc5, 0.75, I+8A, Rm Temperature, N Air lw PD ig. 25: Bde Plt at 8A lad (surcing current) shws a bandwidth f 59kHz and phase margin f 59 degrees 26

27 Layut Cnsideratins The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Make all the cnnectins fr the pwer cmpnents in the tp layer with wide, cpper filled areas r plygns. In general, it is desirable t make prper use f pwer planes and plygns fr pwer distributin and heat dissipatin. The inductr, utput capacitrs and the IR8W shuld be as clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place the input capacitr directly at the in pin f IR8W. The feedback part f the system shuld be kept away frm the inductr and ther nise surces. The critical bypass cmpnents such as capacitrs fr cc shuld be clse t their respective pins. It is imprtant t place the feedback cmpnents including feedback resistrs and cmpensatin cmpnents clse t b and Cmp pins. The cnnectin between the OCSet resistr and the Sw pin shuld nt share any trace with the cnnectin between the btstrap capacitr and the Sw pin. Instead, it is recmmended t use a Kelvin in cnnectin f the trace PGnd frm the OCSet resistr and the trace frm the btstrap in capacitr at the Sw pin. PGnd In a multilayer PCB use ne layer as a pwer grund plane and have a cntrl circuit ut grund (analg grund), t which all signals are referenced. The gal is t lcalize the high AGnd current path t a separate lp that des nt interfere AGnd with the mre sensitive ut analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The Pwer QN is a thermally enhanced package. Based n thermal perfrmance it is recmmended t use at least a 4-layers PCB. T effectively remve heat frm the device the expsed pad shuld be cnnected t the grund plane using vias. igure 26 illustrates the implementatin f the layut guidelines utlined abve, n a 4 layer bard. Cmpensatin parts shuld be placed as clse as pssible t the Cmp pin. in in PGnd PGnd Enugh cpper & minimum length grund path between Input and Output All bypass caps shuld be placed as clse as pssible t their cnnecting pins. Resistrs Rt and Rcset shuld be placed as clse as pssible t their pins. AGnd AGnd ut ut ig. 26a. IR8W layut cnsideratins Tp Layer 27

28 eedback trace shuld be kept away frm nise surces PGnd ig. 26b. IR8W layut cnsideratins Bttm Layer Analg Grund plane Single pint cnnectin between AGND & PGND, shuld be clse t the SupIRBuck, kept away frm nise surces. Pwer in Grund Plane AGnd ig. 26c. IR8W layut cnsideratins Mid Layer Use separate traces fr cnnecting Bt cap and Rcset t the switch nde and with the minimum length traces. Avid big lps. ig. 26d. IR8W layut cnsideratins Mid Layer 2 28

29 PCB Metal and Cmpnents Placement Lead lands (the IC pins) width shuld be equal t nminal part lead width. The minimum lead t lead spacing shuld be 0.2mm t minimize shrting. Lead land length shuld be equal t maximum part lead length + 0. mm utbard extensin. The utbard extensin ensures a large and inspectable te fillet. Pad lands (the 4 big pads ther than the IC pins) length and width shuld be equal t maximum part pad length and width. Hwever, the minimum metal t metal spacing shuld be n less than 0.7mm fr 2 z. Cpper; n less than 0.mm fr z. Cpper and n less than 0.2mm fr z. Cpper. 29

30 Slder Resist It is recmmended that the lead lands are Nn Slder Mask Defined (NSMD). The slder resist shuld be pulled away frm the metal lead lands by a minimum f 0.025mm t ensure NSMD pads. The land pad shuld be Slder Mask Defined (SMD), with a minimum verlap f the slder resist nt the cpper f 0.05mm t accmmdate slder resist mis-alignment. Ensure that the slder resist in-between the lead lands and the pad land is 0.5mm due t the high aspect rati f the slder resist strip separating the lead lands frm the pad land. 0

31 Stencil Design PD The Stencil apertures fr the lead lands shuld be apprximately 80% f the area f the lead lads. Reducing the amunt f slder depsited will minimize the ccurrences f lead shrts. If t much slder is depsited n the center pad the part will flat and the lead lands will be pen. The maximum length and width f the land pad stencil aperture shuld be equal t the slder resist pening minus an annular 0.2mm pull back t decrease the incidence f shrting the center land t the lead lands when the part is pushed int the slder paste.

32 BOTTOM IEW IR WORLD HEADQUARTERS: 2 Kansas St., El Segund, Califrnia 90245, USA Tel: (0) TAC ax: (0) This prduct has been designed and qualified fr the Industrial market (Nte5) isit us at fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 08/ 2