HIGHLY EFFICIENT INTEGRATED 9A, SYNCHRONOUS BUCK REGULATOR

Transcription

1 SupIRBuck TM Features Greater than 95% Maximum Efficiency Wide Input ltage Range.5 t 2 Wide Output ltage Range 0.7 t 0.9*in Cntinuus 9A Lad Capability Integrated Btstrap-dide High Bandwidth E/A fr excellent transient perfrmance Prgrammable Switching Frequency up t.5mhz Prgrammable Over Current Prtectin Over ltage Prtectin Dedicated input fr utput vltage mnitring Prgrammable PGd utput Hiccup Current Limit Precisin Reference ltage (0.7, +/-%) Prgrammable Sft-Start Enable Input with ltage Mnitring Capability Enhanced Pre-Bias Start-up Seq input fr Tracking applicatins External Synchrnizatin -40 C t 25 C perating junctin temperature Thermal Prtectin 4mm x 5mm Pwer QFN Package Halgen Free, Lead Free and RHS cmpliant Descriptin PD-9754 HIGHLY EFFICIENT INTEGRATED 9A, SYNCHRONOUS BUCK REGULATOR The IR3859 SupIRBuck TM is an easy-t-use, fully integrated and highly efficient DC/DC synchrnus Buck regulatr. The MOSFETs cpackaged with the n-chip PWM cntrller make IR3859 a space-efficient slutin, prviding accurate pwer delivery fr lw utput vltage applicatins. IR3859 is a versatile regulatr which ffers prgrammability f start up time, switching frequency and current limit while perating in wide input and utput vltage range. The switching frequency is prgrammable frm 250kHz t.5mhz fr an ptimum slutin. It als features imprtant prtectin functins, such as Pre-Bias startup, hiccup current limit and thermal shutdwn t give required system level security in the event f fault cnditins. Applicatins Server Applicatins Strage Applicatins Embedded Telecm Systems Distributed Pint f Lad Pwer Architectures Netcm Applicatins Cmputing Peripheral ltage Regulatrs General DC-DC Cnverters Fig.. Typical applicatin diagram

2 ABSOLUTE MAXIMUM RATINGS (ltages referenced t GND unless therwise specified) in t 25 cc t 8 (Nte2) Bt t 33 SW t 25(DC), -4 t 25(AC, 00ns) Bt t SW t cc+0.3 (Nte) OCSet t 30 (Max 30mA) Input / utput Pins t cc+0.3 (Nte) PGND t GND t +0.3 Strage Temperature Range C T 50 C Junctin Temperature Range C T 50 C (Nte2) ESD Classificatin JEDEC Class C Misture sensitivity level... JEDEC Level 3@260 C (Nte5) Nte: Must nt exceed 8 Nte2: cc must nt exceed 7.5 fr Junctin Temperature between -0 C and -40 C Stresses beynd thse listed under Abslute Maximum Ratings may cause permanent damage t the device. These are stress ratings nly and functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins are nt implied. PACKAGE INFORMATION 4mm x 5mm POWER QFN 3 2 IN SW PGnd θ θ θ JA JA ( Sync _ FET ( Ctrl _ FET J -PCB ) ) 45 C / W 45 C / W 2 C / W * * Bt Enable Seq Gnd cc Sync PGd * Expsed pads n underside are cnnected t cpper pads f a 4-layer (2 z.) PCB ORDERING INFORMATION Fb sns COMP Gnd Rt SS OCSet PACKAGE DESIGNATOR PACKAGE DESCRIPTION PIN COUNT PARTS PER REEL M IR3859MTRPbF M IR3859MTRPbF

3 Blck Diagram Fig. 2. Simplified blck diagram f the IR3859 3

4 Pin Descriptin PD-9754 Pin Name Descriptin Fb Inverting input t the errr amplifier. This pin is cnnected directly t the utput f the regulatr via resistr divider t set the utput vltage and prvide feedback t the errr amplifier. 2 sns Sense pin fr PGd 3 Cmp Output f errr amplifier. An external resistr and capacitr netwrk is typically cnnected frm this pin t Fb pin t prvide lp cmpensatin. 4;7 Gnd Signal grund fr internal reference and cntrl circuitry. 5 Rt Set the switching frequency. Cnnect an external resistr frm this pin t Gnd t set the switching frequency. See Table fr Fs vs. Rt. 6 SS/SD Sft start / shutdwn. This pin prvides user prgrammable sft-start functin. Cnnect an external capacitr frm this pin t Gnd t set the start up time f the utput vltage. The cnverter can be shutdwn by pulling this pin belw OCSet Current limit set pint. A resistr frm this pin t SW pin will set the current limit threshld. 8 PGd Pwer Gd status pin. Output is pen drain. Cnnect a pull up resistr frm this pin t cc. 9 Sync Sync pin, cnnect external system clck t synchrnize multiple POLs with the same frequency 0 CC This pin pwers the internal IC and the drivers. A minimum f uf high frequency capacitr must be cnnected frm this pin t the pwer grund (PGnd). PGnd Pwer Grund. This pin serves as a separated grund fr the MOSFET drivers and shuld be cnnected t the system s pwer grund plane. 2 SW Switch nde. This pin is cnnected t the utput inductr. 3 IN Input vltage cnnectin pin. 4 Bt Supply vltage fr high side driver. A 0.uF capacitr must be cnnected frm this pin t SW. 5 Enable Enable pin t turn n and ff the device. Use tw external resistrs t set the turn n threshld (see Enable sectin). Cnnect this pin t cc if it is nt used. 6 Seq Sequence pin. Use tw external resistrs t set Simultaneus Pwer up sequencing. If this pin is nt used cnnect t cc. 4

5 Recmmended Operating Cnditins Symbl Definitin Min Max Units in Input ltage.5 2* cc Supply ltage Bt t SW Supply ltage Output ltage *in I Output Current 0 9 A Fs Switching Frequency khz T j Junctin Temperature C * Nte: SW nde shuld nt exceed 25 Electrical Specificatins Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT POWER STAGE Pwer Lsses P lss cc5, in 2,.8, I 9A, Fs600kHz, L0.68uH, Nte4 2. W Tp Switch R ds(n)_tp Bt - sw 5, I D9A, Tj25 C 2 29 Bttm Switch R ds(n)_bt cc5, I D9A, T j25 C 6 mω Deadband Time T db Nte ns Btstrap Dide Frward ltage I(Bt) 30mA m SW leakage Current Isw SW0, Enable0 SW0, Enablehigh, SS3, seq0, Nte4 SUPPLY CURRENT CC Supply Current (Standby) I CC(Standby) SS0, cc5, Enable lw, N Switching CC Supply Current (Dyn) I CC(Dyn) SS3, cc5, Enable high, Fs500kHz 6 ua 500 ua ma REFERENCE OLTAGE Feedback ltage FB 0.7 Accuracy 0 C<Tj<25 C C<Tj<25 C, Nte % SOFT START / SD Sft Start Current ISS Surce ua Sft Start Clamp ltage ss(clamp) Shutdwn Output Threshld SD 0.3 5

6 Electrical Specificatins (cntinued) Unless therwise specified, these specificatins apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT ERROR AMPLIFIER Input Offset ltage s fb-seq, seq m Input Bias Current IFb(E/A) - + Input Bias Current Iseq(E/A) - + μa Sink Current Isink(E/A) Surce Current Isurce(E/A) ma Slew Rate SR Nte /μs Gain-Bandwidth Prduct GBWP Nte MHz DC Gain Gain Nte db Maximum ltage max(e/a) cc Minimum ltage min(e/a) m Seq Cmmn Mde ltage Nte4 0 OSCILLATOR Rt ltage rt Frequency Range Rt59K F S Rt28.7K Rt9.3K, Nte khz Ramp Amplitude ramp Nte4.8 p-p Ramp Offset Ramp(s) Nte4 0.6 Min Pulse Width Dmin(ctrl) Nte4 50 ns Max Duty Cycle Dmax Fs250kHz 92 % Fixed Off Time Tff Nte ns Sync Frequency Range Fsync khz Sync Pulse Duratin Tsync ns Sync Level Threshld High 2 Lw 0.6 6

7 Electrical Specificatins (cntinued) Unless therwise specified, these specificatin apply ver 4.5< cc <5.5, in 2, 0 C<T j < 25 C. Typical values are specified at T a 25 C. PARAMETER SYMBOL TEST CONDITION MIN TYP MAX UNIT FAULT PROTECTION Fs250kHz OCSET Current I OCSET Fs500kHz ua Fs500kHz OC cmp Offset ltage OFFSET Nte m SS ff time SS_Hiccup 4096 Cycles OP Trip Threshld OP(trip) sns Rising %ref OP Fault Prp. Delay OP(delay) Nte4 50 ns Thermal Shutdwn Nte4 40 Thermal Hysteresis Nte4 20 CC -Start-Threshld CC _ULO_Start cc Rising Trip Level CC -Stp-Threshld CC _ULO_Stp cc Falling Trip Level C INPUT/OUTPUT SIGNAL Enable-Start-Threshld Enable_ULO_Start Supply ramping up Enable-Stp-Threshld Enable_ULO_Stp Supply ramping dwn Enable leakage current Ien Enable3.3 5 ua Pwer Gd Threshld PG sns Rising %ref PGd Cmparatr Delay PG(Delay) sns Rising 256/Fs s PGd Delay Cmparatr Threshld SS(Delay) Relative t charge vltage, SS rising PGd Delay Cmparatr Hysteresis Delay(SShys) Nte m PGd Leakage Current I(PGDlk) 0 0 ua PGd ltage Lw PG(vltage) I Pgd -5mA 0.5 Nte3: Cld temperature perfrmance is guaranteed via crrelatin using statistical quality cntrl. Nt tested in prductin. Nte4: Guaranteed by Design but nt tested in prductin. Nte5: Upgrade t industrial/msl2 level applies frm date cdes 227 (marking explained n applicatin nte AN32 page 2). Prducts with prir date cde f 227 are qualified with MSL3 fr Cnsumer market. 7

8 Typical Efficiency and Pwer Lss Curves in2, cc5, I0.9A- 9A, F s 600kHz, Rm Temperature, N Air Flw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. () L (uh) P/N DCR (mohm) PR9876N PR9876N ETQP4LR68XFC ETQP4LR68XFC MPL05-R MPL05-R PD-9754 Efficiency (%) Lad Current (A) Pwer Lss (W) Lad Current (A)

9 Typical Efficiency and Pwer Lss Curves in5, cc5, I0.9A- 9A, Fs600kHz, Rm Temperature, N Air Flw The table belw shws the inductrs used fr each f the utput vltages in the efficiency measurement. PD-9754 () L (uh) P/N DCR (mohm) PR9875N PR9876N PR9876N PR9876N PR9876N 0.29 Efficiency (%) Lad Current (A) Pwer Lss (W) Lad Current (A).0ut.2ut.5ut.8ut 3.3ut 9

10 Rdsn f MOSFETs Over Temperature at cc5 Resistance [mω] Temperature [ C] Sync-FET Ctrl-FET Thermal De-rating Curves Test Cnditins: in2, ut.8, cc5, Fs600kHz, 0-200LFM L0.68uH (ETQP4LR68XFC) 9.0 Maximum Lad Current (A) Ambient Temperature ( C) 0 LFM 00LFM 200LFM 0

11 Icc(Dyn) PD-9754 TYPICAL OPERATING CHARACTERISTICS (-40 C - 25 C) F s 500 khz Icc(Standby) [ua] [khz] Temp[ C] FREQUENCY Temp[ C] [ma] [ua] Temp[ C] IOCSET(500kHz) Temp[ C] 4.46 cc(ulo) Start 4.6 cc(ulo) Stp [] 4.26 [] [] 4.06 Enable(ULO) Start Temp[ C] Temp[ C] ISS [] Temp[ C] Enable(ULO) Stp Temp[ ο C] fb [ua] [m] Temp[ C] Temp[ C]

12 Circuit Descriptin THEORY OF OPERATION Intrductin The IR3859 uses a PWM vltage mde cntrl scheme with external cmpensatin t prvide gd nise immunity and maximum flexibility in selecting inductr values and capacitr types. The switching frequency is prgrammable frm 250kHz t.5mhz and prvides the capability f ptimizing the design in terms f size and perfrmance. IR3859 prvides precisely regulated utput vltage prgrammed via tw external resistrs frm 0.7 t 0.9*in. The IR3859 perates with an external bias supply frm 4.5 t 5.5, allwing an extended perating input vltage range frm.5 t 2. If the input t the Enable pin is derived frm the bus vltage by a suitably prgrammed resistive divider, it can be ensured that the IR3859 des nt turn n until the bus vltage reaches the desired level. Only after the bus vltage reaches r exceeds this level will the vltage at Enable pin exceed its threshld, thus enabling the IR3859. Therefre, in additin t being a lgic input pin t enable the IR3859, the Enable feature, with its precise threshld, als allws the user t implement an Under-ltage Lckut fr the bus vltage in. This is desirable particularly fr high utput vltage applicatins, where we might want the IR3859 t be disabled at least until in exceeds the desired utput vltage level. The device utilizes the n-resistance f the lw side MOSFET as current sense element, this methd enhances the cnverter s efficiency and reduces cst by eliminating the need fr external current sense resistr. IR3859 includes tw lw R ds(n) MOSFETs using IR s HEXFET technlgy. These are specifically designed fr high efficiency applicatins. Fig. 3a. Nrmal Start up, Device turns n when the Bus vltage reaches 0.2 Under-ltage Lckut and POR The under-vltage lckut circuit mnitrs the input supply cc and the Enable input. It assures that the MOSFET driver utputs remain in the ff state whenever either f these tw signals drp belw the set threshlds. Nrmal peratin resumes nce cc and Enable rise abve their threshlds. The POR (Pwer On Ready) signal is generated when all these signals reach the valid lgic level (see system blck diagram). When the POR is asserted the sft start sequence starts (see sft start sectin). Figure 3b. shws the recmmended start-up sequence fr the nn-sequenced peratin f IR3859, when Enable is used as a lgic input. Enable The Enable features anther level f flexibility fr start up. The Enable has precise threshld which is internally mnitred by Under-ltage Lckut (ULO) circuit. Therefre, the IR3859 will turn n nly when the vltage at the Enable pin exceeds this threshld, typically,.2. Fig. 3b. Recmmended startup sequence, Nn-Sequenced peratin 2

13 Figure 3c. shws the recmmended startup sequence fr sequenced peratin f IR3859 with Enable used as lgic input. Fig. 5. Pre-Bias startup pulses Fig. 3c. Recmmended startup sequence, Sequenced peratin Pre-Bias Startup IR3859 is able t start up int pre-charged utput, which prevents scillatin and disturbances f the utput vltage. The utput starts in asynchrnus fashin and keeps the synchrnus MOSFET ff until the first gate signal fr cntrl MOSFET is generated. Figure 4 shws a typical Pre-Bias cnditin at start up. The synchrnus MOSFET always starts with a narrw pulse width and gradually increases its duty cycle with a step f 25%, 50%, 75% and 00% until it reaches the steady state value. The number f these startup pulses fr the synchrnus MOSFET is internally prgrammed. Figure 5 shws a series f 32, 6, 8 startup pulses. Sft-Start The IR3859 has a prgrammable sft-start t cntrl the utput vltage rise and t limit the current surge at the start-up. T ensure crrect start-up, the sft-start sequence initiates when the Enable and cc rise abve their ULO threshlds and generate the Pwer On Ready (POR) signal. The internal current surce (typically 20uA) charges the external capacitr C ss linearly frm 0 t 3. Figure 6 shws the wavefrms during the sft start. The start up time can be estimated by: T start (.4-0.7) * C 20μA SS () During the sft start the OCP is enabled t prtect the device fr any shrt circuit and ver current cnditin. Fig. 6. Theretical peratin wavefrms during sft-start Fig. 4. Pre-Bias startup 3

14 Operating Frequency The switching frequency can be prgrammed between 250kHz 500kHz by cnnecting an external resistr frm R t pin t Gnd. Table tabulates the scillatr frequency versus R t. Table. Switching Frequency and I OCSet vs. External Resistr (R t ) R t (kω) F s (khz) I cset (μa) Shutdwn The IR3859 can be shutdwn by pulling the Enable pin belw its threshld. This will tristate bth, the high side driver as well as the lw side driver. Alternatively, the utput can be shutdwn by pulling the sft-start pin belw 0.3. Nrmal peratin is resumed by cycling the vltage at the Sft Start pin. Over-Current Prtectin The ver current prtectin is perfrmed by sensing current thrugh the R DS(n) f lw side MOSFET. This methd enhances the cnverter s efficiency and reduces cst by eliminating a current sense resistr. As shwn in figure 7, an external resistr (R OCSet ) is cnnected between OCSet pin and the switch nde (SW) which sets the current limit set pint. An internal current surce surces current (I OCSet ) ut f the OCSet pin. This current is a functin f Rt and hence, f the free-running switching frequency. I OCSet Table. shws I OCSet at different switching frequencies. The internal current surce develps a vltage acrss R OCSet. When the lw side MOSFET is turned n, the inductr current flws thrugh the Q2 and results in a vltage at OCSet which is given by: OCSet ( IOCSet ROCSet ) ( R ) I DS(n L )...(3) Fig. 7. Cnnectin f ver current sensing resistr An ver current is detected if the OCSet pin ges belw grund. Hence, at the current limit threshld, OCset 0. Then, fr a current limit setting I Limit,R OCSet is calculated as fllws: R 400 (μa)...(2) R (kω) OCSet R t DS(n) I * OCSet I Limit......(4) An vercurrent detectin trips the OCP cmparatr, latches OCP signal and cycles the sft start functin in hiccup mde. The hiccup is perfrmed by shrting the sft-start capacitr t grund and cunting the number f switching cycles. The Sft Start pin is held lw until 4096 cycles have been cmpleted. The OCP signal resets and the cnverter recvers. After every sft start cycle, the cnverter stays in this mde until the verlad r shrt circuit is remved. The OCP circuit starts sampling current typically 60 ns after the lw gate drive rises t abut 3. This delay functins t filter ut switching nise. 4

15 Thermal Shutdwn Temperature sensing is prvided inside IR3859. The trip threshld is typically set t 40 C. When trip threshld is exceeded, thermal shutdwn turns ff bth MOSFETs and discharges the sft start capacitr. Autmatic restart is initiated when the sensed temperature drps within the perating range. There is a 20 C hysteresis in the thermal shutdwn threshld..5 <in<6 4.5 <cc<5.5 PGd Enable cc PGd Seq Rt SS/ SD Gnd in Bt SW OCSet Fb Cmp PGnd RA RB (master).5 <in<6 Output ltage Sequencing The IR3859 can accmmdate user prgrammable sequencing ptins using Seq, Enable and Pwer Gd pins. 4.5 <cc<5.5 (master) cc Enable in Bt SW (slave) PGd RE RF PGd Seq Rt SS/ SD Gnd OCSet Fb Cmp PGnd RC RD Simultaneus Pwerup 2 Fig. 8a. Simultaneus Pwer-up f the slave with respect t the master. Thrugh these pins, vltage sequencing such as simultaneus and sequential can be implemented. Figure 8. shws simultaneus sequencing cnfiguratins. In simultaneus pwer-up, the vltage at the Seq pin f the slave reaches 0.7 befre the Fb pin f the master. Fr R E /R F R C /R D, therefre, the utput vltage f the slave fllws that f the master until the vltage at the Seq pin f the slave reaches 0.7. After the vltage at the Seq pin f the slave exceeds 0.85, the internal 0.7 reference f the slave dictates its utput vltage. Fig. 8b. Applicatin Circuit fr Simultaneus Sequencing Pwer-Gd and Over-vltage Prtectin The sns pin frms an input t a windw cmparatr whse upper and lwer threshlds are and 0.595, respectively. Hence, the Pwer Gd signal is flagged when the sns pin vltage is within the PGd windw, i.e. between t 0.805, as shwn in figure 9. The PGd pin is pen drain and it needs t be externally pulled high. High state indicates that utput is in regulatin. Figure 9a shws the PGd timing diagram fr nn-tracking peratin. In this case, during startup, PGd ges high after the SS vltage reaches 2. if the sns vltage is within the PGd cmparatr windw. Figure 9.a and Figure 9.b als shw a 256 cycle delay between the sns vltage entering within the threshlds defined by the PGd windw and PGd ging high. If the utput vltage exceeds the ver vltage threshld, an ver vltage trip signal asserts, this will result t turn ff the high side driver and turn n the lw side driver until the sns vltage drps belw.5*ref threshld. Bth drivers are latched ff until a reset perfrmed by cycling either cc r Enable. The OP threshld can be externally prgrammed t user defined value. Figure 0 shws the respnse in ver-vltage cnditin. 5

16 TIMING DIAGRAM OF PGOOD FUNCTION PD SS.5*ref(typical), +/-5% fr Min/Max PGd windw sns 0 PGd *ref(typical), +/-5% fr Min/Max 00ns(typical) Delay At pint A the pwer Gd signal ges lw, high drive turns ff, lw drive turns n till sns is abve Over ltage threshld and the device latches ff. POR (cc/enable) needs t be recycled fr new start up. 00ns(typical) Delay 256/Fs A Fig.9a IR3859 Nn-Tracking Operatin (Seqcc) Fig.9b IR3859 Tracking Operatin 6

17 TIMING DIAGRAM OF Over ltage Prtectin PD-9754 Fig.0 IR3859 Over ltage Timing Diagram External Synchrnizatin The IR3859 incrprates an internal circuit which enables synchrnizatin f the internal scillatr (using rising edge) t an external clck. An external resistr frm Rt pin t Gnd is still required t set the free-running frequency clse t the Sync input frequency. This functin is imprtant t avid sub-harmnic scillatins due t beat frequency fr embedded systems when multiple POL (pint f lad) regulatrs are used. The synchrnizatin clck can be applied during IR3859 nrmal peratin r befre IR3859 startup. In any case, IR3859 will perfrm with the external after the end f the PreBias cycle. Applying the external signal t the Sync input changes the effective value f the ramp signal (ramp/sc). sc ( eff ). 8 f Free _Run f Sync...(5) the frequency f the Sync (f Sync ) and the freerunning frequency (f Free_Run ) results in mre change in the effective amplitude f the ramp signal. Therefre, since the ramp amplitude takes part in calculating the lp-gain and bandwidth f the regulatr, it is recmmended nt t use a Sync frequency which is much higher than the freerunning frequency. In additin, the effective value f the ramp signal, given by equatin (5), shuld be used when the cmpensatr is designed fr the regulatr. The pulse width f the external clck, which is applied t the sync, shuld be greater than 00ns and its high level shuld be greater than 2, while its lwer level is less than 0.6. If this pin is left flating, the IC will run with the free running frequency set by the resistr Rt. Equatin (5) shws that the effective amplitude f the ramp ( sc(eff) ) is reduced after the external Sync signal is applied. Mre difference between 7

18 Minimum n time Cnsideratins The minimum ON time is the shrtest amunt f time fr which the Cntrl FET may be reliably turned n, and this depends n the internal timing delays. Fr the IR3859, the typical minimum n-time is specified as 50 ns. Any design r applicatin using the IR3859 must ensure peratin with a pulse width that is higher than this minimum n-time and preferably higher than 00 ns. This is necessary fr the circuit t perate withut jitter and pulse-skipping, which can cause high inductr current ripple and high utput vltage ripple. In any applicatin that uses the IR3859, the fllwing cnditin must be satisfied: t t n n(min) t n(min) in D F s in F t s n ut in F The minimum utput vltage is limited by the reference vltage and hence ut(min) 0.7. Therefre, fr ut(min) 0.7, s ut F t ut s n(min) Maximum Duty Rati Cnsideratins A fixed ff-time f 200 ns maximum is specified fr the IR3859. This prvides an upper limit n the perating duty rati at any given switching frequency. It is clear, that higher the switching frequency, the lwer is the maximum duty rati at which the IR3859 can perate. T allw a margin f 50ns, the maximum perating duty rati in any applicatin using the IR3859 shuld still accmmdate abut 250 ns ff-time. Fig 0. shws a plt f the maximum duty rati v/s the switching frequency, with 250 ns ff-time. Max Duty Cycle (%) Max Duty Cycle Switching Frequency (khz) Fig.. Maximum duty cycle v/s switching frequency. in in F s F s ut(min) tn(min) ns /s Therefre, at the maximum recmmended input vltage 2 and minimum utput vltage, the cnverter shuld be designed at a switching frequency that des nt exceed 333 khz. Cnversely, fr peratin at the maximum recmmended perating frequency.65 MHz and minimum utput vltage, any vltage abve 4.2 may nt be stepped dwn withut pulseskipping. 6 8

19 Applicatin Infrmatin Design Example: The fllwing example is a typical applicatin fr IR3859. The applicatin circuit is shwn n page 25. Enabling the IR3859 As explained earlier, the precise threshld f the Enable lends itself well t implementatin f a ULO fr the Bus ltage. Fr a maximum Enable threshld f EN.36 Fr a in (min) 0.2, R 49.9K and R 2 7.5K is a gd chice. Prgramming the frequency Fr F s 600 khz, select R t 23.7 kω, using Table.. Output ltage Prgramming Output vltage is prgrammed by reference vltage and external vltage divider. The Fb pin is the inverting input f the errr amplifier, which is internally referenced t 0.7. The divider is ratied t prvide 0.7 at the Fb pin when the utput is at its desired value. The utput vltage is defined by using the fllwing equatin: in 2 ( 3.2 max).8 I 9 A Δ ± 5% f F 600 khz s in (min) IR3859 Enable R8 ref + R9 in R R 2 R2 * EN.36...(6) R + R R2 R 2 EN in( min ) EN...(7) (8) When an external resistr divider is cnnected t the utput as shwn in figure 2. Equatin (6) can be rewritten as: ref R9 R8 ref Fr the calculated values f R8 and R9 see feedback cmpensatin sectin. IR3859 IR3624 Fb OUT Fig. 2. Typical applicatin f the IR3859 fr prgramming the utput vltage Sft-Start Prgramming The sft-start timing can be prgrammed by selecting the sft-start capacitance value. Frm (), fr a desired start-up time f the cnverter, the sft start capacitr can be calculated by using: C SS Where T start is the desired start-up time (ms). Fr a start-up time f 3.5ms, the sft-start capacitr will be 0.099μF. Chse a 0.μF ceramic capacitr. Btstrap Capacitr Selectin (9) T drive the Cntrl FET, it is necessary t supply a gate vltage at least 4 greater than the vltage at the SW pin, which is cnnected the surce f the Cntrl FET. This is achieved by using a btstrap cnfiguratin, which cmprises the internal btstrap dide and an external btstrap capacitr (C6), as shwn in Fig. 3. The peratin f the circuit is as fllws: When the lwer MOSFET is turned n, the capacitr nde cnnected t SW is pulled dwn t grund. The capacitr charges twards cc thrugh the internal btstrap dide, which has a frward vltage drp D. The vltage c acrss the btstrap capacitr C6 is apprximately given as c cc D When the upper MOSFET turns n in the next cycle, the capacitr nde cnnected t SW rises t the bus vltage in. Hwever, if the value f C6 is apprpriately chsen, the vltage c R8 R9 ( μf ) T ( ms ) (0) start...() 9

20 acrss C6 remains apprximately unchanged and the vltage at the Bt pin becmes: Bt in + cc D...(2) Inductr Selectin The inductr is selected based n utput pwer, perating frequency and efficiency requirements. A lw inductr value causes large ripple current, resulting in the smaller size, faster respnse t a lad transient but pr efficiency and high utput nise. Generally, the selectin f the inductr value can be reduced t the desired maximum ripple current in the inductr (Δi ). The ptimum pint is usually fund between 20% and 50% ripple f the utput current. Fr the buck cnverter, the inductr value fr the desired perating ripple current can be determined using the fllwing relatin: A btstrap capacitr f value 0.uF is suitable fr mst applicatins. Input Capacitr Selectin The ripple current generated during the n time f the upper MOSFET shuld be prvided by the input capacitr. The RMS value f this ripple is expressed by: I Fig. 3. Btstrap circuit t generate c vltage RMS D I in D ( D )...(3)...(4) Where: D is the Duty Cycle I RMS is the RMS value f the input capacitr current. I is the utput current. Fr I 9A and D 0.5, the I RMS 3.2A. Ceramic capacitrs are recmmended due t their peak current capabilities. They als feature lw ESR and ESL at higher frequency which enables better efficiency. Fr this applicatin, it is advisable t have 4x0uF 25 ceramic capacitrs C326X5RE06M frm TDK. In additin t these, althugh nt mandatry, a X330uF, 25 SMD capacitr EE-FKE33P may als be used as a bulk capacitr and is recmmended if the input pwer supply is nt lcated clse t the cnverter. Δi in L ; Δt D Δt Fs... (5) L ( in ) Δi * F Where: in Maximum input vltage Output ltage Δi Inductr ripple current F Switching frequency s in Δt Turn n time D Duty cycle If Δi 42%(I ), then the utput inductr is calculated t be 0.69μH. Select L0.68 μh. The ETQP4LR68XFC frm Panasnic prvides a cmpact inductr suitable fr this applicatin. s 20

21 Output Capacitr Selectin The vltage ripple and transient requirements determine the utput capacitrs type and values. The criteria is nrmally based n the value f the Effective Series Resistance (ESR). Hwever the actual capacitance value and the Equivalent Series Inductance (ESL) are ther cntributing cmpnents. These cmpnents can be described as Δ Δ Δ ( ESR ) ( ESR ) + Δ ΔI ( ESL) L * ESR + Δ (C ) The utput LC filter intrduces a duble ple, 40dB/decade gain slpe abve its crner resnant frequency, and a ttal phase lag f 80 (see figure 3). The resnant frequency f the LC filter is expressed as fllws: F LC 2 π L C...(7) Figure 4 shws gain and phase f the LC filter. Since we already have 80 phase shift frm the utput filter alne, the system runs the risk f being unstable. Δ ( ESL) Δ (C ) in L ΔIL 8* C * F * ESL s...(6) Δ Output vltage ripple ΔI L Inductr ripple current Since the utput capacitr has a majr rle in the verall perfrmance f the cnverter and determines the result f transient respnse, selectin f the capacitr is critical. The IR3859 can perfrm well with all types f capacitrs. As a rule, the capacitr must have lw enugh ESR t meet utput ripple and lad transient requirements. The gal fr this design is t meet the vltage ripple requirement in the smallest pssible capacitr size. Therefre it is advisable t select ceramic capacitrs due t their lw ESR and ESL and small size. Six f the TDK C202X5R0J226M (22uF, 6.3, 3mOhm) capacitrs is a gd chice. Feedback Cmpensatin The IR3859 is a vltage mde cntrller. The cntrl lp is a single vltage feedback path including errr amplifier and errr cmparatr. T achieve fast transient respnse and accurate utput regulatin, a cmpensatin circuit is necessary. The gal f the cmpensatin netwrk is t prvide a clsed-lp transfer functin with the highest 0 db crssing frequency and adequate phase margin (greater than 45 ). Fig. 4. Gain and Phase f LC filter The IR3859 uses a vltage-type errr amplifier with high-gain (0dB) and wide-bandwidth. The utput f the amplifier is available fr DC gain cntrl and AC phase cmpensatin. The errr amplifier can be cmpensated either in Type-II r Type-III cmpensatin. Lcal feedback with Type-II cmpensatin is shwn in figure 4. This methd requires that the utput capacitr shuld have enugh ESR t satisfy stability requirements. In general, fr Type-II cmpensatin the utput capacitr s ESR generates a zer typically at 5kHz t 50kHz which is essential fr an acceptable phase margin. The ESR zer f the utput capacitr is expressed as fllws: F ESR 2 π*esr*c...(8) 2

22 Where: in Maximum Input ltage sc Oscillatr Ramp ltage F Crssver Frequency F ESR Zer Frequency f the Output Capacitr F LC Resnant Frequency f the Output Filter R 8 Feedback Resistr T cancel ne f the LC filter ples, place the zer befre the LC filter resnant frequency ple: F 75% F z LC Fz 0. 75* 2π L * C...(23) Fig. 5. Type II cmpensatin netwrk and its asympttic gain plt The transfer functin ( e / ) is given by: sr3c sr C e Zf + H(s) ZIN The (s) indicates that the transfer functin varies as a functin f frequency. This cnfiguratin intrduces a gain and zer, expressed by: ( ) H s R R 3 8 Fz 2π * R * C 3 First select the desired zer-crssver frequency (F ): ESR Use the fllwing equatin t calculate R3: (9)... (20) 4... (2) ( /5 ~ /0) Fs F > F and F * Use equatins (2), (22) and (23) t calculate C4. One mre capacitr is smetimes added in parallel with C4 and R3. This intrduces ne mre ple which is mainly used t suppress the switching nise. The additinal ple is given by: F P 2π * R 3 C * C 4 4 * C + C POLE POLE...(24) The ple sets t ne half f the switching frequency which results in the capacitr C POLE : C POLE......(25) π*r *R 3*F 3*F π s s C 4 Fr a general slutin fr uncnditinal stability fr any type f utput capacitrs, and a wide range f ESR values, we shuld implement lcal feedback with a Type-III cmpensatin netwrk. The typically used cmpensatin netwrk fr vltage-mde cntrller is shwn in figure 6. Again, the transfer functin is given by: e Zf H( s) Z IN R 3 sc * F * F in * F ESR 2 LC * R 8...(22) By replacing Z in and Z f accrding t figure 6, the transfer functin can be expressed as: H(s)...(26) sr 8 ( + sr C )[ + sc ( R + R )] 4 3 ( C + C ) + sr ( + sr C ) C C 4 7 * C + C

23 ZIN OUT C3 Cmpensatr Type F ESR vs F Output Capacitr C7 R0 R8 R3 C4 Zf Type II F LC <F ESR <F <F s /2 Electrlytic Tantalum R9 Fb E/A e Cmp Type III F LC <F <F ESR Tantalum Ceramic H(s) db Fig.6. Type III Cmpensatin netwrk and its asympttic gain plt The cmpensatin netwrk has three ples and tw zers and they are expressed as fllws: F F F F F P P2 P3 Z Z2 0...(27)...(28 ) 2π * R0 * C7...(29) C4 * C3 2π * R3 * C3 2π * R3 C4 C (30) 2π * R3 * C4...(3) 2π * C * (R + R ) 2π * C * R Crss ver frequency is expressed as: F Gain(dB) 7 in R3 * C7 * sc 8 REF FZ FZ2 FP2 FP3 0 * 2π * L * C 7 8 Frequency...(32) Based n the frequency f the zer generated by the utput capacitr and its ESR, relative t crssver frequency, the cmpensatin type can be different. The table belw shws the cmpensatin types fr relative lcatins f the crssver frequency. The higher the crssver frequency, the ptentially faster the lad transient respnse. Hwever, the crssver frequency shuld be lw enugh t allw attenuatin f switching nise. Typically, the cntrl lp bandwidth r crssver frequency is selected such that The DC gain shuld be large enugh t prvide high DC-regulatin accuracy. The phase margin shuld be greater than 45 fr verall stability. Fr this design we have: in 2.8 sc.8 ref 0.7 L 0.68uH C 6x22uF, ESR3mOhm each It must be nted here that the value f the capacitance used in the cmpensatr design must be the small signal value. Fr instance, the small signal capacitance f the 22uF capacitr used in this design (i.e. C326X5RE06M frm TDK) is 9.5uF at.8 DC bias and 600 khz frequency. It is this value that must be used fr all cmputatins related t the cmpensatin. The small signal value may be btained frm the manufacturer s datasheets, design tls r SPICE mdels. Alternatively, they may als be inferred frm measuring the pwer stage transfer functin f the cnverter and measuring the duble ple frequency F LC and using equatin (6) t cmpute the small signal C. These result t: F LC 25.5 khz F ESR 5.5 MHz F s /2300 khz ( /5 ~ /0) Fs F * Select crssver frequency F 00 khz Since F LC <F <F s /2<F ESR, Type-III is selected t place the ple and zers. 23

24 Detailed calculatin f cmpensatin Type-III Desired F Z2 F P2 Select: F F P3 0.5* F Select:C 2.2nF Calculate R, C Select: R Calculate R R 0 F F 2π * C * F Select: R Phase sin Θ khz + sin Θ + sin Θ 567.kHz sin Θ Z C4 2π * F ref R9-0. 5* F kω Z P R8 2π * C * F 3 C3 2π * F * R 3 P2 Z2 ; 4.02 kω Margin Θ 70 Z2 ; C4 * R 8.82 khz khz and C 2π * F * L * C * R3 C * s ref in 9 3 -R : 094. nf, Select: C R 0 sc Ω, ;C 32pF,, R and R : and ;R.66 kω Select: C ; R 3.97 kω, 3 Select: R nf 270 pf 0 30 Ω * R ; R 2.56 kω Select: R 2.55 kω Prgramming the Current-Limit The Current-Limit threshld can be set by cnnecting a resistr (R OCSET ) frm the SW pin t the OCSet pin. The resistr can be calculated by using equatin (4). This resistr R OCSET must be placed clse t the IC. The R DS(n) has a psitive temperature cefficient and it shuld be cnsidered fr the wrst case peratin. R ISET I( LIM ) 9 A * A (50% ver nminal utput I OCSet R DS( n) OCSet mω* mω μa 3.4 kω (at Select F 600 khz) 3.6 kω Setting the Pwer Gd Threshld current Pwer Gd threshld can be prgrammed by using tw external resistrs (R5, R7 n Page 24). The fllwing frmula can be used t set the threshld: R6 ( 0. 85* ( PGd _TH ) ref Where: 0.85*ref is reference f the internal cmparatr, fr IR3859. (PGd_TH) is the selectable utput vltage threshld fr pwer gd, fr this design it is.53 (i.e. 0.85*.8). Select R KOhm Using (24): R KOhm Select R KOhm The PGd is an pen drain utput. Hence, it is necessary t use a pull up resistr R PG frm PGd pin t cc. The value f the pull-up resistr must be chsen such as t limit the current flwing int the PGd pin, when the utput vltage is nt in regulatin, t less than 5 ma. A typical value used is 0kΩ. s R 7 )* R (33) ) I SET I L ( critical ) R OCSet R I DS ( n ) OCSet.... (32) 24

25 Applicatin Diagram: in2 4.5 <cc<5.5 R 49.9 K R2 7.5K Cin 4 X 0 uf uf+x0.uf RPG 0 K PGd CSS 0. uf Ccc uf Rt 23.7 K Seq cc PGd Sync Rt SS/ SD Enable Gnd in Bt SW OCSet sns Fb Cmp PGnd C4 0 nf ROCSet 3.6 K R3.65 K C3 270 pf C6 0. uf R K R K L 0.68uH R K R K C7 2.2nF R0 30 C6X22uF Fig. 7. Applicatin circuit diagram fr a 2 t.8, 9A Pint Of Lad Cnverter Suggested Bill f Materials fr the applicatin circuit: Part Reference Quantity alue Descriptin Manufacturer Part Number 330uF SMD Elecrlytic, Fsize, 25, 20% Panasnic EE-FKE33P Cin 4 0uF 206, 25, X5R, 20% TDK C326X5RE06M 0.uF 0603, 25, X7R, 0% Panasnic ECJ-BE04K L 0.68uH.7x0x4mm, 20%,.58mOhm Panasnic ETQP4LR68XFC C 6 22uF 0805, 6.3, X5R, 20% TDK C202X5R0J226M R 49.9k Thick Film, 0603,/0 W,% Rhm MCR03EZPFX4992 R2 7.5k Thick Film, 0603,/0W,% Rhm MCR03EZPFX750 R t 23.7k Thick Film, 0603,/0W,% Rhm MCR03EZPFX2372 R PG 0k Thick Film, 0603,/0W,% Rhm MCR03EZPFX002 C ss C6 2 0.uF 0603, 25, X7R, 0% Panasnic ECJ-BE04K R3.65k Thick Film, 0603,/0W,% Rhm MCR03EZPFX65 C3 270pF 50, 0603, NPO, 5% Panasnic ECJ-CH27J C4 0nF 0603, 50, X7R, 0% Panasnic ECJ-BH03K R8 R k Thick Film, 0603,/0W,% Rhm MCR03EZPFX402 R9 R k Thick Film, 0603,/0W,% Rhm MCR03EZPFX255 Rcset 3.6k Thick Film, 0603,/0W,% Rhm MCR03EZPFX36 R0 30 Thick Film, 0603,/0W,% Panasnic ERJ-3EKF300 C7 2200pF 0603, 50, X7R, 0% Panasnic ECJ-BH222K C cc.0uf 0603, 6, X5R, 20% Panasnic ECJ-BBC05M U IR3859 SupIRBuck, 9A, PQFN 4x5mm Internatinal Rectifier 25

26 TYPICAL OPERATING WAEFORMS in2.0, cc5,.8, I0-9A, Rm Temperature, N Air Flw Fig. 8: Start up at 9A Lad Ch : in, Ch 2 : ut, Ch 3 : ss, Ch 4 :Enable Fig. 9: Start up at 9A Lad, Ch : in, Ch 2 : ut, Ch 3 : ss, Ch 4 : PGd Fig. 20: Start up with.62 Pre- Bias, 0A Lad, Ch 2 : ut, Ch 3 : SS Fig. 2: Output ltage Ripple, 9A lad Ch 2 : ut Fig. 22: Inductr nde at 9A lad Ch 2 : Switch Nde Fig. 23: Shrt (Hiccup) Recvery Ch 2 : ut, Ch 3 : ss 26

27 TYPICAL OPERATING WAEFORMS in2, cc5,.8, I4.5A- 9A, Rm Temperature, N Air Flw PD-9754 Fig. 24: Transient Respnse, 4.5A t 9A step 2.5A/μs Ch 2 : ut, Ch 4 :I ut 27

28 TYPICAL OPERATING WAEFORMS in2, cc5,.8, I9A, Rm Temperature, N Air Flw Fig. 25: Bde Plt at 9A lad shws a bandwidth f 92kHz and phase margin f 54 degrees Fig. 26: Synchrnizatin t 700kHz external clck signal at 9A lad Ch : SW (Switch Nde) Ch 2 :Sync 28

29 TYPICAL OPERATING WAEFORMS Simultaneus Tracking at Pwer Up and Pwer Dwn in2,.8, I9A, Rm Temperature, N Air Flw K R s IR3859 IR3624 Seq Fb OUT R8 4.02K 2.55K R s2 R9 2.55K Fig. 27: Simultaneus Tracking a 3.3 input at pwer-up and shut-dwn Ch : SEQ(3.3) Ch 2 :SS(.8) Ch 4 : ut(.8) 29

30 Layut Cnsideratins The layut is very imprtant when designing high frequency switching cnverters. Layut will affect nise pickup and can cause a gd design t perfrm with less than expected results. Make all the cnnectins fr the pwer cmpnents in the tp layer with wide, cpper filled areas r plygns. In general, it is desirable t make prper use f pwer planes and plygns fr pwer distributin and heat dissipatin. The inductr, utput capacitrs and the IR3859 shuld be as clse t each ther as pssible. This helps t reduce the EMI radiated by the pwer traces due t the high switching currents thrugh them. Place the input capacitr directly at the in pin f IR3859. The feedback part f the system shuld be kept away frm the inductr and ther nise surces. The critical bypass cmpnents such as capacitrs fr cc shuld be clse t their respective pins. It is imprtant t place the feedback cmpnents including feedback resistrs and cmpensatin cmpnents clse t Fb and Cmp pins. The cnnectin between the OCSet resistr and the SW pin shuld nt share any trace with the cnnectin between the btstrap capacitr and the SW pin. Instead, it is recmmended t use a Kelvin cnnectin in f the trace PGnd frm the OCSet resistr and the trace frm the btstrap in capacitr at the SW pin. PGnd In a multilayer PCB use ne layer as a pwer grund plane and have a cntrl circuit AGnd ut grund (analg grund), t which all signals are referenced. The gal is t lcalize the high current path t a separate lp that des nt interfere AGnd with the mre sensitive ut analg cntrl functin. These tw grunds must be cnnected tgether n the PC bard layut at a single pint. The Pwer QFN is a thermally enhanced package. Based n thermal perfrmance it is recmmended t use at least a 4-layers PCB. T effectively remve heat frm the device the expsed pad shuld be cnnected t the grund plane using vias. Figure 28 illustrates the implementatin f the layut guidelines utlined abve, n the IRDC layer dembard. Enugh cpper & minimum length grund path between Input and Output Cmpensatin parts shuld be placed as clse as pssible t the Cmp pin. in PGnd All bypass caps shuld be placed as clse as pssible t their cnnecting pins. Resistrs Rt, SS cap, and Rcset shuld be placed as clse as pssible t their pins. AGnd ut Fig. 28a. IRDC3859 dembard layut cnsideratins Tp Layer 30

31 in PGnd Single pint cnnectin between AGND & PGND; It shuld be clse t the SupIRBuck, kept away frm nise surces. PGnd SW ut Fig. 28b. IRDC3859 dembard layut cnsideratins Bttm Layer PGnd AGnd Fig. 28c. IRDC3859 dembard layut cnsideratins Mid Layer Use separate trace fr cnnecting Bst cap and Rcset t the switch nde and with the minimum length traces. Avid big lps. Feedback trace shuld be kept away frm nise surces Fig. 28d. IRDC3859 dembard layut cnsideratins Mid Layer 2 3

32 PCB Metal and Cmpnents Placement PD-9754 Evaluatins have shwn that the best verall perfrmance is achieved using the substrate/pcb layut as shwn in fllwing figures. PQFN devices shuld be placed t an accuracy f 0.050mm n bth X and Y axes. Self-centering behavir is highly dependent n slders and prcesses, and experiments shuld be run t cnfirm the limits f self-centering n specific prcesses. Fr further infrmatin, please refer t SupIRBuck Multi-Chip Mdule (MCM) Pwer Quad Flat N-Lead (PQFN) Bard Munting Applicatin Nte. (AN-32) PCB metal pad sizing (all dimensins in mm) PCB metal pad spacing (all dimensins in mm) 32

33 Slder Resist PD-9754 IR recmmends that the larger Pwer r Land Area pads are Slder Mask Defined (SMD.) This allws the underlying Cpper traces t be as large as pssible, which helps in terms f current carrying capability and device cling capability. When using SMD pads, the underlying cpper traces shuld be at least 0.05mm larger (n each edge) than the Slder Mask windw, in rder t accmmdate any layer t layer misalignment. (i.e. 0.mm in X & Y.) Hwever, fr the smaller Signal type leads arund the edge f the device, IR recmmends that these are Nn Slder Mask Defined r Cpper Defined. When using NSMD pads, the Slder Resist Windw shuld be larger than the Cpper Pad by at least 0.025mm n each edge, (i.e. 0.05mm in X&Y,) in rder t accmmdate any layer t layer misalignment. Ensure that the slder resist in-between the smaller signal lead areas are at least 0.5mm wide, due t the high x/y aspect rati f the slder mask strip. 33

34 Stencil Design PD-9754 Stencils fr PQFN can be used with thicknesses f mm ( "). Stencils thinner than 0.00mm are unsuitable because they depsit insufficient slder paste t make gd slder jints with the grund pad; high reductins smetimes create similar prblems. Stencils in the range f 0.25mm-0.200mm ( "), with suitable reductins, give the best results. Evaluatins have shwn that the best verall perfrmance is achieved using the stencil design shwn in fllwing figure. This design is fr a stencil thickness f 0.27mm (0.005"). The reductin shuld be adjusted fr stencils f ther thicknesses. Stencil pad sizing (all dimensins in mm) Stencil pad spacing (all dimensins in mm) 34

35 IR WORLD HEADQUARTERS: 233 Kansas St., El Segund, Califrnia 90245, USA Tel: (30) TAC Fax: (30) This prduct has been designed and qualified fr the Industrial market (Nte5) isit us at fr sales cntact infrmatin Data and specificatins subject t change withut ntice. 08/2 35