INTRODUCTION TO PLL DESIGN

Transcription

1 INTRODUCTION TO PLL DESIGN FOR FREQUENCY SYNTHESIZER Thanks Sung Tae Mn and Ari Valer fr part f this material A M S C Analg and Mixed-Signal Center

2 Cntents Intrductin t Frequency Synthesizer Specificatin Study PLL Design Testing Examples 2

3 Frequency Synthesizer in Transceiver LNA PA Mixer t baseband Frequency Synthesizer frm baseband FS prvides LO signal fr up/dwn cnversin Frequency accuracy is in the rder f tens f ppm High spectral purity in terms f phase nise and spurius signal Settling time requirement when switching channels 3

4 Cmmunicatin Standards T dwn = T slt T pkt = 625 μs 366μs = 259μs 4

5 Phase Nise Requirement SNR = ( P + P ) ( P + P + P ) SNR SIG LO Int N BW > P LO min P Sig +P LO P Int P Int +P N +P BW PSig P N P N P LO = PN DC Sig Calculated frm adjacent channel interference rejectin requirement SNR due t interference dwn cnversin has t be better then minimum required SNR Int BW f LO f BW < ( P P ) P SNR min 5

6 P N P LO = PN < ( P P ) P SNR Sig Int BW min Fr illustratin cnsider the Table in page 4, the Bluetth standard specifies an interferer f +40dB at 3MHz away frm the desired signal. SNRmin frm a BER f is 18dB. PBW = 10lg10 6 =60dB. Thus PN= -118DBc at 3MHz frm carrier. The cmputatin assumes phase white nise within the channel bandwidth 6

7 7 Spurius Signal V c V cntrl prt utput signal VCO VCO utput is mdulated by cupled signal n cntrl prt. Tw sideband tnes at ± m away frm the center frequency + + = + = + = t K t K t V t K t t V t K t V dt t v K t V t v m m m m c ) cs( 2 ) cs( 2 cs ) sin sin (cs ) sin cs( ) ) ( cs( ) (

8 Spur Requirement: Reference spur can be a serius prblem if the system uses narrw channel spacing and the spur cincides with the adjacent channels. This might ccur fr BT transceivers with an integer-n frequency synthesizer. P LO P Int P Sig +P LO P Sp P Int +P Sp P Sig P Sp P LO DC < ( P P ) SNR Sig Int f LO min Calculated frm adjacent channel interference rejectin requirement Since spur is nt nise, P BW is ut f equatin 8

9 Spur Requirement fr b P LO P Sp P Sig DC f LO Channel is wider then spur ffset System level simulatin is required t estimate the degradatin f the signal The reference spur must be at least 25dB belw the carrier signal t keep a BER better than 10-5 when the input SNR is 12dB 9

10 Spur Simulatin in Systemview 10

11 Spur Simulatin Result The effect f reference spur at 2M Hz in b system Spur Pwer 11

12 A basic phase lcked-lp architecture Reference Phase Detectr Errr Lp Filter Lp Filter Synchrnized Oscillatr y 0 = A csϕ OUT Re ference = y i = A i csϕ IN Errr = K P IN OUT ( ϕ ϕ θ ) 12

13 Integer-N Synthesizer VCO f REF PFD CP Lp Filter 1/N f ut f = N ut f REF Channel Selectin Only integer multiple f f REF is allwed fr utput f REF is nt necessarily equal t channel spacing f REF_max =GCD(f Channel,f Spacing ) 13

14 A numerical example.- Fr Wireless LAN b the standard specifies channels frm 2412 MHz t 2472 MHz in steps f 5 MHz. Thus the maximum fref is GCD(2412 MHz, 5MHz) = 1M Hz 14

15 Prcess f Operatin PFD cmpares the phase difference between the reference and the divided VCO utput. PFD utput is a series f pulses with duty cycle prprtinal t the phase difference. CP cnverts the vltage pulses int current pulses Lp filter cnverts current pulses int filtered vltage level. With negative feedback, the phase difference between the reference and the VCO becme smaller and smaller until they are exactly in-phase. Once lcked, the frequency f the VCO is equal t N times the reference frequency. 15

16 Charge-pump PLL Phase frequency detectr (PFD) extends acquisitin range t full VCO tuning range, nt limited by lp bandwidth Charge-pump and capacitive filter intrduce a ple at the rigin. Infinite DC gain leads t zer static phase errr 16

17 Charge-pump PLL Linear Mdel φ IN PFD CP 1/2π R 1 Lp Filter VCO C I 2 K /s C 1 (1+s/ z ) (1+s/ p )sc 1 φ OUT Transfer functin f phase / N 1/N PFD and CP is mdeled as cnstant gain VCO is mdeled as integratr Frequency divider is mdeled as cnstant lss 17

18 Linear Mdel Equatins Open-lp transfer functin T check phase margin fr stability Imprtant parameters : n (natural frequency), c (crssver frequency), z (zer), p (additinal ple) Clsed-lp transfer functin T check transient behavir, including settling time, versht and stability Imprtant parameters : n (natural frequency), ζ (damping factr) 18

19 Open-lp Transfer Functin H pen IK (1 + s / z ) ( s) = 2 2π C N s (1 + s / ) 1 p Tw ples at the rigin make the lp ptentially unstable Stabilizing zer at z makes the lp stable Additinal ple at p imprves rejectin f undesirable signal 19

20 Open-lp Transfer Functin (cnt.) Natural frequency Magnitude Phase z n c p = n IK 2πC N Crssver frequency c 2 n Zer frequency z = Ple frequency p 1 z 1 R C 1 1 R C

21 Stability due t Phase Margin Magnitude Phase Phase margin changes depend n placement f zer and ples Crssver frequency is apprximately same as lp bandwidth 21

22 Gardner s Stability Limit Since PFD and CP wrks in discrete time dmain, linear apprximatin fails when the lp bandwidth gets clse t sampling frequency Gardner s stability limit states < c REF π ( 1+ πz / REF Lp bandwidth shuld be cnsiderably lwer then reference frequency ) 22

23 23 Clsed-lp Transfer Functin ) /( / 1 / 1 ) /( ) /( / 1 / 1 ) ( D z z D p D z z clsed K K s s s K K s K K s s s s H = Secnd-rder transfer functin with a zer Imprtant parameters are n (natural frequency) and ζ (damping factr) C N IK K K D n 1 2π = = z n ζ 2 =

24 Clsed-lp Behavir Magnitude Transient In magnitude respnse, peaking ccurs due t zer in frward path. In transient respnse, versht ccurs when underdamped. 24

25 25 Settling Time Estimatin + Δ Δ Δ = 1 2 ) 1 ( ln 1) ( 1 ln 1 1 ln ζ α ζ ζ ζ ζ α ζ ζ α ζ n n n s f f f f f f t f is starting frequency, Δf is amunt f frequency jump, α is settling accuracy The larger the bandwidth, the faster the settling time Overdamping slws dwn settling time

26 Design Prcedure 1. Determine reference frequency frm requirements f REF =GCD(f Channel,f Spacing ) 2. Frm Gardner s stability limit, determine the lp bandwidth c < REF /10 3. Chse damping rati ζ 4. Calculate natural frequency n = c /2ζ 5. Check if settling time is gd enugh 6. Calculate zer and ple frequency z = n /2ζ, p = n x2ζ 26

27 Testing : Chip Micrpht 27

28 Testing : Failed Chip 28

29 Testing : PC Bard 29

30 Testing : Equipments Agilent infiniium Oscillscpe R&S FSEB Spectrum analyzer Agilent 33250A Functin Generatr HP 33120A Functin Generatr Agilent E3631A Pwer Supply 30

31 Testing Results : Tuning Range 31

32 Testing Results : High Spur 32

33 Testing Results : Lw Spur 33

34 Testing Results : Phase Nise 34

35 Testing Results : Settling Time 35

36 Testing Results : Unstable Settling 36