Performance of Switched-Capacitor Circuits Due to Finite Gain Amplifiers

Transcription

1 Perfrmance f Switched-apacitr ircuits Due t Finite Gain Amplifiers urse: EE35 Prepared by Rbert Wang Prepared fr Prfessr K. Phang Due Date: Nv 5 th, 00

2 able f ntents PERFORMANE OF SWIED-APAIOR IRUIS DUE O FINIE GAIN AMPLIFIERS... ABLE OF ONENS... LIS OF FIGURES... 3 LIS OF EQUAIONS INRODUION BAKGROUND ON S INEGRAORS AND FINIE GAIN ERROR REDUED SENSIIVIY S IRUI PREISE GAIN OPERAIONAL AMPLIFIERS SIGMA-DELA MODULAORS OVERSAMPLING E -BI ONVERER SUMMARY... 9 REFERENE...

3 List f Figures FIGURE : OMPLEMENARY INEGRAORS... 5 FIGURE : S IRUI WI REDUED SENSIIVIY O FINIE OPAMP GAIN... 9 FIGURE 3: ERROR OMPARISON USING REDUED FINIE GAIN SENSIIVIY S IRUI FIGURE 4: FIRS ORDER ELL FOR POG ANALYSIS... FIGURE 5: FIRS ORDER SIGMA DELA MODULAOR... 8 List f Equatins EQUAION : INVERING INEGRAOR RANSFER FUNION IN E Z-DOMAIN... 5 EQUAION : NON-INVERING INEGRAOR RANSFER FUNION IN E Z-DOMAIN... 6 EQUAION 3: RELAIONSIP... 6 EQUAION 4: IDEAL RANSFER FUNION OF E INVERING INEGRAOR... 6 EQUAION 5: IDEAL RANSFER FUNION OF E NON-INVERING INEGRAOR... 6 EQUAION 6: AUAL RANSFER FUNION... 6 EQUAION 7: APPROXIMAION O AUAL RANSFER FUNION... 7 EQUAION 8: AUAL RANSFER FUNION DUE O FINIE OPAMP GAIN... 7 EQUAION 9: INEGRAOR MAGNIUDE ERROR... 7 EQUAION 0: INEGRAOR PASE ERROR... 7 EQUAION : REDUED SENSIIVIY IRUI PASE... 0 EQUAION : REDUED SENSIIVIY IRUI PASE II... 0 EQUAION 3: IDEAL RANSFER FUNION OF FIGURE EQUAION 4: AUAL RANSFER FUNION OF FIGURE 4 USING FINIE GAIN... 3 EQUAION 5: POG APAIOR VALUES... 4 EQUAION 6: POG RANSFER FUNION USING POG APAIOR VALUES... 4 EQUAION 7: EFFEIVE GAIN OF POG... 4 EQUAION 8: FREQUENY SPERUM OF SAMPLED SIGNAL... 6 EQUAION 9: SNR... 6 EQUAION 0: SNR... 7 EQUAION : FIRS ORDER DIFFERENE EQUAION OF SIGMA-DELA MODULAOR

4 . Intrductin One f the distinct advantages f switched-capacitr S circuits is that they are cmpatible with existing MOS technlgy. ence, they are amng the mst ppular analg building blcks. wever, the standard design methdlgy assumes the use f infinite gain and infinite bandwidth peratinal amplifiers. he gain limitatin f peratinal amplifiers intrduces finite gain errr. Sectin f this paper discusses the backgrund f switched-capacitr circuit and derives the relative magnitude f the finite gain errr. After Sectin, three current design methds are intrduced in an attempt t minimizing the finite gain errr. Finally in the summary sectin, we cnclude with the advantages and disadvantages f each methd. 4

5 . Backgrund n S Integratrs and Finite Gain Errr Figure belw shws the inverting parasitic insensitive integratr and the nn inverting parasitic insensitive integratr. Bth are very ppular analg building blcks fr a variety f analg and mixed signal applicatins. Figure : mplementary Integratrs Please nte that the fllwing analysis is largely the result f [] and []. Using discrete analysis f difference equatins, the transfer functin f the abve integratrs can be fund in Equatin and Equatin [4]: z z z Equatin : Inverting Integratr ransfer Functin in the Z-dmain 5

6 6 z z Equatin : Nn-inverting Integratr ransfer Functin in the Z-dmain Using the relatinship presented in Equatin 3 belw, Equatin 4 and Equatin 5 can be derived frm Equatin and Equatin by simple substitutin. sin cs, sin cs, sin cs / / z z e z + + Equatin 3: Relatinship sin / e i Equatin 4: Ideal ransfer Functin f the Inverting Integratr sin / e i Equatin 5: Ideal ransfer Functin f the Nn-Inverting Integratr wever, the practical peratinal amplifier has limited gain. aking int accunt f the finite gain, the actual transfer functin f the integratrs can be expressed in the frm shwn in Equatin 6: [ ] θ i a e m Equatin 6: Actual ransfer Functin

7 7 In Equatin 6, m is the magnitude errr and θ is the phase errr. Fr small errrs where, << θ m, Equatin 6 can be apprximated using Equatin 7: θ m i a Equatin 7: Apprximatin t Actual ransfer Functin Using the fact that the peratinal amplifier has a finite D gain A, the actual transfer functin f bth integratrs is shwn in Equatin 8: + + tan A A i a Equatin 8: Actual ransfer Functin due t Finite Opamp Gain Using definitins stated earlier, we can identify the magnitude and the phase errr in Equatin 9 and Equatin 0: + A m Equatin 9: Integratr Magnitude Errr tan A θ Equatin 0: Integratr Phase Errr We see that if the peratinal amplifier gain is infinite, bth the magnitude errr m and the phase errr θ tend t zer. We als see that bth errrs are inversely

8 prprtinal t the pen lp gain A. In a practical circuit, the inverting terminal is nt a perfect virtual grund. his causes errr during charge transfer. he result is magnitude and phase errr f the integratr transfer functins. In the fllwing sectins, we lk at circuit design techniques that minimize the finite gain errr. 8

9 3. Reduced Sensitivity S ircuit As seen in Sectin, due t the use f finite gain peratinal amplifier, errr is intrduced during charge transferring. minimize this errr, a circuit design technique is prpsed in [3] t reduce the finite gain errr by reducing the circuit sensitivity t the pamp finite gain. By perfrming a preliminary peratin using additinal capacitrs that match the main switching capacitrs, a very clse apprximatin f the finite gain errr is btained. his errr is then stred and used during the final peratin. his circuit is shwn in Figure [6]. Figure : S ircuit with Reduced Sensitivity t Finite Opamp Gain [6] In Figure, and are the riginal capacitr in the inverting integratr cnfiguratin. 3 and 4 are additinal auxiliary capacitrs chsen such that the rati f 3/4 is the same as the rati f /. An additinal capacitr I, is used and its value is nt critical. 9

10 he peratin f the circuit is as fllws. Assuming the input is held cnstant. During phase, capacitr and are discharged. Depending n the rati f 3/4, a preliminary amplificatin/attenuatin is perfrmed using capacitrs 3 and 4. Nte that capacitr I is cnnected t grund and the imperfect virtual grund. Due t the finite gain pamp, this peratin cntains finite gain errr giving rise t a nn-zer vltage at the inverting input f the pamp. Shwn in Equatin is the relatinship between the utput vltage V5 and the input vltage at the inverting terminal V. he superscript dente that this relatinship hlds fr phase f the peratin. V Equatin : Reduced Sensitivity ircuit Phase During phase, amplificatin/attenuatin is perfrmed using capacitrs and. apacitrs 3 and 4 are discharged. he new vltage at Nde in Figure is the new value f V subtracting the ld value f V stred in I as shwn in Equatin. ence, finite gain errr is much reduced. V5 A V V V Equatin : Reduced Sensitivity ircuit Phase II Using mre in depth analysis, it is shwn that the value f I is nt critical as lng as it is much larger than the parasitic capacitance at Nde. And using this technique, it is shwn that the finite errr is reduced t abut A vs. as discussed in A Sectin. Figure 3 belw illustrates the effectiveness f this technique cmparing t the standard circuit. 0

11 In Figure 3, the amplitude errr is in percentage lg scale. urve shws the standard integratr circuit withut any finite gain errr reductin as discussed in Sectin. urve and curve 3 shws the amplitude errr f ther techniques used [3]. And urve 4 shws the amplitude errr f the circuit shwn in Figure. Frm Figure 3, we see that this technique perfrms much better at the expense f additinal auxiliary capacitrs. In terms f circuit design, mre than duble the capacitr area is required t achieve a much smaller finite gain errr. Figure 3: Errr mparisn using Reduced Finite Gain Sensitivity S ircuit [6]

12 4. Precise Gain Operatinal Amplifiers he cncept f a S circuit with reduced sensitivity t amplifier gain minimizes errr such that it can be used in very precise analg-t-digital design blcks. wever, it uses mre than twice the capacitr area which is undesirable since capacitrs cnsume very large silicn area in a chip. One alternative apprach is t use a precise pamp gain POG apprach [5]. As the name suggests, the gain A must be precisely knwn and it is used as a design parameter. By using this apprach, the effective gain f the amplifier is A / ε where epsiln is the maximum relative gain deviatin. he resulting accuracy is the same respnse accuracy f a standard circuit with an effective gain A / ε f the amplifier. Als, by reducing the gain f the amplifier, bandwidth f the amplifier can be increased. ence, POG designs are ften used in higher frequency S circuits. Let s take a lk at the analysis f the first rder cell presented in Figure 4. Figure 4: First Order ell fr POG Analysis [5]

13 Please nte that the fllwing analysis is largely the result f [5], and nly the imprtant steps are listed. Using standard analysis technique, assuming infinite pamp gain, the ideal transfer functin is given in Equatin 3. _ id z 3 + z Equatin 3: Ideal ransfer Functin f Figure 4 Nw, if the pamp gain is finite, the actual transfer functin is given in Equatin 4. We bserve that as pen lp gain tends t infinity, Equatin 4 is reduced t Equatin 3. btain the same transfer functin as the ideal transfer functin, POG capacitr values are btained frm the standard values as shwn in Equatin 5. ence, the transfer functin f the POG has the same frm as the actual transfer functin shwn in Equatin 6. It is imprtant t nte that althugh Equatin 4 and Equatin 6 share the same frm, Equatin 4 is the transfer functin f Figure 4 taking int accunt the finite gain f the amplifier. Equatin 6 is the transfer functin with adusted capacitance values accrding t the finite gain f amplifiers. Als, althugh the ntatin A is used fr the pen lp gain, the actual pamp gain is A ± ε deviatin and its magnitude is much smaller than., where epsiln is the gain _ act z A 3 + z A Equatin 4: Actual ransfer Functin f Figure 4 using Finite Gain 3

14 3 POG POG POG A A + A Equatin 5: POG apacitr Values POG z POG + 3POG + POG + A POG POG + 3POG + POG + ε A + ε Equatin 6: POG ransfer Functin using POG apacitr Values Frm Equatin 4 and Equatin 6, the relative ple deviatin can be cmpared using capacitr values defined in Equatin 5. he result shw that using the POG with an actual gain f ± ε an actual gain f A gives the same ple errr as with the standard apprach with z A eff A + + ε ε A ε Equatin 7: Effective Gain f POG Fr example, using the POG apprach with a gain deviatin ε 0. and an actual pamp gain A 00, the perfrmance is the same with the standard apprach as if the pamp gain is 000. Recall that in sectin, the finite gain errr is inversely prprtinal t the pamp gain. ence in this case using the POG apprach, the finite gain errr is reduced by rder f magnitude. he mre accurate r the smaller the gain deviatin, the larger the effective gain f the pamp. 4

15 5. Sigma-Delta Mdulatrs he tw circuit design technique presented in Sectin 3 and Sectin 4 are useful in terms f building accurate analg building blcks. wever, the draw back is still exists. Fr the circuit with reduced sensitivity t finite pamp gain, large silicn area is wasted t reduce finite gain errr. Fr the POG circuit, additinal design verhead is necessary t cmpute the precise gain value and use it as a design parameter in the capacitrs. In this sectin, a system design tplgy is intrduced that uses the cncept f feedback t minimize this errr. he cncept f sigma-delta mdulatrs have existed since the middle f this century. It has gained increase ppularity in the recent decade mainly due t the advancement in VLSI technlgy and digital signal prcessing. Using the current advance in VLSI technlgy, very high reslutin AD can be achieved using a -bit sigma-delta mdulatr fr lw and medium signal bandwidth. One f the key building blcks f the Sigma-Delta cnverter is the switched-capacitr integratr. he system architecture f the sigma-delta cnverter is discussed here t illustrate that this tplgy is nt nly tlerant t circuit nn-idealities and cmpnent mismatch, but als suppress quantizatin nise using the technique f versampling and feedback [4] [7] [8]. 5. Oversampling he analg-t-digital cnversin invlves tw steps: sampling in time and quantizatin in amplitude. Assuming x s t is the time dmain analg signal, its frequency spectrum is presented in Equatin 8. We see that in the frequency dmain, the signal spectrum is repeated f s apart. ence, t avid aliasing, ne must sample the 5

16 analg signal at equal r greater than twice the highest frequency cmpnent f X s f t avid aliasing. his is knwn as the Nyquist rate sampling criteria. X s f s k X f kf s Equatin 8: Frequency Spectrum f Sampled Signal Using the standard quantizatin nise mdel, that is, assuming the quantizatin nise is f a statinary randm prcess and it is uncrrelated with the input signal, the signal-t-nise rati can be derived and btained in Equatin 9. We see that fr every extra bit f reslutin increase, there is an equivalent increase f 6.0 db in the SNR. wever, increasing reslutin is very difficult fr Nyquist rate cnverters [7]. Fr example, if ne wishes t build a 6bit cnverter, the circuit needs t reslve a 98 db dynamic range. wever, circuit nn-ideality and cmpnent mismatch are t great, making this cnverter impractical fr general Nyquist rate cnverters. SNR [ db] 6.0N Equatin 9: SNR Instead f sampling at the Nyquist rate, by increasing the sampling frequency, greater SNR can be achieved withut using higher reslutin cnverters. By increasing the sampling frequency, the repeated input signal spectrum is als separated. his reduces the design requirement fr the anti-aliasing filter befre the A/D cnversin. he trade ff is speed vs. bandwidth. Assuming the fastest sampling frequency is fixed fr a given technlgy, increasing the sampling frequency effectively translates int reduced allwed signal bandwidth. Equatin 0 shws the SNR and sampling frequency 6

17 relatinship. It is bserved that fr every dubling f OSR, there is a 3.0 db increase in SNR. SNR db where [ ] 6.0N lg OSR f s OSR f Equatin 0: SNR, 5. he -bit nverter With the versampling discussed, we nw turn t the sigma-delta cnverter. A first rder sigma-delta mdulatr is presented in Figure 5. In this figure, the integratr samples the analg signal, and the quantizer is mdeled as an errr cmpnent that is intrduced int the system. Once the signal is sampled and quantized, it is passed int the digital dmain. he key t the first rder sigma-delta mdulatr is the feedback intrduced that cnverts the digital signal y[n] back int the analg dmain. his feedback frces y[n] t be very accurate. Althugh in this mdel, nly the quantizatin nise is mdeled. I believe that the nn-ideality f the circuit can als be mdeled as errr inputs int the system. ence, even thugh circuit nn-ideality and cmpnent mismatch exist, slving this system gives the mdulatr utput shwn in Equatin. he utput is essentially the first rder difference f the errr. his cncept can be extended t higher rder sigma delta systems, but the pint remains the same: the feedback in the sigma delta mdulatr allws the mdulatr utput, even thugh nly at ne bit, be very accurate prvided that the sampling frequency is much higher than the incming analg signal bandwidth. 7

18 Figure 5: First Order Sigma Delta Mdulatr y [] n x[ n ] + e[ n] e[ n ] Equatin : First Order Difference Equatin f Sigma-Delta Mdulatr 8

19 6. Summary Finite gain f peratinal amplifier causes finite gain errr f switched-capacitr circuit, degrading its perfrmance. In this paper, circuit design techniques were discussed t imprve the perfrmance f switched-capacitr circuit by minimizing the finite gain errr. In sectin 3, it is bserved that using a circuit with reduced sensitivity t the finite gain amplifier reduces finite gain errr frm t A A. his technique uses extra capacitrs hence increasing circuit area. Als, the assumptin f input being held cnstant is used during the circuit analysis. If the input frequency is cmparable t the switching frequency, the finite gain errr might nt be reduced as much. ence, this circuit is gd fr lw frequency applicatins. In sectin 4, the POG circuit uses the precise gain parameter f an amplifier as a design parameter in deriving capacitr values. his reduces the finite gain errr by a factr f ε, where epsiln is typically much less than. he POG apprach is great fr large bandwidth switched-capacitr circuit. Using a reduced gain, the bandwidth f the circuit can be increased withut the penalty f increasing finite gain errr by making the precise gain very accurate. wever, extra design verhead is required. he POG apprach is gd fr circuit that requires large bandwidth. It typically finds its applicatin in high frequency S circuits. In Sectin 5, the use f sigma-delta mdulatr uses feedback t minimize the utput errr, including the finite gain errr. Using the versampling technique, the -bit sigma-delta mdulatr can be made very accurate, but at the expense f bandwidth. ence, it is nly applicable t lw and medium frequency signals. 9

20 In this paper, nly the finite gain errr f S circuits is discussed. S circuits suffer frm anther drawback which is due t the finite bandwidth f amplifiers. Often, a design has t trade ff gain fr bandwidth. As circuit designers becme mre experienced in dealing with practical circuit limitatin and imperfectins, better circuits are designed that minimizes these imperfectins and pushes technlgy t its limit. 0

21 Reference [] G.. emes, Finite amplifier gain and bandwidth effects in switched capacitr filters, IEEE J. Slid-Stage ircuits, vl. S-5, pp , June 980 [] K. Martin and A. S. Sendra, Effects f pamp finite gain and bandwidth n the perfrmance f switched-capacitr filters, IEEE rans. ircuits Systems, vl. AS-8, pp. 8-89, Aug. 98 [3] K. Nagara, K. Singhal,. R. Viswanathan, and J. Vlach, Reductin f the finite gain effect in switched-capacitr filters, Electrn. Lettt., vl, pp , July 985. [4] Jhns and Martin, Analg Integrated ircuit Design, Jhn Wiley & Sns, Inc., New Yrk, pp 403. [5] A. Baschirtt, nsideratins fr the design f switched-capacitr circuits using precise-gain peratinal amplifiers, IEEE rans. ircuits Syst. II, vl. 43, pp , Dec. 996 [6] K. Nagara,. R. Viswanathan, K. Singhal, and J. Vlach, Switched-apacitr ircuits with reduced Sensitivity t Amplifier Gain, IEEE ransactins n ircuits and Systems, VOL. AS-34, N 5, May 987. [7] P.M. Aziz,.V. Srensen, and J.V.D. Spiegel, An Overview f Sigma-Delta nverters, IEEE Signal Prcessing Magazine, pp 6-84, January 996. [8] B.E. Bser, B.A. Wley, he Design f Sigma-Delta Mdulatin Analg-t- Digital nverters, IEEE Jurnal f Slid State ircuits, vl. 3, NO 6, pp , December 988