CM5530 GENERAL DESCRIPTION APPLICATIONS TYPICAL APPLICATION CIRCU. Rev.1.0 0

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1 FEATURES Quasi-Resnant Primary Side Regulatin (QR-PSR) Cntrl with High Efficiency Multi-Mde PSR Cntrl Fast Dynamic Respnse Built-in Dynamic Base Drive Audi Nise Free Operatin ±4% CC and C Regulatin Lw Standby Pwer <70mW Prgrammable Cable Drp Cmpensatin (CDC) in C Mde Built-in AC Line & Lad CC Cmpensatin Build in Prtectins: Shrt Lad Prtectin (SLP) Cycle-by-Cycle Current Limiting Leading Edge Blanking (LEB) Pin Flating Prtectin DD OP & UP & Clamp Over temperature prtectin(otp) Available with CM5530 ersins in DIP -8 Package GENERAL DESCRIPTION CM5530 is a high perfrmance Quasi Resnant (QR) Primary Side Regulatin (PSR) PWM pwer switch with high precisin C/CC cntrl ideal fr charger applicatins. In C mde, CM5530 adpts Multi Mde QR Cntrl which uses the hybrid f AM (Amplitude Mdulatin) mde and (Frequency Mdulatin) FM mde t imprve system efficiency and reliability. In CC mde, the IC uses PFM cntrl with line and lad CC cmpensatin. The IC can achieve fast dynamic respnse. The built-in Cable Drp Cmpensatin (CDC) functin can prvide excellent C perfrmance. CM5530 integrates functins and prtectins f Under ltage Lckut (ULO), DD ver ltage Prtectin (DD OP), Cycle-by-cycle Current Limiting (OCP), Shrt Lad Prtectin (SLP), On- Chip Thermal Shutdwn, DD Clamping, etc. APPLICATIONS Battery Chargers fr Cellular Phnes AC/DC Pwer Adapter and LED Lightings TYPICAL APPLICATION CIRCU

2 Pin Cnfiguratin Marking Infrmatin CM5530 fr prduct name; The first tw X reresents the last year,2016 is 16; The third and furth X represents the mnth, in A-L 12 letters; The last tw X n behalf f the date, said. Pin Descriptin (CM5530) Pin Pin I/O Number Name Descriptin 1 DD I Pwer Supply Pin f the Chip. 2 NC I Empty 3 FB I System feedback pin which regulates bth the utput vltage in C mde and utput current in CC mde based n the flyback vltage f the auxiliary winding. 4 CS I Current sense input. 5,6 DR O The Pwer BJT Cllectr 7,8 GND P The Grund f the IC

3 Blck Diagram

4 CM5530 Abslute Maximum Ratings (Nte 1) Parameter alue Unit t t t t ma ma C/W C C C C k Parameter alue Unit Supply ltage, DD 7 t 24 H PIN Maximum ltage H PIN DC DD DC Supply ltage DD DC Clamp Current CS, BASE vltage range FB vltage range R JA ( /W) (SOP7) Maximum Junctin Temperature Operating Temperature Range Strage Temperature Range Lead Temperature (Sldering, 10sec.) ESD Capability, HBM (Human Bdy Mdel) ESD Capability, MM (Machine Mdel) Recmmended Operatin Cnditins (Nte 2) Operating Ambient Temperature -40 t 85 C Maximum Switching Full Lading 70 khz Minimum Switching Full Lading 35 khz ELECTRICAL CHARACTERISTICS (TA = 25OC, DD=20, if nt therwise nted) Symbl Parameter Test Cnditins Min Typ. Max Unit 3 20 ua Supply ltage Sectin(DD Pin) IDD_st Start-up current int DD pin IDD_Op Operatin Current ma Standby Current ma IDD_standby DD_ON DD Under ltage Lckut Exit DD_OFF DD Under ltage Lckut Enter DD_OP DD OP Threshld DD_Clamp DD Zener Clamp ltage I(DD ) = 7 ma Cntrl Functin Sectin (FB Pin) Rev.1.0 0

5 FBREF Internal Errr Amplifier (EA) Reference Input FB_SLP Shrt Lad Prtectin (SLP) Threshld 0.65 TFB_Shrt Shrt Lad Prtectin (SLP) Debunce Time (Nte 3) 36 ms FB_DEM Demagnetizatin Cmparatr Threshld 25 m Tff_min Minimum OFF time (Nte 3) 2 us Tn_max Maximum ON time (Nte 3) 20 us Tff_max Maximum OFF time 5 ms ICable_max TSW /TDEM Maximum Cable Drp Cmpensatin(CDC) Current Rati between Switching Perid and Demagnetizatin Time in CC Mde 60 ua 7/4 Current Sense Input Sectin (CS Pin) T LEB CS Input Leading Edge Blanking Time 500 ns cs(max) Current limiting threshld m TD_OC Over Current Detectin and Cntrl Delay 100 ns On-Chip Thermal Shutdwn T SD Thermal Shutdwn (Nte 3) C T RC Thermal Recvery (Nte 3) C BJT Sectin (H Pin) CEO Cllectr-Emitter vltage 480 CBO Cllectr-Base vltage 800 Nte1. Stresses listed as the abve "Maximum Ratings" may cause permanent damage t the device. These are fr stress ratings. Functinal peratin f the device at these r any ther cnditins beynd thse indicated in the peratinal sectins f the specificatins is nt implied. Expsure t maximum rating cnditins fr extended perids may remain pssibility t affect device reliability. Nte2. The device is nt guaranteed t functin utside its perating cnditins. Nte3. Guaranteed by the Design.

6 CHARACTERIZATION PLOTS

7 PERATION DESCRIPTION CM5530 is a high perfrmance, multi mde, highly integrated Quasi Resnant Primary Side Regulatin (QR-PSR) pwer switch. The built-in high precisin C/CC cntrl with high level prtectin features makes it suitable fr ffline small pwer cnverter applicatins. System Start-Up Operatin Befre the IC starts t wrk, it cnsumes nly startup current (typically 3uA) which allws a large value startup resistr t be used t minimize the pwer lss and the current flwing thrugh the startup resistr charges the DD hld-up capacitr frm the high vltage DC bus. When DD reaches ULO turn-n vltage f 12 (typical), CM5530 begins switching and the IC peratin current is increased t be 0.8mA (typical). The hld-up capacitr cntinues t supply DD befre the auxiliary winding f the transfrmer takes the cntrl f DD vltage. In Primary Side Regulatin (PSR) cntrl, the utput vltage is sensed n the auxiliary winding during the transfer f transfrmer energy t the secndary. Fig.2 illustrates the timing wavefrm f C sampling signal, demagnetizatin signal (DEM) and quasi-resnant (QR) trigger signal in CM5530. When the C sampling prcess is ver, the internal sample/hld (S&H) circuit captures the errr signal and amplifies it thrugh the internal Errr Amplifier (EA). The utput f EA is sent t the Quasi Resnant PSR C Mdulatr (QR-CM) fr C regulatin. A valley is selected t trigger new PWM cycle by the utput f the QR-CM bck, which is determined by the lad. The internal reference vltage fr EA is trimmed t 2 with high accuracy. Fig.2 Fig.1 Once CM5530 enters very lw frequency FM (Frequency Mdulatin) mde, the perating current is reduced t be 500uA typically, which helps t reduce the standby pwer lss. Quasi Resnant PSR C Mdulatin (QR-CM) During the C sampling prcess, an internal variable current surce is flwing t FB pin fr Cable Drp Cmpensatin (CDC). Thus, there is a step at FB pin in the transfrmer demagnetizatin prcess, as shwn in Fig.2. Fig.2 als illustrates the equatin fr demagnetizatin plateau, where and F is the utput vltage and dide frward vltage; R1 and R2 is the resistr divider cnnected frm the auxiliary winding t FB Pin, Ns and Na are

8 secndary winding and auxiliary winding respectively. When heavy lad cnditin, the Mde Selectr (as shwn in Blck Diagram ) based n EA utput will switch t CC Mde autmatically. PSR Cnstant Current Mdulatin (PSR-CCM) Timing infrmatin at the FB pin and current infrmatin at the CS pin allw accurate regulatin f the secndary average current. The cntrl law dictates that as pwer is increased in C regulatin and appraching CC regulatin the primary peak current is at Ipp(max), as shwn in Fig.3. the IC perates in pulse frequency mdulatin (PFM) mde t cntrl the utput current at any utput vltage at r belw the vltage regulatin target as lng as the auxiliary winding can keep DD abve the ULO turn-ff threshld. In CM5530, the rati between Tdem and Tsw in CC mde is 4/7. Therefre, the average utput current can be expressed as: 2 I CC_OU T ma N 500m 7 Rcs In the equatin abve, N----The turn rati f primary side winding t secndary side winding. Rcs--- the sensing resistr cnnected between the pwer BJT emitter t GND. Multi Mde Cntrl in C Mde T meet the tight requirement f averaged system efficiency and n lad pwer cnsumptin, a hybrid f frequency mdulatin (FM) and amplitude mdulatin (AM) is adpted in CM5530 which is shwn in the Fig 4. Fig.3 Arund the full lad, the system perates in FM mde. When nrmal t light lad cnditins, the IC perates in FM+AM mde t achieve excellent regulatin and high efficiency. When the system is near zer lading, the IC perates in FM again fr standby pwer reductin. In this way, the n-lad cnsumptin can be less than 70mW. Referring t Fig.3 abve, the primary peak current, transfrmer turns rati, secndary demagnetizatin time (Tdem), and switching perid (Tsw) determines the secndary average utput current Iut. Ignring leakage inductance effects, the equatin fr average utput current is shwn in Fig.3. When the average utput current Iut reaches the regulatin reference in the Primary Side Cnstant Current Mdulatr (PSR-CCM) blck,

9 Fig.4 Prgrammable Cable Drp Cmpensatin (CDC) in C Mde In smart phne charger applicatin, the battery is always cnnected t the adapter with a cable wire which can cause several percentages f vltage drp n the actual battery vltage. In CM5530, an ffset vltage is generated at FB pin by an internal current surce (mdulated by CDC blck, as shwn in Fig.5) flwing int the resistr divider. The current is prprtinal t the switching perid, thus, it is inversely prprtinal t the utput pwer Put. Therefre, the drp due the cable lss can be cmpensated. As the lad decreases frm full lading t zer lading, the ffset vltage at FB pin will increase. By adjusting the resistance f R1 and R2 (as shwn in Fig.), the cable lss cmpensatin can be prgrammed. The percentage f maximum cmpensatin is given by (cable) ut Fr example, R1=3K Ω, R2=18K Ω, The percentage f maximum cmpensatin is given by: (cable) ut Icable_max R1//R2 FB_REF 100% 60uA 3K//18K 100% 7.7% 2 Fig.5 Optimized Dynamic Respnse In CM5530, the dynamic respnse perfrmance is ptimized t meet USB charge requirements. On Chip Thermal Shutdwn (OTP) When the IC temperature is ver 155 C, the IC shuts dwn. Only when the IC temperature drps t 140 C, IC will restart. Audi Nise Free Operatin As mentined abve, the multi-mde C cntrl with a hybrid f FM and AM prvides frequency mdulatin. An internal current surce flwing t CS pin realizes CS peak vltage mdulatin. In CM5530, the ptimized cmbinatin f frequency mdulatin and CS peak vltage mdulatin algrithm can prvide audi nise free peratin frm full lading t zer lading. Dynamic BJT Base Drive CM5530 drives a pwer BJT with dynamic base drive cntrl t ptimize efficiency. The BJT base

10 drive current ranges frm 12mA t 35mA (typical), and is dynamically cntrlled accrding t the pwer supply lad change. The higher the utput pwer, the higher the based current. Specifically, the base current is related t CS peak vltage, as shwn in Fig.6 Shrt Lad Prtectin (SLP) In CM5530, the utput is sampled n FB pin and then cmpared with a threshld f UP (0.65 typically) after an internal blanking time (10ms typical). In CM5530, when sensed FB vltage is belw 0.6, the IC will enter int Shrt Lad Prtectin (SLP) mde, in which the IC will enter int aut recvery prtectin mde. DD Over ltage Prtectin (OP) and Zener Clamp Fig.6 When DD vltage is higher than 26.5 (typical), the IC will stp switching. This will cause DD fall dwn t be lwer than DD_OFF (typical 6.5) and then the system will restart up again. An internal 28 (typical) zener clamp is integrated t prevent the IC frm damage.

11 Package Dimensin

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