A Novel Structure for CCII Based SC Integrator Based on CCII with Reduced Number of Switches

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1 J. Basic. Appl. Sci. Res., (9) , 01 01, TextRad Publicatin ISSN Jurnal f Basic and Applied Scientific Research A Nvel Structure fr CCII Based SC Integratr Based n CCII with Reduced Number f Switches MstafaMridi (1), HmanKaabi (), Mna Prebrahim (3), MaliheKeshavarzi (4) (1), (3), (4) Department f Electrnic Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran () Department f Electrical Engineering, ShahidChamran University f Ahvaz, Ahvaz, Iran ABSTRACT This paper describes a new switched-capacitr (SC) integratr. This integratr nt nly has the advantages f cnventinal pamp based integratrs but als has the capability f switching in high frequency due t inherent characteristics f secnd generatin current cnveyr (CCII). T implement integratr, 7 switches and nnverlapping clck are used. Time shared use f internal CCII buffers is perfrmed t make input utput transfer functin. The circuit is simulated by means f HSPICE and WAVEVIEW t cnfirm theretical results in 0.35µm technlgy. Key Wrds: Integratr, SC Circuit, Current Cnveyr, Lw Pass Sigma Delta Mdulatr (LPSDM), CCII. 1. INTRODUCTION Sigma-Delta Switched-capacitr circuits have been widely used fr implementing mnlithic filters. The lng time interest in the design f SC filters is mtivated by the fact that such filters can be realized using standard CMOS digital prcess technlgies. This is due t availability f high perfrmance pamps as well as high quality MOS capacitrs and switches. An SC building blck that is useful in implementing SC filters is the SC integratr [1]. It can be shwn that (in the ideal frm) the transfer functin f an SC filter depends n switching frequency and the ratis f capacitance values []. These capacitive ratis can be btained and maintained t accuracy much better than 1% ver a wide range f temperatures and f signal amplitudes [3]. Fr these reasns cnsiderable effrt has been directed tward develping high perfrmance circuits and devices fr SC filters. Traditinally pamps have been used in SC integratr realizatin fr mre than three decades [4]-[7]. Als sme little effrts have been dne t design and implement SC integratrs using vltage buffer [8]-[11]. Therefre it is pssible t replace pamps by ther unity-gain devices. Mre recently a current mde building blck named CCII has been intrduced [1]-[13]. It has the advantages f higher speed, slew rate and wider dynamic range f current mde circuits [1]. Althugh CCII had been intrduced in 1971 but synthesis and design methds are nt mature, especially fr the SC circuits realizatins. It seems there is very little cncern abut CCII based SC circuits in the literature. Due t the inherent high frequency capability f CCII building blck [1] it is an attractive candidate fr replacing pamps in the integratr circuits. Furthermre, CCII des nt need external feedback and hence n stability prblem [13]. Fr the first time Maundy and his clleagues have shwn that it is pssible t realize SC circuits using CCIIs withut requiring circuit transfrmatin [14]-[15]. They emplyed miller therem t replace feedback capacitr C in an SC pamp based integratr by a grunded capacitr f equal value cnnected t the Z terminal f CCII. Fig. 1 shws this prcess. In a recent effrt, sme ther CCII based SC integratrs have been prpsed [16]. As it is shwn in Fig., these wrks were based n realizatin f RC prttypes with required characteristics and transfrmatin f the resulted circuits t their SC equivalents [17]. *Crrespnding Authr: MstafaMridi, Department f Electrnic Engineering, Qazvin Branch, Islamic Azad University, Qazvin, Iran. m.mridi@qiau.ac.ir 9758

2 MridiandKaabi et al., 01 Fig. 1 The derivatin f SC CCII integratr by Millers therem. Fig. An integratr with Realizatin f RC prttype with their SC equivalent. Fig. 3 The CCII based SC integratr by eliminating extra vltage buffer. A cmmn drawback in these wrks was the need fr the vltage buffer at the utput f the circuits t cancel the lading effects f the next stages. This led t use f an extra vltage buffer in additin t the CCII (see Fig. 1d). Thus it seems that nt a pure CCII based circuit is realized. In a mre recent wrk a nvel structure has been prpsed which eliminates the need fr extra vltage buffer [18]. This integratr fllwed by clck pulse scheme is shwn in Fig. 3. It is based n time shared use f internal buffers f CCII. 9759

3 J. Basic. Appl. Sci. Res., (9) , 01 All these effrts t realize integratr by CCII are based n varius tplgies including: 1) input signal is cnnected t Y and utput is cnnected t Z [16], ) input signal is cnnected t X and utput is cnnected t Z [16] and finally 3) input and utput are cnnected t X [18]-[19]. This paper prpses a nvel architecture using Y terminal as input and X terminal as utput [0]. The prpsed integratr has the all advantages f previus CCII based integratrs. It seems t be less nisy in cmpare t [18], because f reduced number f switches [1].. PROPOSED INTEGRATOR The circuit fllwed by its clck pulse is shwn in Fig. 4 [0]. T realize integratr, time sharing f internal CCII current and vltage buffers are used. In the fllwing frmulas, and e indices are the symbls fr dd phases (φ1) and even phases (φ), respectively [1]. Assume that the time f charge and discharge f capacitrs are insignificant cmpared t clck pulse perids. Fig. 4 The prpsed integratr fllwed by clck pulse scheme[0]. Hence ne can results that the charge n C in n-3/ (immediately after shutting ff the φ, ignring nn verlapped time) is equals t the charge which is stred n utput (X terminal) at n-1 (immediately befre shutting ff the φ1 r pening the φ, ignring nn verlapped time). Besides, there is n change in utput after shut ff the φ1, s it can be shwn that: 3 e 3 ( n ) T t ( n 1) T : C V n 1 Q ( n ) ut C (1) During dd phases (see Fig. 5a), input signal is cnnected t Y terminal s that its vltage will be transferred t X terminal thrugh internal vltage buffer f CCII. Therefre the charge stred n C1 becmes: 1 ( n 1) T t ( n ) T : Q n C V n 1 C in () (a) (b) Fig. 5 The prpsed integratr at a) phase φ1 and b) phase φ At the same time, sampling and integrating capacitrs are cnnected t X and Z terminals, respectively. The charge stred n C1 is transferred t C via internal current buffer f CCII. At the next phase (see Fig. 5b) integratin capacitr is cnnected t Y terminal and transfers the charge stred f previus phase via internal vltage buffer f CCII: 1 e 1 e 1 ( n ) T t nt : CVut ( n ) QC ( n ) (3) 9760

4 MridiandKaabi et al., 01 It is wrth t mentin that in this phase, the Z terminal is tied t grund t prevent the Cz parasitic capacitance being charged. It is assumed that the Y terminal has n significant effect n C hence desn t perturb its charge while cnnected t Y terminal. Thus the charge stred n C transfers t utput. Based n this cncept, C hlds the charge f tw preceding pulses: e 1 e 3 QC ( n ) QC1 n 1 QC ( n ) (4) Substituting (1) and () int (4) and put the result int (3), results in: e 1 CVut ( n ) C1V in n 1 CVut n 1 (5) As was mentined befre, it is assumed that the charge during each phase remains unchanged thus there is n change in utput after shut ff the φ 1, s it can be written that: 1 e 1 nt t ( n ) T : Vut n Vut ( n ) (6) Substituting (6) in (5), the integratr s input-utput relatinship will be btained in time dmain. It is shwn in (7). n C V n C V n 1 Vut 1 in 1 ut (7) C Arranging (7) and then using f Z transfrm, the transfer functin f integratr will be prved, which is shwn in (8). 1 z C1 Z 1 z C 1 Z Vut H z Vin The ±sign is due t use CCII- and CCII+, respectively. 3. SIMULATION RESULTS The simulatin was dne fr the prpsed integratr based n a CCII- [1] which is shwn in Fig. 6. This CCII- is simulated in 0.35µm technlgy []. (8) Fig. 6 The circuit f CCII-. The curves f vltage and current buffers f CCII- are shwn in Fig. 7 and 8, respectively. One can results that the errrs frm the ideal gains fr vltage and current are less that 0.5% and 1.8%, respectively, ver a frequency range frm 0 t 10MHz. Therefre the gains are s clse t

5 J. Basic. Appl. Sci. Res., (9) , 01 Fig. 7 The vltage gain f the vltage buffer f CCII-. Fig. 8 The current gain f the current buffer f CCII-. Vltage cntrlled resistrs were used t mdel switches. The amplitude and the frequency f input signal were 0.9 V and 1 MHz, respectively. The sampling frequency was 10 MHz. The was dne by means f HSPICE. The input-utput signals f the integratr are shwn in Fig. 9. The dtted line is input and the slid line is utput. The utput has 90 degree delay with the input signal which dentes the integrating prcess f the integratr. Fig. 9The input-utput signals f the prpsed integratr. 976

6 MridiandKaabi et al., CONCOLUSION A nvel CCII based SC integratr is prpsed. The analysis f the circuit is carried ut. It seems t have similar equatins as traditinal pamp based integratrs. The number f switches is minimized. REFERENCES [1] Allen,P. E. and D. R. Hlberg, 00. CMOS Analg Circuit Design, nd editin. Oxfrd University Press. [] Gregrian, R., K. W. Martin and G. Temes, Aug Switched-Capacitr Circuit Design. IEEE Prc., Vl. 71, N. 8, pp [3] Hastings, A.,001. The Art f Analg Layut. New Jersy, Printice-Hall Inc. [4] Baher, H. and S. O. Scanlan, Apr Exact Synthesis f Band-Pass Switched Capacitr Filters. IEEE Transactins n Circuits and Systems, CAS-31, N. 4, pp [5]Gbet, C. A. and A. Knb, Jan Nise Analysis f Switched Capacitr Netwrks. IEEE Transactins n Circuits and Systems, CAS-30, N. 1, pp [6] Castel, R. and P. R. Gray, Sep Perfrmance Limitatins in Switched-Capacitr Filters. IEEE Transactins n Circuits and Systems, CAS-3, N. 9, pp [7]Temes, G. C., H. J. Orchard and M. Jahanbegl, Dec Switched-Capacitr Filter Design Using the Bilinear z-transfrm. IEEE Transactins n Circuits and Systems, CAS-5, N. 1, pp [8] Wu, P. K., Unit-Gain Buffer Switched-Capacitr Filters-Design Techniques and Circuit Analysis. Ph.D. Thesis, University f Califrnia, Ls Angeles. [9]Y, K., 004. Op-Amp Free SC Biquad LPF and Delta-Sigma ADC. M.Sc. Thesis, University f Oregn. [10]Beruneau, D., 00. High-Speed Switched-Capacitr Filters Based n Unity-Gain Buffers. MSc. Thesis, University f Oregn. [11]Fan, S. C., R. Gregrian, G. C. Temes and M. Zmrrdi, Switched-capacitr filters using unit-gain buffers. Prc. IEEE Internatinal Sympsium n Circuits and Systems, pp [1] Sedra, A., K. C. Smith, A Secnd Generatin Current Cnveyr and its Applicatins. IEEE Trans. Circuits and Systems, CT-17, pp [13]Wilsn, B., Recent Develpments in Current Cnveyrs and Current Mde Circuits. IEE Prc., Pt. G, Vl. 137, N., pp [14]Maundy, B. J., P. B. Arnhime, E. I. Elmasry, Aug Switched-capacitr filters: the current mde apprach. IEEE Prceedings f the 38th Midwest Sympsium n Circuits and Systems, Vl., pp [15]Maundy, B. J., P. B. Arnhime, May Switched-capacitr current cnveyr building blcks. IEEE ISCAS 1996, Vl. 1, pp [16] Tutyshkin, A. A., A. S. Krtkv, 00. Current cnveyr based switched-capacitr integratr with reduced parasitic sensitivity. IEEE ICCSC 00,.pp [17] Krtkv, A. S., A. A. Tutyshkin, 001. Tplgical analysis f cntinuus and discrete-time current cnveyr based circuits. in Prc. Int. Symp. SCS'01, Iasi, Rmania, pp [18] Kaabi, H., A. Ayatllahi and M. R. JahedMtlagh, May 005. A Nvel Current-Cnveyr Based Switched- Capacitr Integratr. Prceedings f IEEE ISCAC 005, pp , Kbe, Japan. [19] Kaabi, H Design f Current Cnveyr Based SC ΣΔ Mdulatrs. Ph.D. Thesis in Persian, Iran University f Science and Technlgy, Tehran, Iran. [0]Mridi, M. 01. Design f Current Cnveyr Based SC Resnatrs.M.Sc. Thesis in Persian, Islamic Azad University, Qazvin Branch, Qazvin, Iran. [1] Michal, V., G. Klisnick, G. Su, M. Redn and J. Sedláček, June 010. Current Cnveyr with Very Lw Output Impedance Vltage Buffer fr Labratry Instrumentatin. Prceedings f 010 IEEE Int. Sympsium n Circuits and Systems (ISCAS), pp [] Maheshwari, S., J. Mhan and D. S. Chauhan, 010. Vltage-mde cascadable all-pass sectins with tw grunded passive cmpnents and ne active element. IET Circuits, Devices and Syst., Vl. 4, ISS.,pp