Design and Implematation of 32-BIT MAC Unit Using Vedic Multiplier and Reversible Logic Gate

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1 Design and Implematatin f 32-BIT MAC Unit Using Vedic Multiplier and Reversible Lgic Gate 1 Achyuth Reddy Dma & 2 M.Harinath Reddy 1 M.Tech student, Dept. f ECE, Sphrthy Engineering Cllege,Hyderabad,Telangana, India 2 Assistant Prfessr Dept. f ECE, Sphrthy Engineering Cllege,Hyderabad,Telangana, India ABSTRACT: A Vedic multiplier is cmpsed by utilizing Urdhava Triyagbhayam sutra and the viper utline is finished by utilizing reversible ratinale dr. Reversible ratinales are likewise the majr prerequisite fr the develping field f Quantum prcessing. The Vedic multiplier is utilized fr the increase unit in rder t lessen incmplete items and t get leading and smaller range.the reversible ratinale is utilized t get less pwer. The MAC is utlined in Verilg HDL and the reprductin is dne in Mdelsim, Xilinx 14.2 and blend is finished in bth RTL cmpiler utilizing rhythm and als Xilinx. The chip utline fr the prpsed MAC is additinally dne. KEYWORDS- MAC, Reversible lgic, Urdhava Triyagbhayam I. INTRODUCTION Vedic mathematics is the ancient Indian system f mathematics which mainly deals with Vedic mathematical frmulae and their applicatin t varius branches f mathematics. The wrd 'Vedic' is derived frm the wrd 'Veda' which means the stre-huse f all knwledge. Vedic mathematics was recnstructed frm the ancient Indian scriptures (Vedas) by Sri Bharati Krishna Tirthaji ( ), after his eight years f research n Vedas. Accrding t his research, Vedic mathematics is mainly based n sixteen principles r wrd-frmulae which are termed as Sutras. This is a very interesting field and presents sme effective algrithms which can be applied t varius branches f Engineering such as Cmputing and Digital Signal Prcessing. In the accumulate adder the previus MAC utput and the present utput will added and it cnsists f Multiplier unit, ne adder unit and bth will get be cmbined by an accumulate unit. The majr applicatins f Multiply-accumulate (MAC) unit are micrprcessrs, lgic units and digital signal prcessrs, since it determines the speed f the verall system. The efficient designs by MAC unit are Nnlinear Cmputatin like Discrete Csine r wavelet Transfrm (DCT), FFT/IFFT. Since, they are basically executed by insistent applicatin f multiplicatin and additin, the entire speed and perfrmance can be cmpute by the speed f the additin and multiplicatin taking place in the system. Generally the delay, mainly critical delay, happens due t the lng multiplicatin prcess and the prpagatin delay is bserved because f parallel adders in the additin stage. The 32 bit Mac design by using Vedic multiplier and reversible lgic gate can be dne in tw parts. First, multiplier unit, where a cnventinal multiplier is replaced by Vedic multiplier using Urdhava Triyagbhayam sutra. Multiplicatin is the fundamental peratin f MAC unit. Pwer cnsumptin, dissipatin, area, speed and latency are the majr issues in the multiplier unit. S, t avid them, we g fr fast multipliers in varius applicatins f DSP, netwrking, etc. There are tw majr criterins that imprve the speed f the MAC units are reducing the partial prducts and because f that accumulatr burden is getting reduced. The basic peratinal blcks in digital system in which the multiplier determines the critical path and the delay. The (lg2n + 1) partial prducts are prduced by 2N-1 crss prducts f different widths fr N*N. The partial prducts are generated by Urdhava sutra is by Criss Crss Methd. The maximum number f bits in partial prducts will lead t Critical path. The secnd part f MAC is Reversible lgic gate. In mdern Available nline: P a g e 2506

2 VLSI, fast switching f signals leads t mre pwer dissipatin. Lss f every bit f infrmatin in the cmputatins that are nt reversible is kt*lg2 jules f heat energy are generated, where k is Bltzmann s cnstant and T the abslute temperature at which cmputatin is perfrmed. In recent years, reversible lgic functins has emerged and played a vital rle in several fields such as Optical, Nan, Cryptgraphy, etc. The main idea f this paper is t btain less pwer, area, speed f MAC unit using Vedic mathematics with reversible lgic gate. II. URDHAVA MULTIPLIER In Urdhava Tiryakbhyam is a Sanskrit wrd which means vertically and crsswire in English. The methd is a general multiplicatin frmula applicable t all cases f multiplicatin. It is based n a nvel cncept thrugh which all partial prducts are generated cncurrently. Fig. Demnstrates a 4 x 4 binary multiplicatin using this methd. The methd can be generalized fr any N x N bit multiplicatin. This type f multiplier is independent f the clck frequency f the prcessr because the partial prducts and their sums are calculated in parallel. The net advantage is that it reduces the need f micrprcessrs t perate at increasingly higher clck frequencies. As the perating frequency f a prcessr increases the number f switching instances als increases. This results mre pwer cnsumptin and als dissipatin in the frm f heat which results in higher device perating temperatures. Anther advantage f Urdhava Tiryakbhyam multiplier is its scalability T. Fig. 1 Line Diagram fr Urdhava Multiplicatin The prcessing pwer can easily be increased by increasing the input and utput data bus widths since it has a regular structure. Due t its regular structure, it can be easily layut in a silicn chip and als cnsumes ptimum area. As the number f input bits increase, gate delay and area increase very slwly as cmpared t ther multipliers. Therefre Urdhava Tiryakbhyam multiplier is time, space and pwer efficient. Fig. 2 Multiplicatin f tw 4 bit Numbers using Urdhava Tiryakbhyam Methd Example 3: Fr the Multiplicatin f tw 4 bit Numbers using Urdhava Tiryakbhyam Methd The line diagram in fig. 3 illustrates the algrithm fr multiplying tw 4-bit binary numbers a3, a2, a1, a0 and b3, b2, b1, b0. The prcedure is divided int 7 steps and each step generates partial prducts. Initially as shwn in step 1 f fig. 2, the least significant bit (LSB) f the multiplier is multiplied with least significant bit f the multiplicand (vertical multiplicatin). This result frms the LSB f the prduct. In step 2 next higher bit f the multiplier is multiplied with the LSB f the multiplicand and the LSB f the multiplier is multiplied with the next higher bit f the multiplicand (crsswire multiplicatin). These tw partial prducts are added and the LSB f the sum is the next higher bit f the final prduct and the remaining bits are carried t the next step. Fr example, if in sme intermediate step, we get the result as 1101, then 1 will act as the result bit (referred as rn) and 110 as the carry (referred as cn). Therefre cn may be a multibit number. Similarly ther steps are carried ut as indicated by the line diagram. The imprtant feature is that all the partial prducts and their sums fr every step can be calculated in parallel. Thus every step in fig. 3.1 has a crrespnding expressin as fllws: Available nline: P a g e 2507

3 r0=a0b0 (1) c1r1=a1b0+a0b1 (2) c2r2=c1+a2b0+a1b1 + a0b2 (3) c3r3=c2+a3b0+a2b1 + a1b2 + a0b3. (4) c4r4=c3+a3b1+a2b2 + a1b3. (5) c5r5=c4+a3b2+a2b3. (6) c6r6=c5+a3b3 (7) With c6r6r5r4r3r2r1r0 being the final prduct. Hence this is the general mathematical frmula applicable t all cases f multiplicatin and its hardware architecture is shwn in fig. 3. In rder t multiply tw 8-bit numbers using 4-bit multiplier we prceed as fllws. Cnsider tw 8 bit numbers dented as AHAL and BHBL where AH and BH crrespnds t the mst significant 4 bits, AL and BL are the least significant 4 bits f an 8-bit number. When the numbers are multiplied multiplied accrding t Urdhava Tiryakbhyam (vertically and crsswire) methd, we get, AH BH AL BL (AH x BH) + (AH x BL + BH x AL) + (AL x BL). The digits n the tw ends f the line are multiplied and the result is added with the previus carry. When there are mre lines in ne step, all the results are added t the previus carry. III. THE PROPOSED APPROACH The design f MAC architecture cnsists f 3 sub designs. Design f bit Vedic multiplier. Design f adder using DKG gate reversible lgic. Design f accumulatr which integrates bth multiplier and adder stages. Fig. 3 Mdified MAC Architecture A. Urdhava Triyagbhayam Sutra It literally means Vertically and crsswise. Shift peratin is nt necessary because the partial prduct calculatin will perfrm it in a single step, which in turn saves time and pwer. This is the main advantage f the Vedic multiplier Urdhva Triyagbhayam is the general frmula applicable t all cases f multiplicatin and als in the divisin f a large number by anther large number. It is ne f Sixteen Vedic Sutras and deals with the multiplicatin f numbers. B. Kgge-Stne adder It s a parallel prefix adder, which is the ne f the fastest adder. Carry stages: lg2 n; the number f cells: n (lg2n-1) +1; Maximum fan-ut: 2 (extra wiring). S, it will reduce the pwer cnsumptin as well as the pwer dissipatin. The Kgge-Stne adder is a parallel prefix frm f carry lk-ahead adder. It generates the carry signals in O (lg2n) time, and is widely cnsidered as the fastest adder design pssible. It is the mst cmmn architecture fr high-perfrmance adders in industry. The fllwing fig shws the design f a Vedic multiplier using an Vedic multiplier and with kgge stne adder the design can be implemented using Verilg HDL. Available nline: P a g e 2508

4 Lps r feedbacks are nt permitted Garbage utputs must be Minimum¾ Minimum delay Minimum quantum cst Zer energy dissipatin B. DKG Gate Fig.4 32x 32 MAC unit with kgge stne adder design C. Accumulatr Stage Accumulatr has an imprtant rle in the DSP applicatins in varius ranges and is a very basic and cmmn methd. The register designed in the accumulatr is used t add the multiplied numbers. Multiplier, adder and an accumulatr are frming the essential fundatin fr the MAC unit. The cnventinal MAC unit has a multiplier and multiplicand t d the basic multiplicatin and sme parallel adders t add the partial prducts generated in the previus step. T get the final multiplicatin utput we add the partial prduct t these results. Vedic Multiplier has put frward t intensify the actin f the MAC Unit. A 4*4 reversible DKG gate [6] that can wrk singly as a reversible full adder and a reversible full subtractr is shwn belw. If input A=0, the DKG gate wrks as a reversible Full adder, and if input A=1 then it wrks as a reversible Full subtractr. It has been verified that a reversible full-adder circuit requires at least tw r three garbage utputs t make the utput cmbinatins unique [5], [6]. Fig. 5a [6] DKG gate IV. DESIGN OF ADDER USING REVERSIBLE LOGIC DKG GATE A. Reversible lgic Reversible lgic is a unique technique (different frm ther lgic). Lss f infrmatin is nt pssible in here. In this, the numbers f utputs are equal t the number f inputs. General cnsideratin fr reversible lgic gate: A Blean functin is reversible if each value in the input set can be mapped with a unique value in the utput set. Landauer prved that the usage f traditinal irreversible circuits leads t pwer dissipatin and Bennet shwed that a circuit cnsisting f nly reversible gates des nt dissipate pwer. In the design f reversible lgic circuits, the fllwing pints must be kept in mind t achieve an ptimized circuit: 5b DKG gate as a Full adder Fig. 5c Parallel adder using DKG gate Fig. Fan-ut is nt permitted Available nline: P a g e 2509

5 IV. RESULT AND DISCUSSION The design f 32 bit MAC with kgge stne adder is dne in Mdelsim. The abve design is implemented in Verilg Cde using mentr graphics mdelsim and Xillinx building blcks and its perfrmance has been analyzed fr all the blcks. Therefre, we can say that the Urdhava Triyagbhayam sutra with 32-bit Multiplier and reversible lgic is the best in all aspects like speed, delay, area and cmplexity Thus the prpsed MAC prvides higher perfrmance, less area, less pwer dissipatin fr higher rder bit multiplicatin and it als presents a highly efficient methd f multiplicatin Urdhva Tiryakbhyam Sutra based n Vedic mathematics. Reversible lgic gates are used t btain the less pwer. It s mre efficient design cmpare t pervius design. REFERENCES Fig. 6 Blck diagram f MAC [1] Vaijyanath Kunchigi,Linganaguda Kulkarni, Subhash Kulkarni 32-bit MAC unit design using Vedic multiplier Internatinal Jurnal f Scientific and Research Publicatins, Vlume3, Issue 2, February 2013 [2] Ramalatha, M.Dayalan, K D Dharani, P Priya, and S Debrah, High Speed Energy Efficient ALU design using Vedic multiplicatin techniques, Internatinal Cnference n Advances in Cmputatinal Tls fr Engineering Applicatins, ACTEA 09.pp , Jul 15-17, [3] Sree Nivas A and Kayalvizhi N. Article: Implementatin f Pwer Efficient Vedic Multiplier. Internatinal Jurnal f Cmputer Applicatins 43(16):21-24, April Published by Fundatin f Cmputer Science, New Yrk, USA Fig. 7 RTL Schematic f 32x32 MAC unit [4] Vaijyanath Kunchigi, Linganaguda Kulkarni, Subhash Kulkarni, High Speed and Area Efficient Vedic Multiplier, Internatinal Cnference n Devices, Circuitsand Systems (ICDCS), [5] D.P.Vasudevan, P.K.Lala, J.Di and J.P.Parkersn, Reversiblelgic design with nline testability, IEEE Trans. On Instrumentatin and Measurement, vl.55., n.2, pp , April [6] Raghava Garipelly, P.Madhu Kiran, A.Santhsh Kumar A Review n Reversible Lgic Gates and their Implementatin Internatinal Jurnal f Emerging Technlgy and Advanced nengineering Website: (ISSN , ISO 9001:2008 Certified Jurnal, Vlume 3, Issue 3, March Fig. 8 Simulatin utput 32x32 MAC unit V. CONCLUSION The results btained by the design f Vedic multiplier with 32 bits and reversible lgic are quite gd. The wrk presented is based n 32 bit MAC unit with Vedic Multipliers. We have designed MAC unit basic [7] Wikipedia.rg/ mac design [8] Prabir Saha, Arindam Banerjee, Partha Bhattacharyya, Anup Dandapat, High Speed ASIC Design f Cmplex Multiplier Using Vedic Mathematics, Prceeding f the 2011 IEEE Students' Technlgy Sympsium January, 2011, IIT Kharagpur. [9] Asmita Haveliya, A Nvel Design fr High Speed Multiplier fr Digital Signal Prcessing Applicatins (Ancient Indian Vedic mathematics apprach), Internatinal Jurnal f Technlgy and Engineering System (IJTES), Vl.2, N.1, Jan -March, Available nline: P a g e 2510

6 [10] Aniruddha Kanhe, Shishir Kumar Das and Ankit Kumar Singh, Design and Implementatin f Lw Pwer Multiplier Using Vedic Multiplicatin Technique, (IJCSC) Internatinal Jurnal f Cmputer Science and Cmmunicatin Vl. 3, N. 1, JanuaryJune 2012, pp Internatinal Jurnal f Scientific and Research Publicatins, Vlume 3, Issue 2, February 2013 ISSN [11] / vedic.htm# Vedic Mathematics. BiData Authr Achyuth Reddy Dma currently pursuing M.Tech in Electrnics and Cmmunicatin Engineering in Dept. f ECE, Sphrthy Engineering Cllege, Hyderabad, Telangana, India. C-Authr M.Harinath Reddy is currently an Asst. Prf. in the Dept. f ECE, Sphrthy Engineering Cllege, Hyderabad, TS, India. Prir t his recent appintment at the SEC-HYD, he was a lecturer in G.Pulla Reddy Engineering Cllege, Kurnl. He has received his UG degree as well as his Masters Degree frm JNTUA, Anantapuramu in the the year He has published 4 papers in Referred Internatinal Jurnals and has als participated in 7 Natinal Level Wrkshps. He als presented 2 natinal and in an internatinal cnferences. Available nline: P a g e 2511