CSEN 601: Computer System Architecture Summer 2014

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1 CSEN 601: Cmputer System Architecture Summer 2014 Practice Assignment 7 Slutin Exercise 7-1: Based n the MIPS pipeline implementatin yu studied, what are the cntrl signals that have t be stred in the ID/EX pipeline register? Grup them based n the stage they are needed in. Slutin: Cntrl signals needed in the EX phase: ALUSrc (1- bit), RegDest (1- bit), ALUOp (2- bits) Cntrl signals needed in the MEM phase: MemRead (1- bit), MemWrite (1- bit), Branch (1- bit) Cntrl signals needed in the WB phase: RegWrite (1- bit), MemTReg (1- bit) Exercise 7-2: Based n the MIPS pipeline implementatin yu studied, what are the sizes f the pipeline registers? Justify yur answer. Ignre any bits required t detect r handle hazards. Slutin: The IF/ID pipeline register has: 64- bits 32- bits instructin 32- bits incremented PC The ID/EX pipeline register has: 147- bits 32- bits incremented PC 32- bits read register 1 value 32- bits read register 2 value 32- bits sign extended ffset 5- bits Rt field 5- bits Rd field 2- bits WB cntrl signals 3- bits MEM cntrl signals 4- bits EX cntrl signals The EX/MEM pipeline register has: 107- bits 32- bits branch address 1- bit zer flag 32- bits ALU result/address 32- bits register value t write t memry 5- bits Rd field (writereg) 2- bits WB cntrl signals 3- bits MEM cntrl signals The MEM/WB pipeline register has: 71- bits 1

2 32- bits ALU result 32- bits memry wrd read 5- bits Rd field (writereg) 2- bits WB cntrl signals Exercise 7-3: Fr the fllwing sequences f instructins: 1. lw $1, 40($6) beq $2, $0, Label Assume $2 == $0 sw $6, 50($2) Label: add $2, $3, $4 sw $3, 50($4) 2. lw $5, - 16($5) sw $4, - 16($4) lw $3, - 20($4) beq $2, $0, Label Assume $2!= $0 add $5, $1, $4 Assuming the fllwing latencies fr the individual pipeline stages: ps 120ps 90ps 130ps 60ps ps 100ps 170ps 220ps 60ps a. Assume that all branches are perfectly predicted (eliminating cntrl hazards) If we have nly ne memry (fr bth instructins and data), there is a structural hazard every time we need t fetch an instructin in the same cycle in which anther instructin accesses data. T guarantee frward prgress, this hazard must always be reslved in favr f the instructin that accesses data. What is the ttal executin time f this instructin sequence in the five- stage pipeline that nly has ne memry? Data hazards can be eliminated by adding nps t the cde. Can structural hazard be eliminated in the same way? Why? 2

3 b. Assume that all branches are perfectly predicted (eliminating cntrl hazards) If we change lad/stre instructins t use a register (withut an ffset) as the address, these instructins n lnger need t use the ALU. As a result, MEM and EX stages can be verlapped and the pipeline has nly fur stages. Change this cde t accmmdate this changed ISA. Assuming this change desn t affect clck cycle time, what speed- up is achieved this instructin sequence? c. Repeat the speed- up calculatin f part b, but take int accunt the pssible change in clck cycle time and the prvided pipeline stage latencies. When EX and MEM are dne in a single stage, mst f their wrk can be dne in parallel. As a result, EX/MEM stage has a latency that is larger f the riginal tw plus 20ps needed fr the wrk that culdn t be dne in parallel. d. Assuming stall- n- branch, what speed- up is achieved n this cde if branch utcmes are determined in the ID stage, relative t the executin where branch utcmes are determined in the EX stage? e. Assume the latency ID stage increases by 50% and the latency f the EX stage decreases by 10ps when branch utcme reslutin is mved t ID. Repeat the speed- up calculatin f part d, but take int accunt the pssible change in clck cycle time and the prvided pipeline stage latencies. f. Assume stall- n- branch, what is the new clck cycle time and executin time f this instructin sequence if beq address cmputatin is mved t the MEM stage? What is the speed- up in this case? Assume that the latency f the EX stage is reduced by 20ps and the latency f the MEM stage remains unchanged. 3

4 Slutin: a. Perfect branch predictin leads t n stalls. In the pipelined executin, *** represents a stall when an instructin can t be fetched because a lad r stre instructin is using the memry in that cycle. We can t add nps t eliminate structural hazards as nps need t be fetched just like any ther instructins, s this hazard must be addressed with a hardware hazard detectin unit in the prcessr. Instructins Pipeline stage Cycles 1. lw $1, 40($6) beq $2, $0, Label 9 add $2, $3, $4 sw $3, 50($4) *** 2. lw $5, - 16($5) sw $4, - 16($4) 12 lw $3, - 20($4) beq $2, $0, Label *** *** *** add $5, $1, $4 b. This change nly saves ne cycle in an entire executin withut data hazards. If there were data hazards frm lads t ther instructins, the change wuld help eliminate sme stall cycles. Instructins Cycles with 5 stages Cycles with 4 Speed- up executed stages = = 7 8/7 = = = 8 9/8 = 1.13 c. The clck cycle time is equal t the latency f the lngest- latency stage. Cmbining EX and MEM stages affect clck time nly if the cmbined EX/MEM stage becmes the lngest- latency. Cycles time with Cycles time with 4 Speed- up 5 stages stages ps (MEM) 150ps (MEM +20ps) (8*130)/(7*150) = ps (MEM) 240ps (MEM +20ps) (9*220)/(8*240) =

5 d. Stall- n- branch delays the fetch f the next instructin until the branch is executed. When branches execute in the ID stage, each branch cause ne stall nly. e. Instructin Branches Cycles with Cycles with Speed- up executed executed branch in EX branch in ID *2 = *1=9 10/9 = *2 = *1=10 11/10 = 1.1 New ID NEW EX New cycle Old cycle Speed- up latency latency time time ps 80ps 180ps (ID) 130ps (MEM) (10*130)/(9*180) = ps 160ps 220ps (MEM) 220ps (MEM) (11*220)/(10*220) = 1.1 f. The cycle time remains unchanged; a 20ps reductin in EX latency has n effect n clck cycle time because EX is nt the lngest- latency stage. The change affects the executin time because it adds ne additinal stall cycle t each branch, because the clck cycle time desn t imprve but the number f cycles increases. Cycles with branch in EX Executin time (branch in EX) Cycles with branch in MEM Executin time (branch in MEM) Speed- up *2 = 10 10*130 = 1300ps 4+4+1*3 = 11 11*130 = 1430ps *2 = 11 11*220 = 2420ps 4+5+1*3 = 12 12*220 = 2640ps