Implementation of High Speed Signed Multiplier Using Compressor

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1 Implementation of High Speed Signed Multiplier Using Compressor D.Srinu 1, S.Rambabu 2, G.Leenendra Chowdary 3 M.Tech, Dept of ECE, SITE, Tadepalligudem, A.P, India 1 Asst. Professor, Dept of ECE, SITE, Tadepalligudem, A.P, India 2 Asst. Professor, Dept of ECE, SITE, Tadepalligudem, A.P, India 3 ABSTRACT: Multipliers play an important role in today s digital signal processing and various other applicatio. With advances in technology, many researchers have tried and are trying to design multipliers which offer either of the following design targets high speed, low power coumption, regularity of layout and hence less area for compact VLSI implementation. This work is based on one of the ancient Vedic algorithms (sutras) called Urdhava method. These sutras are meant for faster calculation. Though faster when implemented in hardware, it coumes less area. This paper presents a technique to modify the architecture of the Urdhava Tiryakbhyam hardware by using 3_2compressor in order to reduce area and delay to improve overall performance. The coding is done for 16 bit (Q15format), 32 bit (Q31format) and 64 bit (Q63 format) fixed point Q-format by using Verilog HDL and Synthesized by using Xilinx ISE version 9.2i. The performance is compared in terms of area, delay with earlier existing architecture of Urdhava Tiryakbhyam method. The proposed work (compressor based Urdhava Tiryakbhyam method) shows improvements in terms of area and time delay. KEYWORDS: Compressor, Fixed point format, Q-format, Urdhava Tiryakbhyam. I.INTRODUCTION Vedic Mathematics is the ancient system of mathematics which was rediscovered early last century by Sri Bharati Krishna Tirthaji ( ) [1].The Sakrit word Veda mea knowledge. He organized and classified the whole of Vedic Mathematics into 16 formulae or also called as sutras. These formulae form the backbone of Vedic mathematics. Great amount of research has been done all these years to implement algorithms of Vedic mathematics on processors. Hence our focus in this work is to develop optimized hardware modules for multiplication operation. Coidering fixed point representation, 16 bit Q15 format, 32 bit Q31 format and 64 bit Q63 formats are provide required precision for most of the digital signal processing applicatio and best suited for implementation on processors. In this paper we propose the implementation of fixed point Q-format [6] high speed multiplier using Urdhava Tiryakbhyam method of Vedic mathematics. Further we have also implemented multipliers using compressor based Urdhava Tiryakbhyam method. The paper is organized into VI sectio. Section II explai fixed point arithmetic III Urdhava Tiryakbhyam method of Vedic mathematics; IV explai the architecture of proposed compressor based Urdhava multipliers; V Presents the simulation results and Comparison of Q format multipliers and lastly VI provides conclusion of the work. A. Literature Review: The application which we are coidering describes about the information about all the basic Vedic mathematics techniques [1] for various operatio. Among these techniques more preferable method is Urdhva method to describe Urdhava methodology [3] and their hardware architecture [4] details and implementation [5] presented. The algorithm to architecture mapping using floating point number representation Coumes more hardware which tends to be expeive.fixed point number representation [6] is a good option to implement at silicon level. Hence our focus in this work is to develop optimized hardware modules for multiplication operation.to performing multiplication operatio for various types of Q- formats [2] architectures (Q15, Q31, and Q63 formats). In this paper the proposed work is the implementation of compressor [7, 8] based methodology to reduce area and time delay to improve overall performance. Copyright to IJAREEIE

2 II. FIXED POINT ARITHMETIC An N-bit fixed-point number [6] can be interpreted as either: an integer (i.e.20640), a fractional number (i.e.0.78). In a 16-bit processor dynamic range in between -32,768 to 32,767. Example for integer fixed-point number: = 60000, this is an overflow. This is difficult to use in processors due to possible overflow. To overcome overflow draw back fractional fixed-point Representation will be which is suitable for DSP algorithms. An N-bit fixed point 2 s complement representation as follows. A = b 2 +b 2 + +b b 2.Equation (1) Equation (1) shows fractional fixed point representation. Fractional number range is between 1 and -1. Multiplying a fraction by a fraction always results in a fraction and will not produce an overflow (e.g., 0.99 x less than 1) Successive additio may cause overflow.to represent fractional numbers in-between -1.0 and 1-2 where N is the number of bits. A.Q- Format Representation: In general any Q-format representation is denoted by Qm.n notation where m is the number of bits for integer portion,n denotes number of bits for fractional portion Total number of bits N = m + n + 1, for signed numbers. B =-b 2 + b b 2 ( ) + b 2 ( ).Equation (2) Equation (2) shows fractional fixed point Q_format representation. Example for Q-format representation: 16-bit number(n=16) and Q2.13 format 2 bits for integer portion, 13 bits for fractional portion, 1 signed bit (MSB). Special cases: 16-bit integer number (N=16) => Q15.0 format 16-bit fractional number (N = 16) => Q0.15 format; also known as Q.15 or Q15. B. Q-Format Multiplication: When two Q15 numbers are multiplied their product is 32 bits long as illustrated in Fig. 1. The product has a redundant or extended sign bit. Since the product stored in memory should also be a Q15 number we left shift the product by one bit and the most significant 16 bits (including sign bit) is stored in the memory. Product of two Q15 numbers is Q30.So we must remember that the 32-bit product has two bits in front of the binary point. Since NxN multiplication yields 2N-1 result Addition MSB sign exteion bit typically only the most significant 15 bits (plus the sign bit) are stored back into memory, so the write operation requires a left shift by one. Fig.1. demotrates multiplication of two Q15 format numbers. The process remai same for Q31format and Q63 format. Figure.1 Multiplicatio of two Q15 format numbers yielding the product in Q15 formats itself. [2] When we want to convert a fractional number in the range of the desired Qm.n format, we multiply it with 2 n. The resultant value is truncated or rounded off to the nearest integer. Therefore a small amount of precision loss is involved which reduces as the number of bits representing the fractional part increases. We prefer rounding technique since its error bias in both positive and negative direction is same. Therefore the rounded value will be more precise. For e.g. Conversion of to Q15 format is done by multiplying it with 2 15 which equals to which when rounded gives 8602.This is stored as in a 16 bit memory location. The most significant bit indicates sign of Copyright to IJAREEIE

3 the number. If it is negative then 2 s complement method is followed to store the number. Thus a fraction is converted to an integer in a Q-format and the choice of the decimal point lies entirely in the hands of the programmer. III. URDHAVA TIRYAKBHYAM METHOD Urdhava Tiryakbhyam [3] is a Sakrit word which mea vertically and crosswire in English. The method is a general multiplication formula applicable to all cases of multiplication. It is based on a novel concept through which all partial products are generated concurrently. Figure. 2 Multiplicatio of two 4 bit numbers using Urdhava Tiryakbhyam method. [5] Fig. 2, the least significant bit (LSB) of the multiplier is multiplied with least significant bit of the multiplicand (vertical multiplication). This result forms the LSB of the product. In step 2 next higher bit of the multiplier is multiplied with the LSB of the multiplicand and the LSB of the multiplier is multiplied with the next higher bit of the multiplicand (crosswire multiplication). These two partial products are added and the LSB of the sum is the next higher bit of the final product and the remaining bits are carried to the next step the Partial products and their sums for every step can be calculated in parallel. Thus every step in fig. 2 has a corresponding expression as Follows: r0=a0b0....step (1) c1r1=a1b0+a0b1.. step (2) c2r2=c1+a2b0+a1b1 + a0b step (3) c3r3=c2+a3b0+a2b1 + a1b2 + a0b3.. step (4) c4r4=c3+a3b1+a2b2 + a1b step (5) c5r5=c4+a3b2+a2b3... step (6) c6r6=c5+a3b3...step (7) With c6r6r5r4r3r2r1r0 being the final product [5]. Hence this is the general mathematical formula applicable to all cases of multiplication and its hardware architecture is shown in fig.4.in order to multiply two 8-bit numbers using 4- bit multiplier we proceed as follows. When the numbers are multiplied according to Urdhava Tiryakbhyam (vertically and crosswire) method, we get AH AL BH BL (AH x BH) + (AH x BL + BH x AL) + (AL x BL). Thus we need four 4-bit multipliers and two adders to add the partial products and 4-bit intermediate carry generated. Since product of a 4 x 4 multiplier is 8 bits long, in every step the least significant 4 bits correspond to the product and the remaining 4 bits are carried to the next step. This process continues for 3 steps in this case. Similarly, 16 bit multiplier has four 8 x 8 multiplier and two 16 bit adders with 8 bit carry. Therefore we see that the multiplier is highly modular in nature. Hence it leads to regularity and scalability of the multiplier layout. Copyright to IJAREEIE

4 Figure.3. Hardware architecture of 4 X 4 Urdhva Tiryakbhyam multiplier [4] IV. ARCHITECTURE Q-format signed multiplier includes Urdhva integer multiplier [4] with certain modificatio as follows. A.3_2 Compressor: High speed multipliers use 3-2, 4-2 and 5-2 compressors to lower the latency of partial product reduction part [7, 8]. Compressors are to minimize delay and area which leads to increase the performance of the overall system. Compressors are generally designed by XOR-XNOR gates and multiplexers. A compressor is a device which is to reduce the operands while adding terms of partial products in multipliers. The most widely and the simplest compressor is the 3-2 compressor which is also known as a full adder. A 3-2 compressor has three inputs X1, X2, X3 and generates two Outputs they are sum and the carry bits. The block diagram of 3-2 compressor is shown in figure.4. (a) And truth table for 3-2 compressor is shown in figure.4. (b). Figure.4. (a) Block diagram of 3_2 compressor Copyright to IJAREEIE

5 a b C in sum carry Figure.4. (b) 3_2 compressor truth table Figure 4. (c) Has two XOR gates in the critical path. The sum output is generated by the second XOR and carry output is generated by the multiplexer (MUX). The equatio (3, 4, and 5) governing the conventional 3-2 compressor outputs are shown below. The conventional architectures of 3-2 compressor shown in figure 4. (c). Figure.4. (c) Conventional 3_2 compressor a +b +C in =sum+2 carry.equation (3) Sum=a b C in.. Equation (4) Carry= (a b) C in + (a b) a...equation (5) Coidering a 16 bit Q15 multiplier, the product is also a Q15 number which is 16 bits long. Figure.5.Architecture of a Q15 format multiplier. Multiplication of two Q15 numbers a and b results in a Q15 product Denoted by P in the figure. Copyright to IJAREEIE

6 Firstly, if the MSB of input is 1 then it is a negative number. Therefore 2 s complement of the number is taken before proceeding with multiplication. Since the MSB denotes sign it is excluded and a 0 is placed in this position while multiplying. A Q15 format multiplier coists of four 8 x 8 Urdhava multipliers and the resulting product is 32 bits Long as shown in fig. 5. Therefore the 32 bit product is left shifted by 1 bit to remove the redundant sign bit and only the most significant 16 bits of this product are coidered which cotitute the final product. An xor operation is performed on the input sign bits to determine the sign of the result. If the output is 1 it enables the conversion of the 16 bit final result to its 2 s compliment format indicating a negative product. Figure.6.Architecture of a Q31 format multiplier. Multiplication of two Q31 numbers a and b results in a Q31 product Denoted by P in the figure In fig. 6 but the product of a Q31 number is also a Q31number which should be 32 bits long. Therefore the 64 bit product is left shifted by 1 bit to remove the redundant sign bit and only the most significant 32 bits of this product are coidered which cotitute the final product. A xor operation is performed on the input sign bits to determine the sign of the result. If the output is 1 it enables the conversion of the 32 bit final result to its 2 s compliment format indicating a negative product. Figure.7.Architecture of a Q63 format multiplier. Multiplication of two Q63 numbers a and b results in a Q63 product Denoted by P in the figure. Copyright to IJAREEIE

7 Similarly as shown in fig. 7 but the product of a Q63 number is also a Q63 number which should be 64 bits long. Therefore the 128 bit product is left shifted by 1 bit to remove the redundant sign bit and only the most significant 64 bits of this product are coidered which cotitute the final product. A xor operation is performed on the input sign bits to determine the sign of the result. If the output is 1 it enables the conversion of the 64 bit final result to its 2 s compliment format indicating a negative product. V. SIMULATION RESULTS The proposed compressor based Urdhava tirykbhyam Q_format multiplier is designed using verilog HDL and structural form of coding. The basic block of both Q15, Q31and Q63 multipliers is a 4 x 4 Urdhava Tiryakbhyam integer multiplier which in turn is made up of two 2 x 2 multiplier blocks.. The Code is completely synthesized using Xilinx XST and Implemented on device family Virtex-5, device XC5VL50, Package FF324 with speed grade -2. A. Simulation Results For Q-format Multipliers: The design was simulated using Isim on Xilinx ISE 9.2i version. For Q15 format multiplication as shown in fig. 5. Input1 = = Input2 = = Output = = Figure.8.Simulation Result for Q15 Multiplication For Q31 format multiplication as shown in fig. 6. Input1= = Input2= = Output= = Figure.9.Simulation Result for Q31 Multiplication But the actual value of the product is Therefore precision loss is involved in this Multiplication and is found to be E -12 which is less than the resolution of Q31 representation i.e Thus it Provides 32 bit accurate products which is acceptable for most Of the DSP applicatio. For Q63 format multiplication as shown in fig. 7. Input1=0.75= Input 2= 0.25= Output=0.1875= Copyright to IJAREEIE

8 B.RTL Schematics for Q-format Multipliers: Figure.10. Simulation Result for Q63 Multiplication Fig.11.The outputs of 8X8 bit multipliers are added accordingly to obtain the 32 bits final product. Thus, in the final stage two adders are also required. The implemented RTLView of 16x16 bits Q-format Multiplier by using 8x8 blocks with the help of ModelSim Tool 6.1e. Figure.11. RTL Schematic of Q15 format multiplier. Fig.12.The outputs of 16X16 bit multipliers are added accordingly to obtain the 64 bits final product. Thus, in the final stage two adders are also required. The implemented RTL View of 32x32 bits Q-format Multiplier by using 16x16 blocks with the help of ModelSim Tool 6.1e. Figure. 12. RTL Schematic of Q31 format multiplier Fig.13.The outputs of 32X32 bit multipliers are added accordingly to obtain the 128 bits final product. Thus, in the final stage two adders are also required. The implemented RTL View of 64x64 Q-format Multiplier by using 32x32 blocks with the help of ModelSim Tool 6.1e. Copyright to IJAREEIE

9 Figure. 13. RTL Schematic of Q63 format multiplier It can be clearly noted from Table.1. That in terms of speed, the compressor based Urdhwa performs exceptionally well and is almost 1.39 times faster than the existing Urdhwa. Table. 1. Comparison of 16 bit Q15 format multiplier Algorithm Total present %of area occupied Frequen cy () Time () Urdhwa Compressor based Urdhwa It can be clearly noted from Table.2.that in terms of speed, the compressor based Urdhwa performs exceptionally well and is almost 1.39 times faster than the existing Urdhwa. Table. 2. Comparison of 32 bit Q31 format multiplier Algorithm Total present %of area occupied Frequen cy () Time () Urdhwa Compressor based Urdhwa It can be clearly noted from Table.3.that in terms of speed; the compressor based Urdhwa performs exceptionally well and is almost 1.19 times faster than the existing Urdhwa. Copyright to IJAREEIE

10 Table. 3. Comparison of 64 bit Q63 format multiplier Algorithm Total present %of area occupied Frequen cy () Time () Urdhwa Compressor based Urdhwa From table1, table2, table3 it can be clearly noted that in terms of area and time delay proposed compressor based Urdhwa gives good performance compare with Urdhwa method because by using compressor we are reducing the number of operatio comparing with adders. Compressors are also in multiplier architectures. Multipliers are structured into three functio: Partial-product generation, Partial-product accumulation and Final addition. The main source of power, delay and area came from the partial-product accumulation stage Compressors usually implement this stage because they contribute to the reduction of the partial products (reducing the number of adders at the final stage) and also contribute to reduce the critical path which is important to maintain the circuit's performance. As per the requirements we are increasing the compressor sizes (4-2compressor, 5-2 compressor etc) it gives maximum good performance. VI.CONCLUSION AND FUTURE WORK The proposed fast multiplier architecture for signed Q-format multiplicatio using compressor based Urdhava Tiryakbhyam method of Vedic mathematics. Since Q-format representation is widely in Digital Signal Processors. The proposed compressed Urdhava Tiryakbhyam method can substantially speed up the multiplication operation which is the basic hardware block. They occupy less area and faster than the Urdhava Tiryakbhyam method. Therefore the compressed Urdhava Tiryakbhyam Q-format multiplier is best suited for digital signal processing applicatio requiring faster multiplicatio. As a future work, the multiplier s performance could be tested within an ALU and also compared with several other existing multipliers. ACKNOWLEDGMENT D.srinu would like to thank Mr. S.Rambabu, Assistant professor ECE Department who had been guiding throughout the project and would like to thank Mr.G.Leennendra chowdary, Assistant professor ECE Department for supporting me in giving technical ideas about the paper and motivating me to complete the work efficiently and successfully. REFERENCES [1] Jagadguru Swami Sri Bharati Krisna Tirthaji Maharaja, Vedic Mathematics: Sixteen Simple Mathematical Formulae from the Veda Motilal Banarasidas Publishers, Delhi, 2009, pp [2] Sandesh S. Saokar, R. M. Banakarand Saroja Siddamal, High Speed Signed Multiplier for Digital Signal Processing Applicatio / IEEE [3] M. Pradhan and R. Panda, Design and Implementation of Vedic Multiplier A.M.S.E Journal, Computer Science and Statistics, France vol. 15, July 2010, pp [4] Harpreet Singh Dhillon, Abhijit Mitra, A Reduced-Bit Multiplication Algorithm for Digital Arithmetic s International Journal of Computational and Mathematical Sciences, spring 2008, pp [5] S.S. Kerur, Prakash Narchi, Jayashree C.N. Harish M.Kittur and GirishV.A, Implementation of Vedic Multiplier for Digital Signal Processing International Journal of Computer Applicatio, 2011, vol. 16, pp [6] Sen-Maw Kuo and Woon-Seng Gan, Digital Signal Processor, architectures, implementatio and applicatio Pearson PrenticeHall, 2005, pp [7]S. Veeramachaneni, K. M. Krishna, L. Avinash, S. R. Puppala, and M. Srinivas, Novel architectures for High-speed and low-power 3-2, 4-2 and 5-2 compressors in VLSI Design, Held jointly with 6th International Conference on Embedded Systems., 20th International Conference on, pp , Jan Copyright to IJAREEIE

11 [8] Nilay Nagdeve, Vishal Moyal, Ms. Archana Fande, A Simulation Based Evaluation of Different Compressors for Fast Multiplication International Journal of Scientific & Engineering Research, vol.3, issue 6, June BIOGRAPHY D.Srinu, Pursuing M.Tech in Sasi ititute of technology and engineering and doing research work on Advanced Multiplication Techniques using Multipliers for DSP Applicatio under the guidance of Mr. S.Rambabu. His areas of interests are VLSI AND EMBEDDED SYSTEM. Mr. S. Rambabu, M.Tech, Asst.Professor in the Department of Electronics and Communication Engineering, Sasi ititute of technology and Engineering, Tadepalligudem, AP. His research areas are based on VLSI. Mr.G.Leennendra Chowdary, M.Tech, Asst.Professor in the Department of Electronics and Communication Engineering, Sasi ititute of technology and Engineering, Tadepalligudem, AP. His research areas are based on VLSI AND EMBEDDED SYSTEM. Copyright to IJAREEIE