Oswal S.M 1, Prof. Miss Yogita Hon 2

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1 International Journal of Modern Trends in Engineering and Research e-issn No.: , Date: April, 2016 IMPLEMENTATION OF MULTIPLICATION ALGORITHM USING VEDIC MULTIPLICATION: A REVIEW Oswal S.M 1, Prof. Miss Yogita Hon 2 1 E&TC Department SNJB s Late Sau.K.B.Jain COE Chandwad sonalioswal270@gmail.com 2 E&TC Department SNJB s Late Sau.K.B.Jain COE Chandwad yogitarathod@gmail.com ABSTRACT -At present, it has been necessary to increase the speed of multiplier as the need of high speed processors is increasing. Multiplier is an important basic function in most fast processing system. Conventional processors need great hardware resources and take more time in multiplication operation. This paper presents high speed multiplier depending on vertical & crosswise method of Vedic mathematics. Implementation is carried on digital hardware. Vedic multiplication needs same number of addition and multiplication operations of normal multiplier using digital hardware; wherein mental calculation is the only case where it differs. Few VHDL codes have been programmed for the same. An efficient implementation of high speed multiplier using the Vedic multiplication method. In this we compare the working of the three multiplier by implementing each of them on FPGA Spartan3 board. As far as comparison is concerned, all multipliers have been tested for 8, 16 and 32 bits multiplications. In our project when we compare the path delay of all the multipliers we find that 8 bit and 16bit Urdhva algorithm gives 50% better delay than that of Nikhilam whereas 100% than that of Binary multiplier.. The result of work helps us to choose a better option between methods of vedic multiplier in fabricating different systems. Multipliers form one of the most important component of many systems. So by analyzing the working of different multipliers helps to frame a better system with less path delay. Keywords- VHDL, FPGA, Urdhva Tiryagbhyam sutra, Nikhilam Navats'caramam dasatah. I) INTRODUCTION Multiplication is one of the silicon intensive functions, especially when implemented in programmable logic. Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors etc. A systems performance is generally determined by performance of the multipliers, because the multiplier is generally the slowest element in the system. Furthermore, it is usually the most area consuming. Hence optimizing the speed and area of the multiplier is major design issue [1].Therefore there are two possible ways to speed up the multiplication reduce the number of partial products or accelerate their accumulation. A smaller number of partial products also reduces the complexity, and as a result reduces the time needed to accumulate the partial products. Multipliers are key components of many high performance systems such as FIR filters, microprocessors, digital signal processors, etc. A system s performance is generally determined by the performance of the multiplier because the multiplier is generally the slowest element in the system. Furthermore, it is generally the most area consuming.hence, optimizing the speed and area of the multiplier is a major design issue. However, area and speed are usually conflicting constraints so that improving speed results mostly in larger areas. The multiplier is a fairly large block of a computing system. The amount of circuitry involved is directly proportional to the square of its resolution i.e. A multiplier of size n bits has n2 gates. For multiplication algorithms performed in DSP applications latency and throughput are the two All rights Reserved

2 concerns from delay perspective. Latency is the real delay of computing a function, a measure of how long the inputs to a device are stable is the final result available on outputs. Throughput is the measure of how many multiplications can be performed in a given period of time; multiplier is not only a high delay block but also a major source of power dissipation. That s why if one also aims to minimize power consumption, it is of great interest to reduce the delay by using various delay optimizations. Vedic Mathematics hails from the ancient Indian scriptures called Vedas or the source of knowledge. This makes it the Easiest and fastest way to perform any mathematical calculation mentally. Vedic Mathematics is believed to be created around 1500 BC and was rediscovered between 1911 to 1918 by Sri Bharti Krishna Tirthaji ( ) who was a Sanskrit scholar, mathematician and a philosopher. In this work, Urdhva tiryakbhyam Sutra is first applied to the binary number system and is used to develop digital multiplier architecture. This Sutra also shows the effectiveness of to reduce the NXN multiplier structure into an efficient 4X4 multiplier structures[6]. Nikhilam Sutra is then discussed and is shown to be much more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller ones. The proposed multiplication algorithm is then illustrated to show its computational efficiency by taking an example of reducing a 4X4-bit multiplication to a single 2X2-bit multiplication operation[5]. II)BINARY MULTIPLIER A Binary multiplier is an electronic hardware device used in digital electronics or a computer or other electronic device to perform rapid multiplication of two numbers in binary representation (this is 11 in decimal) x 1110 (this is 14 in decimal) ====== 0000 (this is 1011 x 0) 1011 (this is 1011 x 1) 1011 (this is 1011 x 1) (this is 1011 x 1) ======= (this is 154 in decimal) 4x4 bit multiplication in Binary number system III)NIKHILAM NAVATS'CARAMAM DASATAH The formula simply means " All from 9 and the last from 10"The formula can be very effectively applied in multiplication or numbers, which are nearer to bases like 10,100,1000 i.e. to the power of 10' The procedure of multiplication using the Nikhilam involves minimum number of steps, space, time saving, and only mental calculation. The numbers taken can be either less or more than the base considered. The difference between the number and the base is termed as deviation. Deviation may be positive or negative [1]. Table 1. Number, Base and Deviation Number Base Number-base Deviation The formula simply means : all from 9 and the last from 10. The formula can be very effectively applied in multiplication of numbers, which are nearer to bases like 10, 100, 1000 i.e., to the powers of 10. The procedure of multiplication using the Nikhilam involves minimum number of steps, space, time saving and only mental All rights Reserved 816

3 The difference between the number and the base is termed as deviation. Deviation may be positive or negative. Positive deviation is written without the positive sign and the negative deviation, is written using Rekhank (a bar on the number). this Sutra is explained by doing the multiplication of two decimal numbers IV)URDHVA TIRYAGBHYAM SUTRA The multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication. It literally means Vertically and crosswise. It is based on a novel concept through which the generation of all partial products can be done with the concurrent addition of these partial products. The parallelism in generation of partial products and their summation is obtained using Urdhava Triyakbhyam explained in fig 1. The algorithm can be generalized for n x n bit number. Since the partial products and their sums are calculated in parallel, the multiplier is independent of the clock frequency of the processor. Thus the multiplier will require the same amount of time to calculate the product and hence is independent of the clock frequency [1]. The processing power of multiplier can easily be increased by increasing the input and output data bus widths since it has a quite a regular structure. Due to its regular structure, it can be easily layout in a silicon chip. The Multiplier has the advantage that as the number of bits increases, gate delay and area increases very slowly as compared to other multipliers. Therefore it is time, space and power efficient. It is demonstrated that this architecture is quite efficient in terms of silicon area/speed [3][6][11]. Symbolically we can represent the whole process as follows: (1*1)6(1*2+1*4)8(4*2) =168 Fig.1 Multiplication scheme using conventional method (B) Multiplication scheme using Urdhva Tiryagbhyam sutra with line diagram. Looking at figure 2, one can easily realize that Vedic method probably makes difference for mental calculations only. For mental calculations it can be proved more convenient; as we can easily visualize Vedic multiplication line diagram. [3]. V) Proposed All rights Reserved 817

4 Conventional multiplier takes more time to execute, hence delay is increases. Reducing the delay of multiplier can increases the speed of multiplier which is essential requirement in many applications. Also conventional processor requires substantially more hardware resources in the multiplication operation, rather than addition and subtraction. Vedic multiplier is excellent solution to solve the problem of maximum delay. The proposed method focuses on using the advantages of minimum delay of Vedic Multiplier(VM) based on Vertically & Crosswise method for the multiplier application. This process has been seen to be large optimization of speed. Vedic mathematics is Fig: 2 Hardware implementation of 4x4 Bit Vedic Urdhva Tiryakbhyam Multiplier With c6r6r5r4r3r2r1r0 being the final product [3] [4] [8]. general multiplication formulae equally applicable to all cases of multiplication. It is based on generating all partial products and their sum in one step. demand for high speed processing has been increasing as a result of expanding computer and signal processing applications. Higher throughput arithmetic operations are important to achieve the desired performance in many real-time signal and image processing applications [2]. The designing of Vedic Multiplier is different from conventional multiplier like array multipliers. Even though both multiplier have the same number of multiplications, the array multiplier use some small blocks like shift and add for designing higher order multipliers. Vedic Multiplier is designed in VHDL, as it is more effective in structural way of coding. The individual block is implemented using VHDL language. The performance of each multiplier is determined using the software ModelSim6.7 and the timing report is obtained by synthesis in Spartan3[3]. As number of bits increases in input, a small modification is required. Divide the total number of bits of each input into two equal parts [8]. A[0:3] P (7:0) B[0:3] 4 X 4 VEDIC MULTIPLER Fig.3: Block representation of 4x4 Vedic Multiplier VI)CONCLUSION In many real-time DSP applications number of complex multiplications are involved, in which high performance is a prime target. However, achieving this may be done at the expense of area, power dissipation and accuracy. The performance in terms of throughput of the processor is limited by the multiplication. So efforts have to be made to decrease the number of multipliers and to increase their speed. A high speed complex number multiplier design using Vedic Mathematics (Urdhva Tiryakbhyam sutra) is implemented using VHDL. This sutra is applicable to all cases All rights Reserved 818

5 multiplication. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement high speed complex multiplier efficiently in digital signal processing algorithms. REFERENCES [1]Himanshu Thapliyal and M.B. Srinivas, High Speed Efficient N X N Bit Parallel Hierarchical Overlay Multiplier Architecture Based On Ancient Indian Vedic Mathematics Transactions On Engineering, Computing And Technology V2 December 2004 Issn [2] Pushpalata Verma Design of 4x4 bit Vedic Multiplier using EDA Tool International Journal of Computer Applications ( ) Volume 48 No.20, June 2012,Raipur, Chhattisgarh, India. [3] Parth Mehta, Dhanashri Gawali, Conventional versus Vedic mathematical method for Hardware implementation of a multiplier 2009 International Conference on Advances in Computing, Control, and Telecommunication Technologies. [4] Sarita Singh, Sachin Mittal, VHDL Design and Implementation for Optimum Delay & Area for Multiplier & Accumulator Unit by 32-Bit Sequential Multiplier, Volume3Issue5, International Journal of Engineering Trends and Technology,2012. [5] Swami Bharati Krshna Tirthaji, Vedic Mathematics. Delhi: Motilal Banarsidass Publishers, [6] L. Sriraman, T. N. Prabakar, Design and Implementation of Two Variable Multiplier Using KCM and Vedic Mathematics, 1st Conf. on Recent Advances in Information Technology RAIT [7] Kavita, Umesh Goyal, Performance Analysis of Various Vedic Techniques for Multiplication International Journal of Engineering Trends and Technology- Volume4Issue [8] Moumita Ghosh, Design And Implementation Of Different Multipliers Using Vhdl Department of Electronics and Communication Engineering National Institute of Technology, Rourkela, [9] Kavita, Umesh Goyal, Performance Analysis of Various Vedic Techniques for Multiplication International Journal of Engineering Trends and Technology- Volume4Issue [10] Kishore Kumar, A.Rajakumari, Modified Architecture of Vedic Multiplier for High Speed Applications, International Journal of Engineering Research & Technology, Vol. 1 Issue 6, August [11] Ch. Harish Kumar, Implementation and Analysis of Power, Area and Delay of array, urdhva,nikhilam vedic mulipliers International Journal of Scientific and Research Publications, Volume 3, Issue 1, January ISSN All rights Reserved 819

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